CN102157363A - Ion implantation method of substrate back of power device - Google Patents
Ion implantation method of substrate back of power device Download PDFInfo
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- CN102157363A CN102157363A CN 201110054844 CN201110054844A CN102157363A CN 102157363 A CN102157363 A CN 102157363A CN 201110054844 CN201110054844 CN 201110054844 CN 201110054844 A CN201110054844 A CN 201110054844A CN 102157363 A CN102157363 A CN 102157363A
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Abstract
The invention relates to an ion implantation method of a substrate back of a power device, belonging to the technical field of semiconductor power devices. The ion implantation method disclosed by the invention comprises the following steps of: after finishing steps of a front face process of the power device, thinning the substrate back to an impurity implantation layer and then depositing a metal aluminum layer by utilizing a corrosion or grinding method after ion implantation (thinning or non-thinning process can be carried out on the substrate back before the ion implantation) and ion activation are finished, but not directly carrying out metal aluminum layer deposition like the traditional process. Therefore, the contact resistance between the subsequently deposited metal aluminum and the substrate can be reduced, unnecessary parasitic multi-layer structures can be eliminated, the leakage current and the on-state voltage drop of the power device are reduced, and the switching time of the power device is shortened. The ion implantation method of the substrate back of the power device, disclosed by the invention, is suitable for semiconductor power devices made from semiconductor materials, such as bulk-silicon, silicon carbide, gallium arsenide, indium phosphide or germanium silicon and the like.
Description
Technical field
The invention belongs to the semiconductor power device technology field, relate to the semiconductor power device manufacturing technology.
Background technology
Power semiconductor technologies is the core of power electronic technology, development along with microelectric technique, the modern power semiconductor technologies that with gated power device and smart-power IC is representative obtained developing rapidly from the eighties in 20th century, and then had greatly promoted the progress of power electronic technology.And the continuous progress of power electronic technology impels power semiconductor technologies to develop to high frequency, high temperature, high pressure, high-power and intelligent, systematization direction conversely.Power semiconductor has passed through 40 years of development, on the device manufacturing technology, improve constantly, experienced with the thyristor is the discrete device of representative, with turn-off thyristor (GTO), huge transistor (GTR), power MOSFET and igbt (IGBT) is the power IC device (PID) of representative, is power integrated circuit three developing periods such as (SPIC) of representative with intelligent power integrated circuit (SSPIC), high-voltage power integrated circuit (HVIC).
Press powerful power electronic device to form the technical market that GTO, IGCT, IGBT, IEGT vie each other, constantly bring forth new ideas in using at present.Manufacturing process by power device can realize device architecture change and parameter optimization, and these devices all have the PNPN four-layer structure.With IGBT is example, and the PT-IGBT that removes initial exploitation is at P
+The growing high resistant thick epitaxial layer is made on the substrate, and other structure adopts slice technique mostly.Not only will carry out front processing and also will carry out back side processing in the manufacturing process of power device, positive processing generally is to make MOS device and conventional VDMOS technology roughly the same; Back side process technology is to be core with the slice technique, need carry out technical processs such as back side ion injection, thermal annealing and back face metalization and finish.With NPT-IGBT is example, typical process flow is: select＜100〉crystal orientation N type silicon substrate, long field oxide is made terminal part, active area etching and long grid oxygen, the deposit polysilicon gate, the etch polysilicon grid inject P type base and annealing, inject N type source region and annealing, thick oxide layer, the etching contact hole injects P
+The tagma, the deposit front metal, the etching front metal, thinning back side injects back side P type collector electrode, P type collector electrode thermal annealing, back side depositing metal Al, smelting furnace sintering, cooling, back side cloth metal Ti/Ni/Ag.
It is a kind ofly to introduce the impurity of may command quantity to substrate that back side ion injects, and changing the method for its electrology characteristic, thereby forms needed knot.But after the incident ion of certain energy enters crystal, because and the electronics in the crystal and nuclear interaction and terminate in a certain position in the crystal behind the degradedness, these ions often are in interstitial site, to not contribution of charge carrier, and the injection meeting of energetic ion is shone into certain damage lattice.Ion injects the damage of shining to crystal, will directly influence the conductivity of semiconductor device.As the increase of scattering center, carrier mobility is descended, increasing of defective reduces the life-span of non equilibrium carrier; In some cases, damage to form electric activity center, change carrier concentration; The damage of implanted layer crystal simultaneously also can make electricity lead decline, and P-N knot reverse leakage current increases or the like.
Inject the defective of bringing and activate the impurity that injects in order to repair the back ion, just need carry out annealing in process.The annealing of silicon chip has two kinds of basic skills: high temperature furnace annealing and rapid thermal annealing (RTA), what adopt usually is the method for high temperature furnace annealing, silicon chip can only be heated to about 800 ℃～1000 ℃ in high temperature furnace, and continue about 30 minutes of annealing.Heat-treat under such temperature and time, can cause the diffusion of impurity excessive, influence Impurity Distribution, this is that the modern IC manufacturing is not wished to see.And rapid thermal annealing (RTA) is with the programming rate that is exceedingly fast with at target temperature transient continuous annealing time silicon chip to be carried out annealing in process, carries out in rapid thermal treatment machine (RTP) usually.Heat up fast and the transient continuous annealing time can and minimize between the diffusion of impurities three at reparation, the activator impurity of lattice defect and obtains optimization, thereby RTA is activator impurity and reduces the best approach that impurity distributes again.
Rapid thermal anneal process can be divided into three major types according to the heating type: heat insulation-type, heat flow flux type and isothermal.The thermal source of heat insulation-type equipment is the wide beam coherent source normally, as excimer laser.Although this annealing system is the shortest required heating time under identical temperature, there are several serious defectives in it, comprises the control difficulty of temperature and time, and longitudinal temperature gradient is big and equipment cost is high.The heat flow flux type system adopts high intensity point source, as electron beam or the laser through focusing on, silicon chip is scanned.But, the defective that horizontal hot inhomogeneities causes makes because making it can't be applied to IC.Isothermal system adopts wide beam radiation heating disk many seconds, and the temperature gradient that isothermal system causes on disk horizontal and vertical is minimum.This isothermal system generally adopts incoherent light source, as one group of tungsten sodium lamp.Because the advantage of isothermal system, nearly all commercial fast thermal annealing system (RTP) all adopts isothermal design now.
At present, the main flow manufacturing process (as shown in Figure 1) of various power devices is after the positive technology of finishing silicon chip (wafer), carry out silicon chip back technology, inject and annealing, form the metal level at the silicon chip back side at the evaporation of the silicon chip back side or splash-proofing sputtering metal as the impurity at the attenuate at the silicon chip back side, the silicon chip back side, finish back process, obtain power device.
Wherein, the back metal of device and the contact resistance (Rc between the silicon chip, contact resistance) is an important device parameters,, back side doped region and back metal well contacted be one of target that the device back process pursued for power device.The main flow manufacturing process of aforementioned various power devices all is directly to make metal electrode after foreign ion injects and anneals, yet, after silicon chip back side impurity injects, annealed activation can form the Impurity Distribution layer of certain depth, if be not thinned to back side impurity layer, can cause back metal and implanted dopant district can not form good Ohmic contact, bring unnecessary parasitic sandwich construction, make leakage current, on-state voltage drop and the switching time of power device become big, the power device that directly causes being developed can not be used.
Summary of the invention
The object of the present invention is to provide a kind of ion injection method of power device substrate back, impurity injects and the employing solvent carries out corroding method to the silicon chip back side by improving, the good contact that the metal of subsequent growth can be obtained with back side doped region to reduce the contact resistance between back metal and the silicon chip, eliminate unnecessary parasitic sandwich construction, leakage current, on-state voltage drop and the switching time of power device are reduced.
Technical solution of the present invention is as follows:
A kind of ion injection method of power device substrate back, as shown in Figure 2, after finishing power device front processing step, the operation that comprises the steps:
Step 1: inject boron or phosphorus impurities ion at the power device substrate back;
Step 2: foreign ion activates;
Step 3: the power device substrate back is thinned to the impurity implanted layer;
Step 4: adopt sputter or method of evaporating at power device substrate back growing metal aluminium lamination.
In the such scheme, when step 1 was injected boron or phosphorus impurities ion at the power device substrate back, the implantation dosage of foreign ion was 1 * 10
13～2 * 10
15Cm
-2, energy range is 30Kev～300Kev, injects the degree of depth to be
The present invention has adopted the usually bigger injection energy of ion implantation technology, and making ion inject the degree of depth increases, when helping step 3 pair power device substrate back and carrying out attenuate, to the control of the attenuate degree of depth and speed; Also can adopt the injection energy that progressively increases, help foreign ion like this and successively distribute, when step 2 pair foreign ion activates, make foreign ion obtain good diffusion and distribution.
In the technique scheme, when step 2 pair foreign ion activates, can adopt rapid thermal anneal process or high temperature furnace annealing process.During the utilization rapid thermal annealing, annealing temperature is between 900 ℃～1100 ℃, and annealing time is 5-60s; During the annealing of utilization high temperature furnace, annealing temperature is between 800 ℃～1000 ℃, and annealing time is 20-40min.
In the technique scheme, when step 3 pair power device substrate back carries out attenuate, can adopt etching process or grinding technics, the power device substrate back is thinned to the impurity implanted layer, can make metal aluminium lamination and back side doped region form good Ohmic contact.
Adopt sputter or method of evaporating behind power device substrate back growing metal aluminium lamination in step 4, also need usually at aluminium lamination surface other metal or alloy of evaporation as final electrode, such as: titanium/nickel/silver; Chromium/yellow gold; Chromium/nickel/silver; Titanium/nickel/gold etc.
The ion injection method of a kind of power device substrate back provided by the invention, finish on the positive technology basis, finish ion inject (ion can carry out attenuate or non-reduction processing to substrate back before injecting) and ion-activated after, directly carry out the deposit of metal aluminium lamination unlike traditional handicraft, but adopt corrosion or abrasive method that substrate back is thinned to after the impurity implanted layer depositing metal aluminium lamination again, can reduce the metallic aluminium of subsequent deposition and the contact resistance between the substrate like this, eliminate unnecessary parasitic sandwich construction, make the leakage current of power device, on-state voltage drop and switching time reduce.The present invention is applicable to the power semiconductor of semi-conducting material manufacturings such as body silicon, carborundum, GaAs, indium phosphide or germanium silicon.
Description of drawings
Fig. 1 is an existing power device main flow back side injection technology schematic flow sheet.
Fig. 2 is the ion injection method schematic flow sheet of the power device substrate back that proposes of the present invention.
Embodiment
A kind of ion injection method of power device substrate back, as shown in Figure 2, after finishing power device front processing step, the operation that comprises the steps:
Step 1: inject boron or phosphorus impurities ion at the power device substrate back;
Step 2: foreign ion activates;
Step 3: the power device substrate back is thinned to the impurity implanted layer;
Step 4: adopt sputter or method of evaporating at power device substrate back growing metal aluminium lamination.
In the such scheme, when step 1 was injected boron or phosphorus impurities ion at the power device substrate back, the implantation dosage of foreign ion was 1 * 10
13～2 * 10
15Cm
-2, energy range is 30Kev～300Kev, injects the degree of depth to be
The present invention has adopted the usually bigger injection energy of ion implantation technology, and making ion inject the degree of depth increases, when helping step 3 pair power device substrate back and carrying out attenuate, to the control of the attenuate degree of depth and speed; Also can adopt the injection energy that progressively increases, help foreign ion like this and successively distribute, when step 2 pair foreign ion activates, make foreign ion obtain good diffusion and distribution.
In the technique scheme, when step 2 pair foreign ion activates, can adopt rapid thermal anneal process or high temperature furnace annealing process.During the utilization rapid thermal annealing, annealing temperature is between 900 ℃～1100 ℃, and annealing time is 5-60s; During the annealing of utilization high temperature furnace, annealing temperature is between 800 ℃～1000 ℃, and annealing time is 20-40min.
In the technique scheme, when step 3 pair power device substrate back carries out attenuate, can adopt etching process or grinding technics, the power device substrate back is thinned to the impurity implanted layer, can make metal aluminium lamination and back side doped region form good Ohmic contact.
Adopt sputter or method of evaporating behind power device substrate back growing metal aluminium lamination in step 4, also need usually at aluminium lamination surface other metal or alloy of evaporation as final electrode, such as: titanium/nickel/silver; Chromium/yellow gold; Chromium/nickel/silver; Titanium/nickel/gold etc.
The present invention finishes on the positive technology basis, finish ion inject (ion can carry out attenuate or non-reduction processing to substrate back before injecting) and ion-activated after, directly carry out the deposit of metal aluminium lamination unlike traditional handicraft, but adopt corrosion or abrasive method that substrate back is thinned to after the impurity implanted layer depositing metal aluminium lamination again, can reduce the metallic aluminium of subsequent deposition and the contact resistance between the substrate like this, eliminate unnecessary parasitic sandwich construction, leakage current, on-state voltage drop and the switching time of power device are reduced.The present invention is applicable to the power semiconductor of semi-conducting material manufacturings such as body silicon, carborundum, GaAs, indium phosphide or germanium silicon.
Should illustrate, every based on variation of the unsubstantiality on the technical solution of the present invention and improvement in the present technique field, should not get rid of outside protection scope of the present invention.
Claims (6)
1. the ion injection method of a power device substrate back, after finishing power device front processing step, the operation that comprises the steps:
Step 1: inject boron or phosphorus impurities ion at the power device substrate back;
Step 2: foreign ion activates;
Step 3: the power device substrate back is thinned to the impurity implanted layer;
Step 4: adopt sputter or method of evaporating at power device substrate back growing metal aluminium lamination.
2. the ion injection method of power device substrate back according to claim 1 is characterized in that, when step 1 was injected boron or phosphorus impurities ion at the power device substrate back, the implantation dosage of foreign ion was 1 * 10
13～2 * 10
15Cm
-2, energy range is 30Kev～300Kev, injects the degree of depth to be
3. the ion injection method of power device substrate back according to claim 1 is characterized in that, when step 2 pair foreign ion activates, adopts rapid thermal anneal process or high temperature furnace annealing process.
4. the ion injection method of power device substrate back according to claim 3 is characterized in that, the annealing temperature of described rapid thermal anneal process is between 900 ℃～1100 ℃, and annealing time is 5-60s.
5. the ion injection method of power device substrate back according to claim 3 is characterized in that, the annealing temperature of described high temperature furnace annealing process is between 800 ℃～1000 ℃, and annealing time is 20-40min.
6. the ion injection method of power device substrate back according to claim 1 is characterized in that, the process when step 3 pair power device substrate back carries out attenuate is etching process or grinding technics.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522326A (en) * | 2011-12-14 | 2012-06-27 | 杭州立昂微电子股份有限公司 | Production method of semiconductor discrete device back side metal suitable for screen printing |
| CN103050397A (en) * | 2011-10-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | Process implementation method of epitaxial field barrier layer at back of IGBT (Insulated Gate Bipolar Translator) device |
| CN103700586A (en) * | 2013-12-18 | 2014-04-02 | 无锡中微晶园电子有限公司 | Method for increasing back injection impurity activation rate |
| CN104112680A (en) * | 2013-04-22 | 2014-10-22 | 无锡华润上华半导体有限公司 | Semiconductor device back manufacturing process |
| CN106571402A (en) * | 2016-11-18 | 2017-04-19 | 吉林瑞能半导体有限公司 | Fast recovery diode and manufacturing method thereof |
| CN107636806A (en) * | 2015-04-24 | 2018-01-26 | Abb瑞士股份有限公司 | The power semiconductor of top-level metallic design with thickness and the method for manufacturing such power semiconductor |
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
| US11270957B2 (en) | 2018-02-07 | 2022-03-08 | Stmicroelectronics (Rousset) Sas | Method for detecting a breach of the integrity of a semiconductor substrate of an integrated circuit from its rear face, and corresponding device |
| CN114300581A (en) * | 2021-12-31 | 2022-04-08 | 北海惠科半导体科技有限公司 | Method for manufacturing photosensitive element and semiconductor device |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050397A (en) * | 2011-10-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | Process implementation method of epitaxial field barrier layer at back of IGBT (Insulated Gate Bipolar Translator) device |
| CN102522326A (en) * | 2011-12-14 | 2012-06-27 | 杭州立昂微电子股份有限公司 | Production method of semiconductor discrete device back side metal suitable for screen printing |
| CN102522326B (en) * | 2011-12-14 | 2014-09-24 | 杭州立昂微电子股份有限公司 | Production method of semiconductor discrete device back side metal suitable for screen printing |
| CN104112680A (en) * | 2013-04-22 | 2014-10-22 | 无锡华润上华半导体有限公司 | Semiconductor device back manufacturing process |
| CN103700586A (en) * | 2013-12-18 | 2014-04-02 | 无锡中微晶园电子有限公司 | Method for increasing back injection impurity activation rate |
| CN107636806A (en) * | 2015-04-24 | 2018-01-26 | Abb瑞士股份有限公司 | The power semiconductor of top-level metallic design with thickness and the method for manufacturing such power semiconductor |
| CN106571402A (en) * | 2016-11-18 | 2017-04-19 | 吉林瑞能半导体有限公司 | Fast recovery diode and manufacturing method thereof |
| CN106571402B (en) * | 2016-11-18 | 2024-03-29 | 吉林瑞能半导体有限公司 | Fast recovery power diode and manufacturing method thereof |
| US11270957B2 (en) | 2018-02-07 | 2022-03-08 | Stmicroelectronics (Rousset) Sas | Method for detecting a breach of the integrity of a semiconductor substrate of an integrated circuit from its rear face, and corresponding device |
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
| CN109659236B (en) * | 2018-12-17 | 2022-08-09 | 吉林华微电子股份有限公司 | Process method for reducing VDMOS recovery time and VDMOS semiconductor device thereof |
| CN114300581A (en) * | 2021-12-31 | 2022-04-08 | 北海惠科半导体科技有限公司 | Method for manufacturing photosensitive element and semiconductor device |
| CN114300581B (en) * | 2021-12-31 | 2024-05-17 | 北海惠科半导体科技有限公司 | Method for manufacturing photosensitive element and semiconductor device |
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