JP2010283166A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To impart gettering capability to a semiconductor device which is thinned in a device post-step and has a polished rear surface. <P>SOLUTION: The manufacturing method includes: a rear surface grinding step S31 for grinding the rear surface of a silicon substrate to make thickness to ≤100 μm; a rear surface polishing step S32 for polishing the rear surface of the ground silicon substrate; an ion implantation step S33 for executing ion implantation of boron or n-type dopant to the ground rear surface of the silicon substrate; and an activating step S34 for activating the boron or n-type dopant which has been implanted by heating the rear surface of the silicon substrate. According to this method, contamination due to heavy metal to be introduced in the device post-step is captured to the rear surface of the silicon substrate by a gettering effect of activated ion species. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for mounting on a multichip package (MCP).

  One of the problems in the semiconductor process is that heavy metals as impurities are mixed in the silicon wafer. When heavy metals diffuse into a device region formed on the surface side of a silicon wafer, device characteristics such as pause time failure, retention failure, junction leak failure, and dielectric breakdown of the oxide film are significantly adversely affected. For this reason, in order to suppress the heavy metal mixed in the silicon wafer from diffusing into the device region, the gettering method is generally adopted. Gettering is aimed at preventing heavy metal contamination in a device pre-process for forming a device on the surface of a silicon substrate.

  On the other hand, heavy metal contamination in post-device processes such as thinning of the silicon substrate, wire bonding, or resin encapsulation performed after the pre-device process has not been particularly emphasized. This is a process of grinding and removing the back surface of the silicon wafer in the early stage of the device post-process. Scratches and damage introduced during the back surface grinding act as a gettering source by strong extrinsic gettering (EG). Because.

  However, the final chip thickness is becoming thinner year by year, and in particular, the chip mounted on the MCP is often made thinner to 100 μm or less, and depending on the product, it is currently made thinner to 25 μm or less, and in the future it will be 10 μm or less. Both are predicted. When the thickness of the chip is reduced to 100 μm or less, there arises a problem that the silicon wafer is easily broken due to damage during back grinding. In order to solve such a problem, it is necessary to newly add a process of removing damage after the back surface grinding, that is, a back surface polishing process by the CMP method.

  However, if the damage on the back surface of the silicon wafer is removed by back surface polishing, the back surface gettering source also disappears, and the EG effect is lost. Moreover, since a thin silicon wafer has a thin intrinsic gettering (IG) layer, a sufficient IG effect cannot be expected with a normal IG layer formed of oxygen precipitates. More specifically, even in the case of an epitaxial wafer or silicon wafer using the IG method, a DZ layer having no oxygen precipitation nuclei including the thickness of the epitaxial film is formed by heat treatment to have a thickness of 10 μm or more from the wafer surface. When the final film thickness of the chip becomes thinner, the IG layer hardly exists and the impurity metal generated in the device post-process cannot be gettered at all.

  As described above, in the thin semiconductor device in which the back surface of the silicon wafer is polished, the problem of heavy metal contamination in the device post-process is beginning to become apparent.

  In this regard, Patent Document 1 discloses a technique for providing gettering capability to a thinned wafer back surface by various methods. For example, a method of depositing a polycrystalline silicon film or nitride film on the back surface of a thinned silicon wafer, a method of damaging the back surface using silica particles, a method of forming a damage layer on the back surface by ion implantation, etc. ing.

JP 2006-41258 A

  However, since deposition of a polycrystalline silicon film or a nitride film requires a film forming apparatus such as a CVD apparatus, it is not practical for a mass-produced product to form these in a device post-process. Further, the method of damaging the back surface using silica particles is considered to be effective if the chip thickness is thick to some extent, but as already explained, the final chip thickness is 100 μm or less, and in the future 10 μm. If the thickness is reduced to a certain extent, the bending strength is reduced due to the introduction of physical damage due to silica particles and the like, and the problem of chip cracking occurs. Furthermore, it is difficult to obtain a sufficient gettering capability only with a damaged layer by ion implantation.

  The present invention has been made to solve such problems.

  A method for manufacturing a semiconductor device according to the present invention includes a thinning step of removing a part of a silicon substrate having a semiconductor element formed on a front surface from the back side, thereby reducing the thickness of the silicon substrate to 100 μm or less. A back surface polishing step for polishing the back surface of the silicon substrate; and an ion implantation step for ion-implanting boron or an n-type dopant into the polished back surface of the silicon substrate.

  In the present invention, if an activation step of activating the implanted boron or n-type dopant by heating the back surface of the silicon substrate is further provided, boron or n-type dopant implanted into the back surface of the silicon substrate. Thus, not only damage due to ion implantation but also gettering effect due to activated ion species can be obtained. In other words, when boron is used as the ion species, boron existing at the time of implantation exists at the interstitial position and the lattice position, and by performing heat treatment, the boron at the interstitial position moves to the lattice position. Since boron contained in the metal has a negative charge, it can capture heavy metals diffusing in the form of cations such as Cu. In addition, when an n-type dopant is used as the ion species, it has a positive charge by moving to the lattice position, and therefore, it is considered to inhibit cations entering from the outside. Accordingly, since the solid solubility of Cu is reduced in the n-type substrate, it is effective as a barrier for heavy metals entering from the back surface.

In the ion implantation step, it is preferable that the dose of boron or n-type dopant be 1 × 10 ¹³ atoms / cm ² or more and 1 × 10 ¹⁵ atoms / cm ² or less. According to this, it becomes possible to effectively exhibit the gettering ability by the activated ionic species without significantly reducing the productivity.

  In the present invention, the activation step is preferably performed using an apparatus for heating the back surface of the silicon substrate on one side. According to this, the back surface of the silicon substrate can be heated while suppressing a temperature rise on the surface of the silicon substrate.

  In this case, the activation step is preferably performed under the condition that the surface temperature of the silicon substrate is equal to or lower than the device heat resistance temperature. The device heat-resistant temperature refers to a temperature at which various devices formed on the surface of a silicon substrate such as a semiconductor element such as a transistor, a passive element such as a cell capacitor, and a metal wiring do not deteriorate. Therefore, as long as the temperature of the surface of the silicon substrate is equal to or lower than the device heat resistance temperature, the temperature of the back surface of the silicon substrate may exceed the device heat resistance temperature.

  In addition, the ion implantation process and the activation process are performed in a state where the back grind protective tape is attached to the surface of the silicon substrate. In the activation process, heating is performed under the condition that the temperature of the back grind protective tape is lower than the heat resistant temperature. It is more preferable. The heat resistant temperature of the back grind protective tape is a temperature at which the back grind protective tape deteriorates. Since the thinned silicon wafer is difficult to handle unless the back grind protective tape is applied, it is necessary to perform the activation process at a temperature below which the back grind protective tape does not deteriorate. It is. Therefore, as long as the temperature of the back grind protective tape is equal to or lower than the heat resistant temperature, the temperature of the back surface of the silicon substrate may exceed the heat resistant temperature of the back grind protective tape.

  As described above, according to the present invention, effective gettering is achieved by the activated ion species without using a film forming apparatus such as a CVD apparatus in the post-device process or physically damaging the back surface of the chip. Can be performed. For this reason, the heavy metal adhering to the back surface of the silicon substrate when the back surface polishing or the like is performed remains on the back surface, and diffusion to the device region is prevented. As a result, it is possible to increase the yield of semiconductor devices thinned to 100 μm or less while preventing a significant increase in manufacturing costs in the device post-process and a reduction in the bending strength of the chip.

1 is a schematic cross-sectional view illustrating a semiconductor device 10 structure according to a preferred embodiment of the present invention. It is a schematic sectional drawing which shows the structure of the semiconductor device 10 by a modification. 1 is a schematic cross-sectional view showing a structure of an MCP 20 using a semiconductor device 10. 4 is a flowchart for roughly explaining a method for manufacturing the semiconductor device 10. It is a flowchart for demonstrating a device back process (step S30).

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view illustrating the structure of a semiconductor device 10 according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device 10 according to the present embodiment includes a silicon substrate 11, a device region 12 provided on the front surface 11 a side of the silicon substrate 11, and gettering provided on the back surface 11 b side of the silicon substrate 11. It is constituted by the layer 13. The thickness of the silicon substrate 11 is reduced to 100 μm or less, which makes it suitable for mounting on an MCP. The back surface 11b of the silicon substrate 11 is mirror-polished. Thereby, although the total thickness is reduced to 100 μm or less, the bending strength is ensured, so that the chip is prevented from cracking.

The silicon substrate 11 is not particularly limited, but is a so-called P-substrate doped with boron, and the specific resistance of the silicon substrate 11 based on the boron concentration is adjusted to about 20 Ω · cm. Although not particularly limited, the initial oxygen concentration of the silicon substrate 11 is preferably 7 × 10 ¹⁷ atoms / cm ³ or more. This is because the oxygen precipitate formed by the heat treatment functions as a gettering source for heavy metals such as Cu and Ni. The oxygen precipitation heat treatment for forming oxygen precipitates on the silicon substrate 11 may be performed before the device pre-process, or may be substituted by a thermal process in the device pre-process.

  The device region 12 is a region where a semiconductor element such as a MOS transistor, a passive element such as a cell capacitor, and a metal wiring are formed. Among these, at least the semiconductor element is formed on the surface layer portion including the surface 11 a of the silicon substrate 11. Further, the metal wiring and the like are formed above the surface 11a of the silicon substrate 11. Although the boundary between the device region 12 and other regions in the silicon substrate 11 is not necessarily clear, the thickness of the device region 12 can be defined as the maximum depth of the depletion layer. The maximum depth of the depletion layer depends on the device design, but is about 10 μm, for example.

  The device configuration formed in the device region 12 differs depending on the type of the semiconductor device 10. For example, examples of the semiconductor device 10 include logic devices such as MPU and DSP, and memory devices such as DRAM and flash memory. For this reason, the semiconductor device 10 has different device heat resistance temperatures depending on the type.

  The gettering layer 13 is a part of the silicon substrate 11 and is provided on the back surface 11b side. The gettering layer 13 is formed by implanting boron or n-type dopant subjected to activation treatment into the silicon substrate 11. Here, when the ion species implanted into the gettering layer 13 is boron, heavy metals that diffuse in the form of cations such as Cu can be captured by the activated boron ions. In addition, when the ion species implanted into the gettering layer 13 is an n-type dopant, the solid solubility of heavy metals diffusing in the form of cations such as Cu is reduced by the activated n-type dopant. Effective as a barrier for heavy metals entering from the back side. An example of the n-type dopant is phosphorus. The thickness of the gettering layer 13 is not particularly limited as long as it does not affect the device region 12.

The dose of the gettering layer 13 is preferably set to 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less, preferably 1 × 10 ¹³ atoms / cm ² or more and 1 × 10 ¹⁵ atoms / cm 2. It is more preferable to set it to ² or less. This is because if the dose amount is less than 1 × 10 ¹³ atoms / cm ² , the gettering ability cannot be exhibited effectively, and the dose amount exceeds 5 × 10 ¹⁵ atoms / cm ^2. However, since further effects cannot be obtained, considering the productivity, the dose of the gettering layer 13 is in the above range, particularly 1 × 10 ¹³ atoms / cm ² or more and 1 × 10 ¹⁵ atoms / cm ^2. If set to the following, it is possible to obtain a high gettering effect without significantly reducing the productivity.

  The gettering effect by the gettering layer 13 is obtained not only by the boron or n-type dopant subjected to the activation process but also by damage caused to the crystal lattice by ion implantation. The gettering effect due to damage is effective not only for heavy metals that diffuse in the form of cations such as Cu, but also for those that diffuse in silicon in an electrically neutral state, such as Ni. That is, various heavy metals can be effectively captured by these two gettering effects.

The above is the configuration of the semiconductor device 10. The configuration of the semiconductor device 10 is not limited to the configuration shown in FIG. 1. For example, as shown in FIG. 2, an epitaxial film 14 may be provided on the surface 11 a of the silicon substrate 11. In this case, the device region 12 is formed on the surface layer of the epitaxial film 14. When such an epitaxial film 14 is used, the dopant species and dopant concentration to the silicon substrate 11 are not particularly limited, but it is preferable to use a so-called P + substrate doped with a high concentration of boron. According to this, in addition to the gettering effect by the gettering layer 13, the gettering effect by boron contained in the silicon substrate 11 is also obtained. In this case, the dose of boron is preferably 1.2 × 10 ¹⁷ atoms / cm ³ or more and 5.5 × 10 ¹⁹ atoms / cm ³ or less (2 mΩ · cm to 200 mΩ · cm), preferably 4 × 10. More preferably, it is ¹⁷ atoms / cm ³ or more and less than 1 × 10 ¹⁸ atoms / cm ³ (20 mΩ · cm or more and 100 mΩ · cm or less).

  FIG. 3 is a schematic cross-sectional view showing the structure of the MCP 20 using the thinned semiconductor device 10. The MCP 20 shown in FIG. 3 has a configuration in which four semiconductor devices 10 are stacked on a package substrate 21. The semiconductor device 10 and the package substrate 21 that are vertically adjacent to each other are fixed by an adhesive 22. Further, the semiconductor device 10 and the package substrate 21 are connected by the bonding wire 23, whereby each semiconductor device 10 is electrically connected to the external electrode 24 via an internal wiring (not shown) provided on the package substrate 21. Connected. A sealing resin 25 for protecting the semiconductor device 10 and the bonding wire 23 is provided on the package substrate 21.

  In the MCP 20 having such a configuration, since the thickness of one semiconductor device 10 is reduced to, for example, about 100 μm, the entire thickness of the MCP can be reduced to, for example, about 1 mm. For this reason, the application to the use as which a low profile is requested | required, such as a mobile apparatus, is suitable.

  Next, a method for manufacturing the semiconductor device 10 will be described with reference to a flowchart.

  FIG. 4 is a flowchart for roughly explaining a method for manufacturing the semiconductor device 10. As shown in FIG. 4, the manufacturing process of the semiconductor device 10 is roughly classified into three processes: a silicon wafer manufacturing process (step S10), a device pre-process (step S20), and a device post-process (step S30). . Hereinafter, each process will be described in detail.

  The silicon wafer manufacturing process (step S10) is performed by cutting a silicon wafer from a silicon ingot pulled up by the Czochralski (CZ) method. The specific resistance of the silicon wafer can be adjusted by the amount of boron added to the silicon melt, and the initial oxygen concentration can be adjusted by convection control of the silicon melt. Moreover, an oxygen precipitate is formed by performing heat treatment as necessary. Further, an epitaxial film is formed as necessary.

  The device pre-process (step S20) is a process of forming a semiconductor element or the like on the silicon substrate 11 (or the epitaxial film 14), but since it differs depending on the type of semiconductor device to be manufactured, its details are omitted. Examples of the semiconductor device include logic semiconductor devices such as MPU and DSP, and memory semiconductor devices such as DRAM and flash memory.

  FIG. 5 is a flowchart for explaining the device post-process (step S30).

  As shown in FIG. 5, in the device post-process, first, the back grinding of the silicon wafer is performed (step S31). The back surface grinding is performed by roughly grinding a part of the silicon substrate 11 from the back surface side, thereby reducing the thickness of the silicon substrate 11 to 100 μm or less. Note that this step (thinning step) is not limited to grinding but can be performed by etching or the like.

  Next, the polished back surface of the silicon substrate 11 is mirror-polished (step S32), whereby the damage introduced by the back surface grinding (step S31) is removed and the mechanical strength is increased. The back grinding (step S31) and back grinding (step S32) described above are performed in a state where a back grind protective tape is attached to the front side of the silicon wafer (silicon substrate 11) in order to protect the device region 12. Is preferred. As a material of the back grind protective tape, a commercially available tape generally used in a device post-process can be mentioned. In this case, the heat resistant temperature is about 200 ° C.

Next, boron or an n-type dopant is ion-implanted from the back side of the polished silicon wafer (silicon substrate 11) (step S33). Since the thinned silicon wafer is difficult to handle, this step is preferably performed in a state where a back grind protective tape is attached to the surface side of the silicon wafer. As an apparatus for performing ion implantation, an ion implantation apparatus or an ion doping apparatus may be used. The implantation energy is not particularly limited, but is preferably set to 10 KeV to 200 KeV. Dose, as already ^{described, 1 × 10 13 atoms / cm} 2 or more 5 × ¹⁰ 15 atoms / cm ² is preferably set ^{below, 1 × 10 13 atoms / cm} 2 or more 1 × ¹⁰ 15 atoms / cm It is more preferable to set it to ² or less.

  Next, the implanted boron or n-type dopant is activated by heating the back surface of the silicon wafer (silicon substrate 11) (step S34). The activation treatment is also preferably performed in a state where a back grind protective tape is attached to the surface side of the silicon wafer. By performing the activation treatment, the implanted boron or n-type dopant is activated and functions as a powerful gettering source. Further, damage remaining on the back surface of the silicon wafer also exhibits a gettering effect.

  In order to suppress the temperature rise of the surface of the silicon wafer formed with the device as much as possible, it is preferable to use an apparatus capable of single-sided heating instead of an apparatus that heats the entire surface such as a batch heat treatment furnace. Examples of the apparatus that can perform single-side heating include a laser heating apparatus and a flash lamp apparatus. That is, if the back surface of the silicon wafer is heated using a laser heating device or a flash lamp device, the temperature of the back surface of the silicon wafer is controlled while suppressing the temperature rise of the device region 12 on the silicon wafer surface and the back grind protective tape. It can be raised.

  Specifically, using a device that performs single-sided heating, it is preferably performed under the condition that the temperature of the silicon wafer surface is equal to or lower than the device heat resistance temperature, and is performed under the condition that the temperature of the back grind protective tape is equal to or lower than the heat resistance temperature. More preferable. Although the device heat-resistant temperature varies depending on the type of the semiconductor device 10, it is generally about 400 ° C. The heat resistant temperature of the back grind protective tape is generally about 200 ° C., although it varies depending on the type of material of the back grind protective tape. On the other hand, since the temperature necessary for activating the implanted ion species is 1000 ° C. or higher, the back surface of the silicon wafer is heated to 1000 ° C. or higher, while the surface of the silicon wafer is 400 ° C. or lower, particularly 200 ° C. It is preferable to keep the temperature below ℃.

  Next, the silicon wafer is diced into individual chips (step S35). Thereby, the chip | tip (semiconductor device 10) separated into pieces is completed.

  After that, when the separated semiconductor device 10 is mounted on a package substrate or the like and wire bonding or resin sealing is performed, the MCP is completed (step S36).

  In such a device post-process (step S30), heavy metals such as Cu and Ni may adhere to the back surface of the silicon substrate 11 in the back surface grinding process (step S31), the back surface polishing process (step S32), and the like. However, in the present embodiment, after the back surface grinding and the back surface polishing are performed, ions are implanted into the back surface of the silicon substrate 11 (step S33) and further activated (step S34), so that the silicon substrate 11 Heavy metal adhering to the back surface of the metal stays on the back surface, and diffusion to the device region 12 is prevented.

  As described above, according to the present embodiment, since a predetermined ion species is ion-implanted and then activated, the gettering ability and mechanical strength of the semiconductor device 10 whose mirror-polished back surface is obtained. Can be secured.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

[Example 1]
^Three boron-doped CZ wafers having a diameter of 150 mm, a thickness of 525 μm, an initial oxygen concentration of 12 × 10 ¹⁷ atoms / cm ³ and a specific resistance of 20 Ω · cm were prepared. With the back grind protective tape attached to the front surface of these wafers, the back surface of the wafer was ground to reduce the thickness to 300 μm. Next, the back surface of the wafer was polished by 3 μm with a CMP apparatus.
Then, boron is applied to each of the three wafers at a dose of 1 × 10 ¹³ atoms / cm ² , 5 × 10 ¹³ atoms / cm ² , and 1 × 10 ¹⁵ atoms / cm ² at an acceleration energy of 30 KeV from the back surface. ion implantation, further Cu surface concentration performs a spin coating contamination in the polishing surface so as to be ^{5 × 10 11 atoms / cm 2} , 200 ℃ on a hot plate and subjected to heat treatment for 1 hour. Finally, the back grind protective tape was removed, and the sample was washed with pure water.
A sample with a dose amount of 1 × 10 ¹³ atoms / cm ² is Example 1A, a sample with a dose amount of 5 × 10 ¹³ atoms / cm ² is Example 1B, and a dose amount is 1 × 10 ¹⁵ atoms / cm ² . One sample was designated Example 1C.

[Example 2]
A sample of Example 2 was produced in the same manner as Example 1 except that laser irradiation was performed on the back surface of the wafer in order to activate boron after the boron implantation.
A sample with a dose amount of 1 × 10 ¹³ atoms / cm ² is Example 2A, a sample with a dose amount of 5 × 10 ¹³ atoms / cm ² is Example 2B, and a dose amount is 1 × 10 ¹⁵ atoms / cm ² . One sample was designated Example 2C.

[Example 3]
A sample of Example 3 was produced in the same manner as Example 2 except that phosphorus was ion-implanted instead of boron. The dose of phosphorus was 1 × 10 ¹⁴ atoms / cm ² .

[Comparative Example 1]
A sample of Comparative Example 1 was produced in the same manner as Example 1 except that ion implantation was omitted.

[Evaluation]
After all samples were allowed to stand at room temperature for 7 days, the Cu concentration diffused on the wafer surface was measured by total reflection fluorescent X-ray.
As a result, a Cu concentration of 1 to 3 × 10 ⁹ / cm ^{2 was} detected in the sample of Example 1, and in all the samples of Example 2 and Example 3, the Cu concentration was a detection limit value (1 × 10 ⁹ / Cm ² or less). On the other hand, in the sample of Comparative Example 1, 4 × 10 ¹⁰ / cm ² of Cu was detected. Thereby, the effect of the ion implantation to the back surface and the activation treatment was confirmed.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Silicon substrate 11a Front surface 11b of silicon substrate Back surface 12 of silicon substrate Device region 13 Gettering layer 14 Epitaxial film 20 MCP
21 Package Substrate 22 Adhesive 23 Bonding Wire 24 External Electrode 25 Sealing Resin

Claims (6)

Removing a part of the silicon substrate on which the semiconductor element is formed on the front surface from the back side, thereby reducing the thickness of the silicon substrate to 100 μm or less;
A back surface polishing step for polishing the back surface of the thinned silicon substrate;
And an ion implantation step of ion-implanting boron or an n-type dopant into the polished back surface of the silicon substrate. ^2. The semiconductor device according to claim 1, wherein, in the ion implantation step, a dose amount of the boron or the n-type dopant is 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less. Manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, further comprising an activation step of activating the implanted boron or n-type dopant by heating the back surface of the silicon substrate.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the activation step is performed using an apparatus that heats the back surface of the silicon substrate on one side.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the activation step is performed under a condition that a surface temperature of the silicon substrate is equal to or lower than a device heat-resistant temperature.   The ion implantation step and the activation step are performed in a state where a back grind protective tape is attached to the surface of the silicon substrate, and in the activation step, the temperature of the back grind protective tape is a heat resistant temperature or less. The method for manufacturing a semiconductor device according to claim 3, wherein heating is performed.

Images