JP2010283296A - Silicon wafer, manufacturing method thereof, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon wafer suitable for a semiconductor device which is to be thinned in a device post-step and has a rear surface to be polished. <P>SOLUTION: A manufacturing method includes: a step S11 for preparing a silicon substrate 11 having ≥2m Ω cm and ≤200m Ω cm of specific resistance based on boron concentration; an ion implantation step S12 for implanting ions at a dose of ≥1×10<SP>13</SP>and ≤5×10<SP>15</SP>atoms/cm<SP>2</SP>in the silicon substrate 11; and a step S13 for forming an epitaxial film 12 having a film thickness of ≤10 μm on the surface of a side subjected to ion implantation of the silicon substrate 11. With this configuration, chips are thinned by grinding the rear surface of the silicon substrate 11 in the device post-step, and thus, even if the rear surface is further polished, sufficient gettering performance can be exhibited for contamination due to heavy metal to be introduced in the device post-step. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a silicon wafer and a manufacturing method thereof, and more particularly to a silicon wafer suitable for a semiconductor device mounted on a multichip package (MCP) and a manufacturing method thereof. The present invention also relates to a method for manufacturing a semiconductor device suitable for mounting on an MCP.

  One of the problems in the semiconductor process is that heavy metals as impurities are mixed in the silicon wafer. When heavy metals diffuse into a device region formed on the surface side of a silicon wafer, device characteristics such as pause time failure, retention failure, junction leak failure, and dielectric breakdown of the oxide film are significantly adversely affected. For this reason, in order to suppress the heavy metal mixed in the silicon wafer from diffusing into the device region, the gettering method is generally adopted. Gettering is aimed at preventing heavy metal contamination in a device pre-process for forming a device on the surface of a silicon substrate.

  On the other hand, heavy metal contamination in post-device processes such as thinning of the silicon substrate, wire bonding, or resin encapsulation performed after the pre-device process has not been particularly emphasized. This is a process of grinding and removing the back surface of the silicon wafer in the early stage of the device post-process. Scratches and damage introduced during the back surface grinding act as a gettering source by strong extrinsic gettering (EG). Because.

  However, the final chip thickness is becoming thinner year by year, and in particular, the chip mounted on the MCP is often made thinner to 100 μm or less, and depending on the product, it is currently made thinner to 25 μm or less, and in the future it will be 10 μm or less. Both are predicted. When the thickness of the chip is reduced to 100 μm or less, there arises a problem that the silicon wafer is easily broken due to damage during back grinding. In order to solve such a problem, it is necessary to newly add a process of removing damage after the back surface grinding, that is, a back surface polishing process by the CMP method.

  However, if the damage on the back surface of the silicon wafer is removed by back surface polishing, the back surface gettering source also disappears, and the EG effect is lost. Moreover, since a thin silicon wafer has a thin intrinsic gettering (IG) layer, a sufficient IG effect cannot be expected with a normal IG layer formed of oxygen precipitates. More specifically, even in the case of an epitaxial wafer or silicon wafer using the IG method, a DZ layer having no oxygen precipitation nuclei including the thickness of the epitaxial film is formed by heat treatment to have a thickness of 10 μm or more from the wafer surface. When the final film thickness of the chip becomes thinner, the IG layer hardly exists and the impurity metal generated in the device post-process cannot be gettered at all.

  As described above, in the thin semiconductor device in which the back surface of the silicon wafer is polished, the problem of heavy metal contamination in the device post-process is beginning to become apparent.

  In this regard, Patent Document 1 discloses that a silicon epitaxial film (first layer) containing high-concentration boron is grown on a silicon substrate by about 100 μm, and further a high-resistance silicon epitaxial film (second layer) serving as a device region. ) Is grown about several tens of μm. And after performing a device pre-process using such a silicon wafer, the total thickness is reduced to about 100 μm by grinding the silicon substrate from the back surface, and the back surface is further mirror-polished.

  According to the method described in Patent Document 1, since the first silicon epitaxial film containing high-concentration boron exists below the second silicon epitaxial film serving as the device region, mirror polishing is used. Even if the EG layer disappears, heavy metal, particularly Cu or Fe, can be efficiently gettered by the effect of high-concentration boron. However, the inventors have confirmed through experiments that boron has no effect on Ni contamination.

  Patent Document 1 discloses a method for forming a damaged layer by ion implantation of oxygen, nitrogen, or the like in an epitaxial film containing high-concentration boron, or a method in which a silicon substrate is previously formed at a temperature of 1000 ° C. or higher, for example, 1200 ° C. or lower. A method is also described in which the first heat treatment is performed and the second heat treatment is further performed at 1000 ° C. or lower, for example, 800 ° C. According to these methods, it is considered that a certain effect can be obtained against Ni contamination. However, growing an epitaxial film as much as several tens of μm can not withstand the miniaturized structure used in the most advanced devices because it causes a significant decrease in productivity and a deterioration in film accuracy itself.

  Moreover, since the first heat treatment is an oxygen outward diffusion treatment for forming the DZ layer, heat treatment at 1200 ° C. for about 1 hour is required. In this case, in order to prevent the occurrence of slip dislocation, it is necessary to sufficiently slow the temperature raising / lowering speed, and about 10 hours are required for one process, resulting in an increase in cost. In particular, as the diameter of the silicon wafer is increased, the processing time is increased, so that mass production becomes increasingly difficult.

  On the other hand, Patent Document 2 discloses a technique for imparting gettering capability to a thinned wafer back surface by various methods. For example, a method of depositing a polycrystalline silicon film or a nitride film on the back surface of a thinned silicon wafer, a method of damaging the back surface using silica particles, a method of giving a damaged layer on the back surface by ion implantation, etc. Yes. Certainly, these methods are considered to be effective if the chip thickness is thick to some extent, but as already explained, if the final chip thickness is reduced to 100 μm or less, and in the future to about 10 μm, The yield strength is expected to be significantly reduced because the bending strength is reduced due to the introduction of physical damage due to silica particles and the like, resulting in a problem of chip cracking. In addition, it is not practical for a mass-produced product to deposit a polycrystalline silicon film or a nitride film or perform ion implantation in a device post-process.

JP 2005-317735 A JP 2006-41258 A

  As a result of intensive research conducted by the present inventors to solve such problems, if the silicon substrate itself contains a high concentration of boron and ion implantation is performed on the silicon substrate before the formation of the epitaxial film, After that, it was found that it can be mass-produced as a silicon wafer for a semiconductor device to be thinned only by forming a very thin epitaxial film on the surface of the silicon substrate. The present invention has been made based on such technical knowledge.

The silicon wafer according to the present invention has a specific resistance based on boron concentration of 2 mΩ · cm to 200 mΩ · cm, and is formed on the surface of the silicon substrate, and has a film thickness of 10 μm or less. An epitaxial film having a high specific resistance, and a dose amount of 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less on the surface of the silicon substrate on the epitaxial film side. The ions are implanted.

The silicon wafer manufacturing method according to the present invention is 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less for a silicon substrate having a specific resistance based on boron concentration of 2 mΩ · cm to 200 mΩ · cm. An ion implantation step of implanting ions at a dose of 1 nm and an epitaxial film having a film thickness of 10 μm or less and a higher specific resistance than the silicon substrate on the surface of the silicon substrate on which the ion implantation has been performed. And an epitaxial process.

The method of manufacturing a semiconductor device according to the present invention is 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less for a silicon substrate having a specific resistance based on boron concentration of 2 mΩ · cm to 200 mΩ · cm. An ion implantation step of implanting ions at a dose of 1 nm and an epitaxial film having a film thickness of 10 μm or less and a higher specific resistance than the silicon substrate on the surface of the silicon substrate on which the ion implantation has been performed. After performing the epitaxial process, the device pre-process for forming a semiconductor element on the epitaxial film, and the device pre-process, a part of the silicon substrate is removed from the back surface side, thereby forming the silicon substrate and the epitaxial film. A thinning step for reducing the total thickness to 100 μm or less, and the back surface of the thinned silicon substrate And back grinding step for grinding, characterized in that it comprises a.

  According to the present invention, since an epitaxial film of 10 μm or less is formed on a silicon substrate and used as a device region, the epitaxial film can be formed in a short time and can be applied to mass-produced products. It becomes. Moreover, since the silicon substrate contains high-concentration boron, even if the final chip thickness is reduced to about 100 μm, heavy metals such as Cu and Fe can be effectively gettered by boron. It becomes. In addition, since high-concentration ion implantation is performed on the silicon substrate immediately below the epitaxial film, heavy metal such as Ni can be effectively gettered from the initial device process due to damage caused by this.

  In the present invention, the ion species implanted into the silicon substrate is one or more ions selected from the group consisting of boron, phosphorus, antimony, arsenic, helium, argon, fluorine, oxygen, nitrogen, carbon, silicon, and germanium. Preferably it is a seed. By selecting these ion species, it is possible to effectively getter heavy metals such as Ni without adversely affecting the device.

In the present invention, the initial oxygen concentration of the silicon substrate is preferably 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. According to this, oxygen precipitates are formed on the silicon substrate by heat treatment before or during the device pre-process, and this becomes a gettering source for heavy metals such as Ni.

  Further, in the method of manufacturing a semiconductor device according to the present invention, the damage recovery at the time of ion implantation is performed by a heat treatment in the pre-device process, for example, in a heat treatment process in which a heat treatment at 1100 ° C. or higher is performed for 30 minutes or more for well diffusion. For example, the heat treatment time in a batch furnace is 1050 ° C. or less and the heat treatment time is several tens of minutes or less, or the heat treatment in a short time of several seconds to 1 minute in a single-wafer lamp furnace. In this case, since the damage is not completely recovered, a sufficient gettering effect can be exhibited even in the post-device process, and the implanted ions do not diffuse to the device region.

  Thus, according to the silicon wafer and the manufacturing method thereof according to the present invention, it is possible to inexpensively mass-produce semiconductor devices whose final chip thickness is reduced to about 100 μm.

  In addition, according to the semiconductor device manufacturing method of the present invention, it is possible to mass-produce thinned semiconductor devices at low cost.

1 is a schematic cross-sectional view showing the structure of a silicon wafer 10 according to a preferred embodiment of the present invention. 1 is a schematic cross-sectional view showing a structure of a thinned semiconductor device 20. It is a schematic sectional drawing which shows the structure of MCP30 using the semiconductor device 20 reduced in thickness. 4 is a flowchart for roughly explaining a method for manufacturing the semiconductor device 20. It is a flowchart for demonstrating the manufacturing process (step S10) of a silicon wafer. It is a flowchart for demonstrating a device back process. It is a table | surface which shows the evaluation result of an Example.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view showing the structure of a silicon wafer 10 according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the silicon wafer 10 according to the present embodiment includes a silicon substrate 11 and an epitaxial film 12 formed on the surface thereof. The silicon substrate 11 secures the mechanical strength of the silicon wafer 10 and serves as a heavy metal gettering source. Among heavy metals, those that diffuse in silicon in a cation state, such as Cu and Fe, are mainly captured by the anions of boron contained in the silicon substrate 11. Further, among heavy metals, those that diffuse in silicon in an electrically neutral state, such as Ni, are captured by crystal damage caused by ions implanted into the silicon substrate 11. Crystal damage also contributes to trapping Cu and Fe. Furthermore, oxygen precipitates formed by heat treatment also serve as gettering sources. The thickness of the silicon substrate 11 is not particularly limited as long as the mechanical strength is ensured, but is about 725 μm, for example.

The silicon substrate 11 is a so-called P + substrate doped with high-concentration boron. The dose amount of boron is 1 × 10 ¹⁷ atoms / cm ³ or more and 5.5 × 10 ¹⁹ atoms / cm ³ or less, whereby the specific resistance of the silicon substrate 11 based on the boron concentration is 2 mΩ · cm or more and 200 mΩ · cm. It becomes as follows. The specific resistance of the silicon substrate 11 needs to be 2 mΩ · cm or more because if the boron concentration is too high, the device region may be affected by boron diffusion into the epitaxial film 12, and the lattice This is because it becomes difficult to form the epitaxial film 12 free from defects due to mismatch. On the other hand, the specific resistance of the silicon substrate 11 needs to be 200 mΩ · cm or less because heavy metals such as Cu and Fe cannot be sufficiently gettered if the boron concentration is too low.

In particular, the specific resistance of the silicon substrate 11 based on the boron concentration is preferably 40 mΩ · cm or more and 100 mΩ · cm or less. This is equivalent to 2 × 10 ¹⁷ atoms / cm ³ or more and less than 1 × 10 ¹⁸ atoms / cm ³ in terms of boron dose. If the specific resistance of the silicon substrate 11 is set within this range, the above-described problems due to high-concentration boron are hardly caused while securing gettering ability such as Cu and Fe. In Patent Document 1, there is no change in the diffusion rate of heavy metal unless the impurity concentration is 1 × 10 ¹⁸ atoms / cm ³ or higher, and the diffusion rate of heavy metal is not higher than 1 × 10 ²⁰ atoms / cm ^3. Although it has been reported that it does not change significantly, according to a more detailed study by the present inventors, even if the boron concentration is less than 1 × 10 ¹⁸ atoms / cm ³ , an obvious gettering effect has been confirmed. Yes. Specific experimental results are described in the examples described later.

The fact that the silicon substrate 11 does not need to contain excessive boron has the following significance. That is, if the silicon substrate 11 contains excessive boron, the resistivity of the epitaxial film cannot be controlled because the boron of the substrate diffuses in the vapor phase during the growth of the epitaxial film. Also, boron solid layer diffusion from the silicon substrate 11 to the device region during the device process cannot be ignored. For this reason, when the thickness of the epitaxial film 12 is thin (10 μm or less) as in the present invention, excessive boron may reduce the yield. Considering this point, the dose of boron is 1 × 10 ¹⁷ atoms / cm ³ or more and 5.5 × 10 ¹⁹ atoms / cm ³ or less (2 mΩ · cm or more and 200 mΩ · cm or less in terms of specific resistance). It is preferable to set it to 2 × 10 ¹⁷ atoms / cm ³ or more and less than 1 × 10 ¹⁸ atoms / cm ³ (40 mΩ · cm or more and 100 mΩ · cm or less in terms of specific resistance).

The silicon substrate 11 preferably has an initial oxygen concentration of 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. This is because oxygen precipitates necessary for gettering heavy metals such as Ni are not sufficiently formed when the oxygen concentration is less than 7 × 10 ¹⁷ atoms / cm ³ , and the oxygen concentration is 2.4 × 10 ¹⁸ atoms. This is because if it exceeds / cm ³ , it becomes difficult to form the epitaxial film 12 having no defect. However, in the present invention, since the crystal damage due to ion implantation functions as a gettering source, the initial oxygen concentration of the silicon substrate 11 may be less than 7 × 10 ¹⁷ atoms / cm ³ . In addition, all the oxygen concentrations described in this specification are measured values by Fourier transform infrared spectrophotometry standardized by ASTM F-121 (1979).

The initial oxygen concentration of the silicon substrate 11 is preferably higher in a range not exceeding 2.4 × 10 ¹⁸ atoms / cm ³ , and carbon or nitrogen is included in the silicon substrate 11 to promote oxygen precipitation. Is more preferable. The carbon content is preferably 1 × 10 ¹⁶ atoms / cm ³ or more and 1.2 × 10 ¹⁷ atoms / cm ³ or less, and the nitrogen content is 1 × 10 ¹³ atoms / cm ³ or more and 1 It is preferable that it is x10 ¹⁴ atoms / cm ³ or less.

  The oxygen precipitation heat treatment for forming oxygen precipitates on the silicon substrate 11 may be performed before the device pre-process, or may be substituted by a thermal process in the device pre-process. In addition, when performing oxygen precipitation heat processing before a device pre-process, it is preferable to carry out before the ion implantation mentioned later. This is because if the oxygen precipitation heat treatment is performed after forming the damaged layer 11x by ion implantation, the damage is recovered and the gettering effect by the damaged layer 11x may be lost.

As shown in FIG. 1, the damage layer 11 x is formed on the surface layer of the silicon substrate 11 on the epitaxial film 12 side. The damage layer 11x is formed by ion implantation of an ion species that does not contaminate the device layer, and the dose amount is set to 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less. This is because if the dose amount is less than 1 × 10 ¹³ atoms / cm ² , the silicon substrate 11 is not damaged so much that heavy metals such as Ni cannot be captured sufficiently, and the dose amount is 5 × 10 6. ^This is because if it exceeds ¹⁵ atoms / cm ² , the silicon substrate 11 is damaged so much that it is difficult to form the defect-free epitaxial film 12.

  The ion species used for forming the damaged layer 11x can be selected from ion species used as a P-type dopant, ion species used as an N-type dopant, and non-dopant ions. As the ion species used as the P-type dopant, it is preferable to select boron. Furthermore, it is preferable to select helium, argon, fluorine, oxygen, nitrogen, carbon, silicon, or germanium as the non-dopant.

  If boron is selected as the ion species, not only the implantation damage but also the boron concentration of the silicon substrate 11 is further increased, so that the gettering effect by boron ions can be enhanced. Moreover, it is preferable to select phosphorus, antimony, or arsenic as the ion species used as the N-type dopant. If an N-type dopant is selected as the ion species, not only implantation damage but also the conductivity of the damaged layer 11x becomes N-type, and the solid solubility of Cu ions is lower than that of the boron substrate. It is effective as a barrier against Cu ion contamination during backside polishing. Further, when a non-dopant ion is selected as the ion species, the gettering effect is only implantation damage, but there is no risk of fluctuation in the threshold value of the transistor.

  Considering the above points and the ease of ion implantation, it is particularly preferable to select boron, phosphorus, antimony, silicon, or argon as the ion species.

  The epitaxial film 12 is formed on the surface of the silicon substrate 11 as shown in FIG. The epitaxial film 12 is a part that becomes a device region. For this reason, the specific resistance of the epitaxial film 12 is set higher than the specific resistance of the silicon substrate 11. The film thickness of the epitaxial film 12 is 10 μm or less. This is because when the thickness of the epitaxial film 12 is increased to more than 10 μm, the thickness of the silicon substrate 11 is reduced correspondingly, so that the remaining thickness of the oxygen precipitation layer is reduced, so that the gettering ability is reduced and the epitaxial growth is performed. This is because it takes time, and an increase in film thickness leads to deterioration in flatness, which cannot be handled by a state-of-the-art device.

  The above is the configuration of the silicon wafer 10 according to the present embodiment. In such a silicon wafer 10, after device formation is performed on the epitaxial film 12 by a device pre-process, a part of the silicon substrate 11 is removed from the back surface side, so that the total thickness of the silicon substrate 11 and the epitaxial film 12 is 100 μm. It can be as follows.

  FIG. 2 is a schematic cross-sectional view showing the structure of a thinned semiconductor device (silicon chip) 20. In the semiconductor device 20 shown in FIG. 2, a part of the silicon substrate 11 is removed from the back surface side by grinding or etching, and the newly exposed back surface 11a is mirror-polished. Thereby, even if it is a case where total thickness is thinned to about 100 micrometers, since bending strength is ensured, it becomes possible to prevent a crack of a chip | tip.

  FIG. 3 is a schematic cross-sectional view showing the structure of the MCP 30 using the thinned semiconductor device 20. The MCP 30 shown in FIG. 3 has a configuration in which four semiconductor devices 20 are stacked on a package substrate 31. The semiconductor device 20 and the package substrate 31 that are vertically adjacent to each other are fixed by an adhesive 32. Further, the semiconductor device 20 and the package substrate 31 are connected to each other by bonding wires 33, whereby each semiconductor device 20 is electrically connected to the external electrode 34 via an internal wiring (not shown) provided on the package substrate 31. Connected. Further, a sealing resin 35 for protecting the semiconductor device 20 and the bonding wire 33 is provided on the package substrate 31.

  In the MCP 30 having such a configuration, since the thickness of one semiconductor device 20 is reduced to, for example, about 100 μm, the thickness of the entire MCP can be reduced to, for example, about 1 mm. For this reason, the application to the use as which a low profile is requested | required, such as a mobile apparatus, is suitable.

  Next, a method for manufacturing the semiconductor device 20 will be described with reference to a flowchart.

  FIG. 4 is a flowchart for roughly explaining a method for manufacturing the semiconductor device 20. As shown in FIG. 4, the manufacturing process of the semiconductor device 20 is roughly classified into three processes: a silicon wafer manufacturing process (step S10), a device pre-process (step S20), and a device post-process (step S30). . Hereinafter, each process will be described in detail.

  FIG. 5 is a flowchart for explaining the silicon wafer manufacturing process (step S10).

In the present embodiment, first, a silicon substrate 11 is prepared (step S11). The silicon substrate 11 is a CZ wafer cut out from a silicon ingot pulled up by the Czochralski (CZ) method. As described above, the resistivity based on the boron concentration is 2 mΩ · cm to 200 mΩ · cm, preferably initial The oxygen concentration is set to 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. The specific resistance can be adjusted by the amount of boron added to the silicon melt, and the initial oxygen concentration can be adjusted by convection control of the silicon melt.

Next, ion implantation is performed on the silicon substrate 11 at a dose of 1 × 10 ¹³ atoms / cm ^{2 to} 5 × 10 ¹⁵ atoms / cm ² (step S12). Thereby, a damage layer 11x is formed in the vicinity of the surface of the silicon substrate 11 on which the epitaxial film 12 is to be formed. Preferred ionic species are as described above.

  Next, crystal recovery heat treatment is performed on the silicon substrate 11 in a temperature range of 500 ° C. or higher and 1100 ° C. or lower (step S13). Thereby, excessive crystal damage generated in the silicon substrate 11 due to ion implantation is repaired, and the defect-free epitaxial film 12 can be formed in the next step. However, it is not essential to perform crystal recovery heat treatment in the present invention.

  Then, the epitaxial film 12 is formed on the surface of the silicon substrate 11 (step S14). The film thickness of the epitaxial film 12 is set to 10 μm or less, and the specific resistance is set to be higher than that of the silicon substrate 11. When the crystal recovery heat treatment is not performed before the formation of the epitaxial film 12, excessive crystal damage generated in the silicon substrate 11 is repaired by heat at the time of forming the epitaxial film 12. Thus, the silicon wafer 10 is completed. Thus, since the ion implantation for forming the damaged layer 11x is performed before the formation of the epitaxial film 12, the epitaxial film 12 is not damaged by the ion implantation.

  The above is the silicon wafer manufacturing process (step S10). As shown in FIG. 4, when the silicon wafer manufacturing process (step S10) is completed, a device pre-process (step S20) is performed next. The device pre-process (step S20) is a process of forming a semiconductor element or the like on the epitaxial film 12, but the details thereof are omitted because it differs depending on the type of semiconductor device to be manufactured. Examples of the semiconductor device include logic semiconductor devices such as MPU and DSP, and memory semiconductor devices such as DRAM and flash memory. However, in the device pre-process (step S20), when performing heat treatment using a batch heat treatment furnace, heat treatment is preferably performed in a temperature range not exceeding 1100 ° C., and heat treatment is performed using a single wafer lamp furnace or a laser annealer. In some cases, the temperature exceeds 1100 ° C., but it is an ultra-short time heat treatment in milliseconds, and even when a normal RTP process is constituted by a short time heat treatment for several seconds to several minutes, damage during ion implantation may disappear. Absent.

  FIG. 6 is a flowchart for explaining the device post-process (step S30).

  As shown in FIG. 6, in the device post-process, first, the back surface of the silicon wafer 10 is ground (step S31). The back surface grinding is performed by roughly grinding a part of the silicon substrate 11 from the back surface side, thereby reducing the total thickness of the silicon substrate 11 and the epitaxial film 12 to 100 μm or less. Note that this step is not limited to grinding but can be performed by etching or the like.

  Next, the polished back surface of the silicon substrate 11 is mirror-polished (step S32), whereby the damage introduced by the back surface grinding (step S31) is removed and the mechanical strength is increased.

  Next, the silicon wafer 10 is diced into individual chips (step S33). Thereby, the chip | tip (semiconductor device 20) separated into pieces is completed.

  After that, when the separated semiconductor device 20 is mounted on a package substrate or the like and wire bonding or resin sealing is performed, the MCP is completed (step S34).

  In such a device post-process (step S30), heavy metals such as Cu and Ni may be mixed into the silicon substrate 11 particularly in the back grinding process (step S31) and the back polishing process (step S32). In the silicon wafer 10 according to the embodiment, since the silicon substrate 11 contains high-concentration boron and the damaged layer 11x is formed in the vicinity of the epitaxial film 12, heavy metals such as Cu and Ni are present in the device region. It will never reach.

  As described above, according to the present embodiment, since the thin epitaxial film 12 is formed on the silicon substrate 11 containing high concentrations of boron and oxygen, the final chip thickness is as thin as 100 μm or less. Even when the back surface is mirror-polished, gettering ability and mechanical strength can be ensured.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

[Example 1]
^Three boron-doped CZ wafers having a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 7 × 10 ¹⁷ atoms / cm ³ , and a specific resistance of 10 to ²⁰ mΩ · cm were prepared, and each 1 × 10 ¹³ atoms / cm ^2. After implanting boron with a dose of 1 × 10 ¹⁴ atoms / cm ² and 1 × 10 ¹⁵ atoms / cm ² , an epitaxial film having a specific resistance of 10 Ω · cm and a film thickness of 3.5 μm is formed on the surface of the ion-implanted side. Grew. A sample with a dose amount of 1 × 10 ¹³ atoms / cm ² is Example 1A, a sample with a dose amount of 1 × 10 ¹⁴ atoms / cm ² is Example 1B, and a dose amount is 1 × 10 ¹⁵ atoms / cm ² . One sample was designated Example 1C.

[Example 2]
Two boron-doped CZ wafers having a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 1.2 × 10 ¹⁷ atoms / cm ³ , and a specific resistance adjusted to 50 to 100 mΩ · cm are prepared, and 1 × 10 ¹⁴ atoms / cm. ^After argon and phosphorus were ion-implanted at a dose of ² , respectively, an epitaxial film having a specific resistance of 10 Ω · cm and a film thickness of 3.5 μm was grown on the ion-implanted surface. Samples into which argon was ion-implanted were Example 2A and phosphorus was ion-implanted in Example 2B.

[Example 3]
Two boron-doped CZ wafers having a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 1.2 × 10 ¹⁷ atoms / cm ³ and a specific resistance adjusted to 10 to ²⁰ mΩ · cm are prepared, and 1 × 10 ¹⁴ atoms / cm. ^After argon and antimony were ion-implanted at a dose of ² , respectively, an epitaxial film having a specific resistance of 10 Ω · cm and a film thickness of 3.5 μm was grown on the ion-implanted surface. The sample into which argon was ion-implanted was Example 3A and Example 3B into which antimony was ion-implanted.

[Comparative Example 1]
A boron-doped CZ wafer having a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ , and a specific resistance adjusted to 15 to 20 Ω · cm is prepared, and a specific resistance of 12 Ω · cm is provided on the surface. An epitaxial film having a thickness of 3.5 μm was grown. The sample thus obtained was designated as Comparative Example 1.

[Comparative Example 2]
One phosphorus-doped CZ wafer with a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 1.2 × 10 ¹⁸ atoms / cm ³ , and a specific resistance adjusted to about 20 Ω · cm is prepared. An epitaxial film having a thickness of cm and a thickness of 3.5 μm was grown. The sample thus obtained was referred to as Comparative Example 2.

[Comparative Example 3]
One boron-doped CZ wafer having a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ and a specific resistance adjusted to 5 to 10 mΩ · cm is prepared, and a specific resistance of 12 Ω · cm is provided on the surface. An epitaxial film having a thickness of 3.5 μm was grown. The sample thus obtained was referred to as Comparative Example 3.

[Comparative Example 4]
One boron-doped CZ wafer having a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ and a specific resistance adjusted to 15 to 20 Ω · cm is prepared, and a specific resistance of 50 to 100 mΩ is provided on the surface. A first epitaxial film with a thickness of 50 μm is grown, and a second epitaxial film with a specific resistance of 10 Ω · cm and a thickness of 3.5 μm is grown on the surface of the first epitaxial film. It was. The sample thus obtained was designated as Comparative Example 4.

[Comparative Example 5]
One boron-doped CZ wafer having a diameter of 200 mm, a thickness of 725 μm, an initial oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ , and a specific resistance adjusted to 15 to 20 Ω · cm is prepared at 1200 ° C. under an argon gas atmosphere. After the heat treatment for an hour, the heat treatment was further performed at 800 ° C. for 2 hours. Next, a first epitaxial film having a specific resistance of 50 to 100 mΩ · cm and a film thickness of 50 μm is grown on the surface of the wafer, and a specific resistance of 10 Ω · cm and a film thickness is formed on the surface of the first epitaxial film. A second epitaxial film of 3.5 μm was grown. The sample thus obtained was designated as Comparative Example 5.

[Evaluation 1]
All samples were subjected to spin coating contamination of 1 × 10 ¹² / cm ^{2 in} terms of Ni surface concentration, followed by heat treatment at 1000 ° C. for 1 hour, and the surface oxide film was removed with a hydrofluoric acid aqueous solution. . Then, after performing selective etching (Wright Etching), defects on the epitaxial surface were observed with an optical microscope.
The results are shown in FIG. As shown in FIG. 7, in the samples of Comparative Examples 1 to 4, many defects were observed on the surface of the epitaxial film. No defects were observed with the other samples.

[Evaluation 2]
All samples were subjected to 5 × 10 ¹¹ / cm ² of spin coat contamination in terms of Cu surface concentration, and then subjected to heat treatment at 900 ° C. for 1 hour. Thereafter, the surface was washed and heated on a hot plate at 400 ° C. for 1 hour. The sample after heating was evaluated with total reflection fluorescent X-rays in order to evaluate the Cu concentration on the surface of the epitaxial film.
The results are shown in FIG. As shown in FIG. 7, in the samples of Comparative Examples 1 and 2, about 1 × 10 ¹² / cm ² of Cu was detected on the surface of the epitaxial film, but in other samples, it was 1 × 10 ¹⁰ / cm ² or less. there were.

[Evaluation 3]
As a simulation of contamination in the device post-process, the back surface of all samples was polished by 2 μm with a slurry intentionally contaminated with 20 ppb of Cu. Thereafter, the surface was washed and heated on a hot plate at 400 ° C. for 1 hour. The sample after heating was evaluated with total reflection fluorescent X-rays in order to evaluate the Cu concentration on the surface of the epitaxial film.
The results are shown in FIG. As shown in FIG. 7, in the samples of Comparative Examples 1 and 2, about 1 × 10 ¹¹ / cm ² of Cu was detected on the surface of the epitaxial film, but in other samples, it was 1 × 10 ¹⁰ / cm ² or less. there were.

[Evaluation 4]
For all samples, productivity was evaluated assuming mass production.
The results are shown in FIG. As shown in FIG. 7, in the samples of Comparative Examples 4 and 5, epitaxial growth is performed twice and the growth film thickness is large, so that it is considered impractical to apply to mass-produced products. Other samples are considered suitable for mass production.

[Discussion]
Considering the above evaluations 1 to 4, the samples of Examples 1 to 3 are considered to be excellent in heavy metal gettering ability and excellent in mass productivity. For this reason, even if the chip is thinned by grinding the back surface of the silicon substrate in the post-device process and further polished on the back surface, it exhibits sufficient gettering ability against heavy metal contamination that can be introduced in the post-device process. Can be considered.
On the other hand, it is considered that the samples of Comparative Examples 1 to 5 have insufficient heavy metal gettering capability or insufficient mass productivity.

10 Silicon wafer 11 Silicon substrate 11a Back surface 11x of silicon substrate Damaged layer 12 Epitaxial film 20 Semiconductor device 30 MCP
31 Package Substrate 32 Adhesive 33 Bonding Wire 34 External Electrode 35 Sealing Resin

Claims (9)

A silicon substrate having a specific resistance based on boron concentration of 2 mΩ · cm to 200 mΩ · cm;
An epitaxial film formed on the surface of the silicon substrate, having a film thickness of 10 μm or less and having a higher specific resistance than the silicon substrate,
A silicon wafer in which ions having a dose of 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less are implanted into a surface layer of the silicon substrate on the epitaxial film side.   The implanted ion species is one or more ion species selected from the group consisting of boron, phosphorus, antimony, arsenic, helium, argon, oxygen, nitrogen, carbon, silicon, and germanium. Item 2. The silicon wafer according to Item 1. ^3. The silicon wafer according to claim 1, wherein an initial oxygen concentration of the silicon substrate is 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. Ion implantation in which ions are implanted at a dose of 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less into a silicon substrate having a specific resistance based on boron concentration of 2 mΩ · cm to 200 mΩ · cm. Process,
An epitaxial process for forming an epitaxial film having a film thickness of 10 μm or less and a higher specific resistance than the silicon substrate on the surface of the silicon substrate on which the ion implantation has been performed. Manufacturing method.   In the ion implantation step, one or more ion species selected from the group consisting of boron, phosphorus, antimony, arsenic, helium, argon, oxygen, nitrogen, carbon, silicon, and germanium are ion-implanted. The method for producing a silicon wafer according to claim 4. 6. The method for producing a silicon wafer according to claim 4, wherein an initial oxygen concentration of the silicon substrate is 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less. Ion implantation in which ions are implanted at a dose of 1 × 10 ¹³ atoms / cm ² or more and 5 × 10 ¹⁵ atoms / cm ² or less into a silicon substrate having a specific resistance based on boron concentration of 2 mΩ · cm to 200 mΩ · cm. Process,
An epitaxial step of forming an epitaxial film having a film thickness of 10 μm or less and a higher specific resistance than the silicon substrate on the surface of the silicon substrate on which the ion implantation has been performed;
A device pre-process for forming a semiconductor element on the epitaxial film;
After performing the device pre-process, by removing a part of the silicon substrate from the back side, a thinning process to make the total thickness of the silicon substrate and the epitaxial film 100 μm or less,
And a back surface polishing step for polishing the back surface of the thinned silicon substrate.   In the ion implantation step, one or more ion species selected from the group consisting of boron, phosphorus, antimony, arsenic, helium, argon, oxygen, nitrogen, carbon, silicon, and germanium are ion-implanted. A method for manufacturing a semiconductor device according to claim 7. 9. The method of manufacturing a semiconductor device according to claim 7, wherein an initial oxygen concentration of the silicon substrate is 7 × 10 ¹⁷ atoms / cm ³ or more and 2.4 × 10 ¹⁸ atoms / cm ³ or less.

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