CN103325679B

CN103325679B - Method for manufacturing back of semiconductor power device

Info

Publication number: CN103325679B
Application number: CN201210081423.1A
Authority: CN
Inventors: 苏冠创
Original assignee: LISHIN SEMICONDUCTOR Inc
Current assignee: LISHIN SEMICONDUCTOR Inc
Priority date: 2012-03-23
Filing date: 2012-03-23
Publication date: 2017-05-10
Anticipated expiration: 2032-03-23
Also published as: CN103325679A

Abstract

The invention discloses a method for manufacturing the back of a semiconductor power device. The method for manufacturing the back of the semiconductor power device includes the following steps that firstly, the back of a silicon sheet which undergoes the previous procedure is ground until the required thickness is reached. Afterwards, a grinding procedure is just performed on a semiconductor substrate and a doping agent is not added yet, the smallest metal layer is formed on the back of the silicon sheet in a sputtering mode or a sediment mode; p type doped ions are filled in the back of the silicon sheet in the filling angle of 7 degrees deviating from the vertical direction and n type doped ions are filled in the back of the silicon sheet in the filling angle of 0 degree deviating from the vertical direction. Afterwards, the p type doping and the n type doping filled in the back of the silicon sheet are activated by undergoing annealing heat treatment to form a p type zone and an n type buffering zone. Finally, multiple metal layers deposit on the back of the silicon sheet and are connected with the p type zone to form a back electrode.

Description

A kind of preparation method of back of semiconductor power device

Technical field

The present invention relates to a kind of manufacturing process of semiconductor power device, more particularly to a kind of semiconductor power The new method of the back side processing technique of the silicon chip of device.

Background technology

The commercialization of IGCT was realized in 1956 by GE (GE).Since then, IGCT is rapid Become the essential core switch of field of power electronics.Many different device architectures are derived by thyristor structure.Device performance Become better and better, power level more and more higher.The IGCT power of early stage, to the initial stage eighties, has developed in several hectowatts or so To MW class.However, the structure of IGCT itself limits its operating frequency.The operating frequency of IGCT is generally below 5KHz, which greatly limits its application.At the initial stage eighties, various high frequency gated power devices are occurred in that, and obtained rapid Development.These devices include (i) power MOS pipe, (ii) IGBT (insulated gate bipolar transistor Insulated Gate Bipolar Transistor), (iii) SIT, (iv) MCT (MOS control thyristor MOS Controlled Thyristor) and V () MGT etc., the end of the nineties, transparent collector junction punch IGBT starts to go into operation, and from that time, IGBT is developed rapidly, and main The market of medium power range has been led, work has been explained by taking IGBT as an example below.

1980, RCA Corp. of the U.S. applied for first IGBT patent, and Toshiba Corp is made that first within 1985 Industrial IGBT.From device physically for, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT- are abbreviated as PT-IGBT).PT-IGBT is manufactured on epitaxial silicon chip, usually in P⁺On substrate One layer of N-shaped relief area of growth, then grows again a n^-Area, will manufacture the resistance to voltage devices of 1200V, just need to grow a N-shaped relief area, mix Miscellaneous concentration is about 1 × 10¹⁷/cm³, thickness is about 10 μm, and then the epitaxy layer thickness of regrowth one is about 110 μm, and doping content is about For 5 × 10¹³/cm³To 1 × 10¹⁴/cm³N^-Area, this is relatively thicker epitaxial layer.To manufacture pressure higher PT-IGBT, As pressure for 2500V or 3300V, then n^-Area needs thicker and higher resistivity.The extension of such specification is grown, is technically had Difficulty, and cost can drastically increase, so, PT-IGBT is typically only applicable to pressure in the range of 400V to 1200V.

The turn-off time of the PT-IGBT of early stage is relatively long, there are about several microseconds, in order to shorten the turn-off time, improves switch Speed, after the nineties, typically all quotes high energy particle irradiation technique (such as electron irradiation, hydrion or helium ion irradiation etc.) and subtracts Excess carrier lifetime in gadget.This method can improve the switching speed of PT-IGBT, but on state voltage can be made to be reduced to subzero temperature Degree coefficient.I.e. in the on-state, if be maintained to flow through, collector current is constant, the voltage difference between current collection best generating pole Can raise with temperature and reduce.In use, if device somewhere local temperature is higher, then has more conducting electric currents and flow through this Place, this can make temperature at this become higher, it is possible to making device enter a positive feedback state, finally device be burnt, This voltage is reduced to the performance deficiency that negative temperature coefficient is PT-IGBT.

As it was previously stated, PT-IGBT is typically only applicable to pressure in the range of 400V to 1200V, pressure it is to manufacture 1700V or 2500V or 3300V or more, early stage, (Non-punchthrough IGBT, were abbreviated as all with non-punch through IGBT NPT-IGBT), device is fabricated directly in thickness and has in hundreds of micron of FZ N-type silicon chips, the p type island region of device collector junction or p-type/N Type area is formed by ion implanting.The voltage of this non-punch through IGBT is reduced to positive temperature coefficient.The structure of this collector junction Also device such as MCT or GTO etc. are used for.Because the doping of collector junction is formed by ion implanting, the dosage of injection can be controlled arbitrarily, If the P-type dopant amount of injection is high, general high hole injection efficiency collector junction (i.e. strong colelctor electrode) can be formed；If injection P-type dopant amount is little, then hole injection efficiency is low, and electronics can effectively flow through p type island region and contact to metal via diffusion Place, this kind of collector junction is referred to as weak collector junction or transparent collector junction (or referred to as transparent collector).During 94 and 95 years, weak collection Electricity knot was once used for NPT-IGBT and GTO (turn-off thyristor Gate Turnoff Thyristor), if weak collector junction side Method is used for manufacturing 600V or 1200V IGBT, then the collector junction of IGBT needs to make the FZ N in only about 60 μm or about 120 μ m-thicks On type silicon chip back side, during 94 and 95 years, industrial quarters does not also have this ultra thin silicon wafers technological ability.

In 1996, motorola inc delivered an article description about manufacturing the research of non-break-through IGBT, stresses The technique that colelctor electrode how is manufactured in thin silicon wafer, FZ N-type silicon chips most thin used there are about 170 μ m-thicks.Next year, Infineon companies have also delivered the NPT-IGBT that 600V is made with the FZ N-type silicon chips of 100 μ m-thicks.It is 99 years or so, industrial new The IGBT of a generation starts to go into operation, and the IGBT of this new generation is a kind of high-speed switching devices, and its voltage is reduced to positive temperature coefficient, It need not with heavy metal or irradiation to shorten device in minority carrier life time, main technology is ultra thin silicon wafers technique plus weak collection Electricity knot (or referred to as transparent collector junction).

The technique of the transparent collector junction punch IGBT of 400V to 1200V is manufactured with FZ N-type silicon chips, two big portions are broadly divided into Divide, i.e. preceding working procedure and later process.Preceding working procedure is mainly made the front structure of device the of FZ N-type silicon chip substrates On one interarea (20).Then it is such as pressure for 1200V FZ silicon chips from the second interarea (30) wear down of substrate to desired thickness, then Desired thickness be about 100 μm it is more.Subsequently into later process, the existing scheme of later process has following several：

Scheme one：

I the back side of the FZ N-type silicon chips of () after wear down technique is completed, with ion implantation phosphonium ion or arsenic ion are injected To required injection depth, general dosage range is 1 × 10¹²/cm³To 5 × 10¹⁵/cm³, Implantation Energy is 500KeV to 2MeV；

(ii) then the p type island region of boron ion injection FZ silicon chip back side formation backrest surfaces, general dosage range is 1 × 10¹³/ cm³To 1 × 10¹⁶/cm³, injection depth is less than 0.5 μm；

(iii) and then with sputtering or deposition process carry out back face metalization, metal level can for aluminum/nickel silver or titanium/nickel/ Silver or other；

(iv) to the phosphonium ion that injects before or arsenic ion or boron ion, annealing activation, typical annealing conditions are required for Be temperature range be 300 DEG C to 450 DEG C, anneal 30 minutes to 100 minutes, annealing steps can formed backplate it Before, or carry out in the middle of backplate step afterwards or being formed.

Scheme two：

Such as scheme one, phosphonium ion or arsenic ion are simply injected using more than one dosage and Implantation Energy, this method can To form the N-shaped relief area of a non-single concentration distribution, whereby can adjustment device turn-off characteristic.

Above several schemes are all with practical value, but they have some shortcomings, to be improved：

(1) when N-shaped relief area dopant is made with phosphonium ion or arsenic ion, need with the injection energy of 500KeV to 2MeV Amount can be only achieved required injection depth, and this high-energy injection can increase production cost；

(2) after FZ silicon chips have just completed wear down operation, the pollution of back surface is minimum, at this moment carries out back surface Aurum metallicum Change, the contact effect on metal-semiconductor surface is best；Existing method is just carried on the back after the step such as injection and annealing Surface metalation, this can make the effect that metal-semiconductor surface contacts be deteriorated；

(3) FZ silicon chips have just been completed after wear down operation, when being that silicon chip is most breakable, because silicon chip surface has metal level And passivation layer, but back surface what does not all have, the stress suffered by FZ thin silicon wafers is relatively large, in ion implanting step is carried out, FZ thin silicon wafers are easily caused to crush.

The content of the invention

It is an object of the invention to propose a kind of to be avoided that a kind of above-mentioned not enough and semiconductor power device of practical The back side of silicon chip, is the new method of the second interarea (30) processing technique of Fig. 2 silicon chips, and implementing the present invention has following several differences Scheme：

Scheme (1)：In the general operation that ion is injected to silicon chip, all the injection direction of silicon chip relative ion is inclined 7 Degree, it is to avoid the channelling effect of ion implanting.The present invention is implementing to inject silicon chip back surface the dopant as N-type buffer layer When, the injection direction of silicon chip relative ion not to be made any inclination or only make a little inclination, such as inclination angle is less than 3 degree, so, with Injection direction inclines 7 degree and compares, and the dopant of N-type buffer layer can be injected needed for silicon chip back surface with less Implantation Energy Depths.The peak of the concentration of dopant of general transparent collector junction requirement N-type buffer layer is from silicon back surface preferably at 0.5 μm Or more, at 1.0 μm or more more preferably, injection doping ionic speciess can be arsenic ion, or phosphonium ion, or sulphion；Extremely In the p-type area of colelctor electrode, then need near back surface, the peak of general p-type area concentration of dopant is less than from silicon back surface 0.5 μm, injection doping ionic speciess are boron ion；Ion note of the one of scheme of the present invention in later process is implemented When entering step, during the dopant of implanted with p-type layer, injector angle is 7 degree of offset from perpendicular (Fig. 3)；Implant n-type undoped buffer layer agent When, injector angle is 0 degree of offset from perpendicular (Fig. 4), and the injection of the p-type dopant of injection or the dopant of N-type buffer layer is successively Order can be random.

Scheme (2)：In back surface implant n-type dopant, if only using single injector angle, single Implantation Energy, Single dosage or single N-shaped dopant species, then the doping concentration distribution of the N-shaped relief area for being formed is single.We Case is with different injector angles, or different Implantation Energies, or different implantation dosages, can form non-single, and the N-shaped of optimization delays Rush the doping concentration distribution in area；Except the different doping injection parameter with more than, it is also possible to different N-shaped dopant species, plus Upper different doping injection direction and Implantation Energy are forming the doping concentration distribution of the N-shaped relief area of optimization, different doping The injection order of injection successively can be random.

Scheme (3)：After silicon chip has just completed wear down operation, before also unimplanted any dopant, just splash in silicon chip back surface Penetrating or deposit minimum has layer of metal layer or a titanium nitride layer 104, and gross thickness is less than 1 μm, and metal material can be aluminum, silver or titanium or its Its metal, then just injects dopant, after completing injection doping, then sputters or deposit required more metal layers completing the back side Electrode metallization step.Annealing can be after injection doping be completed, the pre-treatment of metallization, it is also possible in the middle of metallization step Or carry out afterwards.Annealing conditions be temperature range be 300 DEG C to 450 DEG C, anneal 30 minutes to 100 minutes.In wear down operation The benefit for just enclosing metal as early as possible afterwards is：I () back side has just completed the surface after wear down operation and has not been contaminated, at this moment enclose metal The metal-semiconductor contact for being formed is best.(ii) metal level that the back side is enclosed can add a stress in thin silicon wafer On, this can offset the stress of passivation layer and metal level of the part before silicon chip, subtract the net impact being attached on silicon chip It is little, so that thin silicon wafer has stronger opposing breaking capacity.In scheme (3) the step of injection dopant, the above side can be used Case (1), or the method for scheme (2).

The scheme of the above each back side preparation method can be used for semiconductor power device such as IGBT or MCT or GTO；Also may be used For semiconductor power device such as FRRD or power MOS pipe, it is only necessary to the P in the scheme of the above each back side preparation method Type area doping step is taken away and just may be used.

Description of the drawings

Accompanying drawing is used for providing a further understanding of the present invention, together with embodiments of the present invention for explaining the present invention, It is not construed as limiting the invention, in the accompanying drawings：

Fig. 1 is the surface texture schematic diagram of the formation power device of the embodiment of the present invention 1；

Fig. 2 is that the embodiment of the present invention 1 completes schematic diagram after grinding step；

Fig. 3 is the back surface to silicon chip 100 of the embodiment of the present invention 1 with implant angle as 7 degree of injection p of offset from perpendicular Type doping ion schematic diagram；

Fig. 4 is the back surface to silicon chip 100 of the embodiment of the present invention 1 with implant angle as 0 degree of injection n of offset from perpendicular Type doping ion schematic diagram；

Fig. 5 is the p-type doping and N-shaped doping that back surface is injected into annealing heat-treats activation of the embodiment of the present invention 1 Matter is forming p type island region 102 and the schematic diagram of N-shaped relief area 101；

Fig. 6 is that the back surface deposition more metal layers formation backplate 103 in silicon chip 100 of the embodiment of the present invention 1 is shown It is intended to；

Fig. 7 be the embodiment of the present invention 5 be initially formed after the wear down of silicon chip 10 to desired thickness minimum layer of metal layer or Make injection schematic diagram after titanium nitride layer 104.

Reference markss table：

1 passivation layer

2 aluminium alloy layers

3 inter-level dielectrics

4 highly doped polysilicons

5 N-type source regions

The p-type high-doped zone of 6 contact hole channel bottoms

7 p-type bases

10 it is original it is not thinning before silicon chip

First interarea of 20 silicon chips

Second interarea of 30 silicon chips

100 complete the silicon chip after wear down operation

101 N-shaped relief areas

The p type island region of 102 collector junctions

103 second interarea electrodes (i.e. colelctor electrode)

The wear down of 104 silicon chip 10 to desired thickness, injection doping before formed minimum have layer of metal layer or Titanium nitride layer

The surface texture of 200 power devices

The current collection interface that 201 p type island regions are formed with N-shaped relief area

Specific embodiment

Embodiment 1：

As shown in figure 1, the manufacturing process of the chip of whole power device can be divided into preceding working procedure and later process, front road work Sequence the surface cell of device, such as the MMOS unit makings on IGBT device surface silicon chip 10 front surface, before silicon chip 10 It is the inter-level dielectric 3 of MMOS units, metal level 2 (titanium/titanium nitride layer, tungsten and aluminium alloy) and passivation layer 1 on surface.Manufacture exists Device on the surface of silicon chip 10 can also be MCT or GTO, and silicon chip described here is FZ n-type silicon chips, or CZ n-type silicon chips, Resistance value regarding manufactured device it is pressure depending on, be 1200V Ru pressure, resistance value scope is about the 50 Ω .cm of Ω .cm to 120, thick Spend for the conventional thickness for being used before typically thinning, about 400 μm to 720 μ m-thicks.

Such as Fig. 2, the wear down of silicon chip 10 of front road technique is completed to desired thickness, the resistance to voltage devices of 1200V are such as manufactured, then After the completion of wear down operation, thickness is about 110 μm, and silicon chip 10 becomes silicon chip 100.

As shown in figure 3, inject boron dope agent to the back surface of silicon chip 100, implant angle is 7 degree of offset from perpendicular, agent Amount scope is 1 × 10¹³/cm³To 1 × 10¹⁶/cm³, Implantation Energy scope is 20KeV to 200KeV.

As shown in figure 4, inject sulfur doping agent to the back surface of silicon chip 100, implant angle is 0 degree of offset from perpendicular, agent Amount scope is 1 × 10¹²/cm³To 5 × 10¹⁵/cm³, Implantation Energy scope is 200KeV to 2MeV.

As shown in figure 5, silicon chip 100 is placed in into temperature range for 300 DEG C to 450 DEG C, anneal 30mins to 100mins, moves back Boron and sulfur doping agent activation of the fiery step injection, forms the p type island region and N-type relief area of collector junction.

As shown in fig. 6, the back surface of silicon chip 100 is metallized with sputtering or deposition process, as the backplate of device, gold Category layer material can be A1/Ti/Ni/Ag or Ti/Ni/Ag or A1/Ti/Ni/Au etc..

In embodiment 1, annealing can also complete backplate metallization after or overleaf electrode metallization step work as In carry out.

Embodiment 2：

The technical scheme of the present embodiment is roughly the same with embodiment 1, and it is differed only in：

In above-described embodiment 1, to silicon chip 100 back surface injection sulfur doping matter instead of injection phosphonium ion or arsenic from Son, implant angle is 0 degree of offset from perpendicular, and dosage range is 1 × 10¹²/cm³To 5 × 10¹⁵/cm³, Implantation Energy scope is 200KeV to 2MeV.

Embodiment 3：

In above-described embodiment 1, in the back surface injection sulfur doping to silicon chip 100, injection sulfur doping number of times is more than one Secondary, the injection parameter of injection parameter each time from another time is different, and injection parameter includes implant angle, implantation dosage and Implantation Energy.

Embodiment 4：

The technical scheme of the present embodiment is roughly the same with embodiment 3, and it is differed only in：

It is many instead of injection phosphorus more than once in the back surface injection sulfur doping agent to silicon chip 100 in above-described embodiment 3 In once, or injection arsenic is more than once, and the injection parameter of injection parameter each time from another time is different, injection parameter bag Include implant angle, implantation dosage and Implantation Energy.

Embodiment 5：

In above-described embodiment 1, after the wear down of silicon chip 10 to desired thickness；Make any in the back surface to silicon chip 100 Before injection, first minimum layer of metal layer or titanium nitride layer 104 are formed in the back surface of silicon chip 100 with sputtering or deposition process, gold Category layer can be aluminum, or aluminium alloy, or silver, or gold, or titanium, or tungsten, and thickness is about 0.05 μm to 1.0 μm, injects afterwards, moves back As described in Example 1 step is identical with the step such as surface metalation for fire.

Other embodiment：

The technical scheme of other embodiment and embodiment 2, or embodiment 3, or embodiment 4 is roughly the same, its difference only exists In：

In the various embodiments described above, after the wear down of silicon chip 10 to desired thickness；Make any in the back surface to silicon chip 100 Before injection, first minimum layer of metal layer or titanium nitride layer 104 are formed in the back surface of silicon chip 100 with sputtering or deposition process, gold Category layer can be aluminum, or aluminium alloy, or silver, or gold, or titanium, or tungsten, and thickness is about 0.05 μm to 1.0 μm, injects afterwards, moves back Fire and the step such as each embodiment such as surface metalation in state step identical.

Finally it should be noted that：The preferred embodiments of the present invention are these are only, the present invention is not limited to, this It is bright can be used to being related to manufacturing semiconductor power device (for example, insulated trench gate bipolar transistor Trench IGBT or MCT or GTO), the content of the invention of presents with embodiment is made an explanation with N-type passage device, and the present invention also can be used for p-type passage device Part, although being described in detail to the present invention with reference to embodiment, for a person skilled in the art, it still can be with Technical scheme described in foregoing embodiments is modified, or equivalent is carried out to which part technical characteristic, but It is all any modification, equivalent substitution and improvements within the spirit and principles in the present invention, made etc., should be included in the present invention Protection domain within.

Claims

1. a kind of preparation method of back of semiconductor power device, it is characterised in that comprise the following steps：

(1) a kind of semi-conductor silicon chip (10) is partly led with the first interarea (20) and the second interarea (30) relative to each other described First interarea (20) side of body silicon chip (10) forms the surface texture (200) of power device；

(2) grinding has formed second interarea (30) of the semi-conductor silicon chip (10) of the surface texture (200) of power device；

(3) after semi-conductor silicon chip just completes grinding step, before also unimplanted any dopant, just the second of semi-conductor silicon chip Interarea (30) surface deposits layer of metal layer or titanium nitride layer (104)；

(4) complete to form p on the second interarea (30) after deposition layer of metal layer or titanium nitride layer (104) in semi-conductor silicon chip Type area (102), the manufacturing process of p-type area (102) is comprising implanted with p-type doping ion to described the second of the semi-conductor silicon chip Interarea (30), implant angle is 7 degree of offset from perpendicular；

(5) complete to form n on the second interarea (30) after deposition layer of metal layer or titanium nitride layer (104) in semi-conductor silicon chip Type relief area (101), the manufacturing process of N-shaped relief area (101) includes implant n-type doping ion to the semi-conductor silicon chip Second interarea (30), implant angle scope is 0 degree of offset from perpendicular；

(6) the p-type doping ion and N-shaped doping ion implanting described in the second interarea (30) passes through afterwards at same annealing heat Reason is activated；

(7) the second interarea electrode (103) is formed on described the second interarea (30), the second interarea electrode (103) has The described p-type area (102) of more metal layers connection.

2. the preparation method of back of semiconductor power device according to claim 1, it is characterised in that：Described quasiconductor Power device can be IGBT or MCT or GTO.

3. the preparation method of back of semiconductor power device according to claim 1, it is characterised in that：In step (4) The injection parameter of described implanted with p-type doping ion be injector angle be 7 degree of offset from perpendicular, implantation dosage scope be 1 × 10¹³/cm³To 1 × 10¹⁶/cm³, less than 0.5 μm, injection species is boron ion to injection depth；Injection n described in step (5) It is 0 degree of offset from perpendicular that the injection parameter of type doping ion is injector angle, and implantation dosage scope is 1 × 10¹²/cm³To 5 × 10¹⁵/cm³, injection depth is more than 0.5 μm, and injection species is arsenic ion, or phosphonium ion, or sulphion；Described implanted with p-type is mixed The injection order of foreign ion and described implant n-type doping ion successively can be random.

4. the preparation method of back of semiconductor power device according to claim 1, it is characterised in that：In step (5) Described implant n-type doping ion, minimum has two kinds of different injection parameters, and injection parameter includes injection depth, injection Dosage, injects species；The injection time of implanted with p-type doping ion in the N-shaped doping ion and step (4) of injection different parameters Sequence successively can be random.

5. the preparation method of back of semiconductor power device according to claim 1, it is characterised in that：In step (6) The annealing conditions of the annealing heat-treats are 300 DEG C to 450 DEG C of temperature range, are annealed 30 minutes to 100 minutes, annealing heat-treats Can carry out after complete step (4) and step (5)；Can also carry out after step (7) is completed or in step (7) is carried out it is complete Into.

6. the preparation method of back of semiconductor power device according to claim 1, it is characterised in that：In step (3) The second interarea (30) the surface deposition layer of metal layer or titanium nitride layer (104) in semi-conductor silicon chip；Metal layer material can Being aluminum, or aluminium alloy, or silver, or gold, or titanium, or tungsten, thickness is 0.05 μm to 1.0 μm.

7. the preparation method of back of semiconductor power device according to claim 1, it is characterised in that：In step (7) The second interarea electrode (103), with the metal level stacked gradually from the second interarea (30) side be aluminium lamination, titanium layer, Nickel dam and silver layer；The metal level for stacking gradually can also be aluminium lamination, titanium layer, nickel dam and layer gold, or titanium layer, nickel dam and silver layer.

8. a kind of preparation method of back of semiconductor power device, it is characterised in that comprise the following steps：

(3) after semi-conductor silicon chip just completes grinding step, before also unimplanted any dopant, just the second of semi-conductor silicon chip Interarea (30) deposits layer of metal layer or titanium nitride layer (104)；

(4) n-type area is formed on second interarea (30) of semi-conductor silicon chip after, the manufacturing process of n-type area is mixed comprising implant n-type To second interarea (30) of the semi-conductor silicon chip, implant angle is 0 degree of offset from perpendicular to foreign ion；

(5) the N-shaped doping ion of the second interarea (30) is injected into annealing heat-treats activation；

(6) the second interarea electrode (103) is formed on described the second interarea (30), the second interarea electrode (103) has The described n-type area of multiple layer metal connection.

9. the preparation method of back of semiconductor power device according to claim 8, it is characterised in that：Described quasiconductor Power device can be fast-recovery commutation diode or power MOS pipe.

10. the preparation method of back of semiconductor power device according to claim 8, it is characterised in that：In step (4) It is 0 degree of offset from perpendicular that the injection parameter of described implant n-type doping ion is implant angle, and implantation dosage scope is 1 ×10¹²/cm³To 5 × 10¹⁵/cm³, Implantation Energy scope is 200KeV to 2MeV, and injection species can be arsenic ion, or phosphorus from Son, or sulphion.