CN103325679A - Method for manufacturing back of semiconductor power device - Google Patents
Method for manufacturing back of semiconductor power device Download PDFInfo
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- CN103325679A CN103325679A CN2012100814231A CN201210081423A CN103325679A CN 103325679 A CN103325679 A CN 103325679A CN 2012100814231 A CN2012100814231 A CN 2012100814231A CN 201210081423 A CN201210081423 A CN 201210081423A CN 103325679 A CN103325679 A CN 103325679A
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Abstract
The invention discloses a method for manufacturing the back of a semiconductor power device. The method for manufacturing the back of the semiconductor power device includes the following steps that firstly, the back of a silicon sheet which undergoes the previous procedure is ground until the required thickness is reached. Afterwards, a grinding procedure is just performed on a semiconductor substrate and a doping agent is not added yet, the smallest metal layer is formed on the back of the silicon sheet in a sputtering mode or a sediment mode; p type doped ions are filled in the back of the silicon sheet in the filling angle of 7 degrees and n type doped ions are filled in the back of the silicon sheet in the filling angle of 0 degree. Afterwards, the p type doping and the n type doping filled in the back of the silicon sheet are activated by undergoing annealing heat treatment to form a p type zone and an n type buffering zone. Finally, multiple metal layers deposit on the back of the silicon sheet and are connected with the p type zone to form a back electrode.
Description
Technical field
The present invention relates to a kind of manufacturing process of semiconductor power device, more particularly relate to a kind of new method of back side processing technology of silicon chip of semiconductor power device.
Background technology
The commercialization of thyristor is realized in 1956 by GE (GE).Since then, thyristor becomes rapidly the main core switching of field of power electronics.Derive a lot of different device architectures by thyristor structure.Device performance is become better and better, and power level is more and more higher.Early stage thyristor power to the initial stage eighties, has been developed to MW class about several hectowatts.Yet, the structural limitations of thyristor itself its operating frequency.The operating frequency of thyristor generally is lower than 5KHz, and this has limited its application greatly.At the initial stage eighties, multiple high frequency gated power device occurred, and obtained developing rapidly.These devices comprise (i) power MOS pipe, (ii) IGBT (insulated gate bipolar transistor Insulated Gate Bipolar Transistor), (iii) SIT, (iv) MCT (MOS control thyristor MOS Controlled Thyristor) and (v) MGT etc., the end of the nineties, transparent collector junction punch IGBT begins to go into operation, from that time, IGBT develops rapidly, and dominated the market of medium power range, below explain work as an example of IGBT example.
1980, U.S. RCA Corp. applied for first IGBT patent, and Toshiba Corp had made first industrial IGBT in 1985.On the physical structure of device, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT-is abbreviated as PT-IGBT).PT-IGBT is manufactured on the epitaxial silicon chip, generally is at P
+Grown one deck N-shaped buffering area, and then a long n
-The district will make the withstand voltage device of 1200V, the N-shaped buffering area that just needs to grow, and doping content is about 1 * 10
17/ cm
3, thickness is about 10um, and then the epitaxy layer thickness of growing is about 110um, and doping content is about 5 * 10
13/ cm
3To 1 * 10
14/ cm
3N
-The district, this is quite thick epitaxial loayer.If make withstand voltage higher PT-IGBT, as withstand voltage be 2500V or 3300V, then n
-The district needs thicker and higher resistivity.The extension of such specification of growing, technical having any problem, and also cost can sharply increase, so PT-IGBT generally is only applicable to withstand voltage in 400V to the 1200V scope.
The turn-off time of early stage PT-IGBT is relatively very long, and several microseconds are approximately arranged, in order to shorten the turn-off time, improve switching speed, after the nineties, generally all quote high energy particle irradiation technique (such as electron irradiation, hydrogen ion or helium ion irradiation etc.) and reduce the excess carrier life-span in the device.This method can improve the switching speed of PT-IGBT, but can make on state voltage reduce to negative temperature coefficient.Namely under conducting state, if the collector current that keeps flowing through is constant, then collector electrode to the voltage difference of generating electricity between the utmost point can reduce with the temperature rising.When using, if device somewhere local temperature is higher, then have more On currents this place that flows through, this can make this place's temperature become higher, thereby might make device enter a positive feedback state, at last device be burnt, this voltage is reduced to the performance deficiency that negative temperature coefficient is PT-IGBT.
As previously mentioned, PT-IGBT generally is only applicable to withstand voltage in 400V to the 1200V scope, if make withstand voltage for 1700V or 2500V or 3300V or more than, all use in early days non-punch through IGBT (Non-punchthrough IGBT, be abbreviated as NPT-IGBT), device is fabricated directly in thickness to be had on the FZN type silicon chip of hundreds of micron, and the p type island region of device collector junction or P type/N-type district are formed by Implantation.The voltage of this non-punch through IGBT is reduced to positive temperature coefficient.The structure of this collector junction also is used to device such as MCT or GTO etc.Because the doping of collector junction is formed by Implantation, the dosage of injection can arbitrarily be controlled, if the P type dopant dose that injects is high, then can form general high hole injection efficiency collector junction (being strong collector electrode); If the P type dopant dose that injects is little, then hole injection efficiency is low, and electronics can flow through p type island region to the metal connecting synapsis effectively via diffusion, collector junction or transparent collector junction (or being called transparent collector) a little less than this class collector junction is called as.During 94 and 95 years, weak collector junction once was used to NPT-IGBT and GTO (turn-off thyristor Gate Turnoff Thyristor), if weak collector junction method is used for making 600V or 1200VIGBT, then the collector junction of IGBT need to be made on only have an appointment 60um or FZ N-type silicon chip back side that approximately 120um is thick, during 94 and 95 years, industrial quarters does not also have this ultra thin silicon wafers technological ability.
In 1996, motorola inc delivered the research that the relevant non-break-through IGBT of manufacturing described in one piece of article, stressed how to make at the thin silicon sheet technique of collector electrode, and the thinnest used of FZ N-type silicon chip approximately has 170um thick.In next year, Infineon company has also delivered the NPT-IGBT that makes 600V with the thick FZ N-type silicon chip of 100um.About 99 years, the IGBT of industrial a new generation begins to go into operation, the IGBT of this a new generation is a kind of high-speed switching devices, its voltage is reduced to positive temperature coefficient, it does not need to shorten minority carrier life time in the device with heavy metal or irradiation, and the technology of main usefulness is that ultra thin silicon wafers technique adds weak collector junction (or being called transparent collector junction).
Make the technique of the transparent collector junction punch of 400V to 1200V IGBT with FZN type silicon chip, mainly be divided into the two large divisions, i.e. preceding working procedure and later process.Preceding working procedure mainly is that the front structure of device is made on the surface of FZN type silicon chip.Then FZ silicon chip wear down to desired thickness, as withstand voltage be 1200V, then to be about 100um more for desired thickness.Then enter later process, the existing scheme of later process has following several:
Scheme one:
(i) phosphonium ion or arsenic ion are injected to the required injection degree of depth with ion implantation in the back side of the FZ N-type silicon chip after finishing wear down technique, and general dosage range is 1 * 10
12/ cm
3To 5 * 10
15/ cm
3, Implantation Energy is 500KeV to 2MeV;
(ii) then the p type island region of boron Implantation FZ silicon chip back side formation backrest face, general dosage range is 1 * 10
13/ cm
3To 1 * 10
16/ cm
3, inject the degree of depth less than 0.5um;
(iii) then carry out back face metalization with sputter or deposition process, metal level can be aluminium/nickel/silver or titanium/nickel/silver or other;
(iv) phosphonium ion or arsenic ion or the boron ion to injecting before, all need annealing to activate, typical annealing conditions is to be 300 ℃ to 450 ℃ in temperature range, annealed 30 minutes to 100 minutes, annealing steps can be before forming backplate, or carry out afterwards or in the middle of forming the backplate step.
Scheme two:
Such as scheme one, just do not inject phosphonium ion or arsenic ion, but hydrogen injecting ion or sulphion are used as the N-shaped dopant, such as hydrogen injecting, implantation dosage is 1 * 10
13/ cm
3To 1 * 10
16/ cm
3, Implantation Energy is 150KeV to 500KeV.
Scheme three:
Such as scheme one, just to use more than a kind of dosage and Implantation Energy and inject phosphonium ion or arsenic ion or hydrogen ion, this method can form the N-shaped buffering area of a non-single CONCENTRATION DISTRIBUTION, but adjustment device turn-off characteristic whereby.
Above several scheme is all with practical value, but they have some shortcomings, and is to be improved:
(1) when making N-shaped buffering area dopant with phosphonium ion or arsenic ion, need to just can reach the required injection degree of depth with the Implantation Energy of 500KeV to 2MeV, this high-energy injects can increase production cost;
When (2) using hydrogen as N-shaped buffering area dopant, Implantation Energy just can reach the general required injection degree of depth at 150KeV to 200KeV, but, the hydrogen that injects can produce some defectives, these defectives can make the N-shaped concentration ratio N-shaped buffering area peak concentration on FNN type silicon chip back of the body surface also high, and this can cause harmful effect to device;
(3) after the FZ silicon chip has just been finished the wear down operation, the pollution on back of the body surface is minimum, at this moment carries on the back the surface metal aurification, and the contact effect on metal-semiconductor surface is best; Existing method be through injection and the step such as annealing after just carry on the back surface metalation, this can make the deleterious of metal-semiconductor Surface Contact;
(4) after the FZ silicon chip has just been finished the wear down operation, be that silicon chip is the most breakable the time, because silicon chip surface has metal level and passivation layer, but what does not all have on back of the body surface, the suffered stress of FZ thin silicon sheet is relatively large, in carrying out the Implantation step, causes that easily FZ thin silicon sheet is broken.
Summary of the invention
The object of the invention is to propose a kind ofly can avoid above-mentioned deficiency and the new method of the back side processing technology of a kind of semiconductor power device silicon chip of practical, implementing the present invention has following several different scheme:
Scheme (1): in the general operation to the silicon chip ion, all the injection direction of the relative ion of silicon chip inclination 7 degree, avoid the channeling effect of Implantation.The present invention is when implementing that silicon chip back of the body surface injected dopant as the N-shaped resilient coating, the injection direction of the relative ion of silicon chip is not done any inclination or only done a little inclination, be less than 3 degree such as the inclination angle, like this, compare with injection direction inclination 7 degree, available less Implantation Energy injects the dopant of N-shaped resilient coating carries on the back surperficial required depths from silicon chip.General transparent collector junction require the N-shaped resilient coating concentration of dopant peak from silicon back of the body surface be preferably in 0.5um or more than, at 1.0um or above better, dopant implant matter ionic species can be hydrogen ion, or the helium ion, or phosphonium ion, or sulphion; As for the p-type district of collector electrode, then need near back of the body surface, less than 0.5um, dopant implant matter ionic species is the boron ion to the peak of general p-type district concentration of dopant from silicon back of the body surface; During the Implantation step of one of them scheme of the present invention in implementing later process, when injecting the dopant of p-type layer, injector angle is 7 degree (Fig. 4); During the agent of Implanted n-Type undoped buffer layer, injector angle is 0 degree (Fig. 5), and the injection precedence of the p-type dopant of injection or the dopant of N-shaped resilient coating can be random.
Scheme (2): in the doping situation take the hydrogen injecting ion as N-shaped, before or after hydrogen injecting, inject helium on back of the body surface, inject the degree of depth less than 0.5um, the implantation dosage scope is 1 * 10
12/ cm
3To 5 * 10
14/ cm
3, the harmful effect that this defective that produces in the time of can offsetting hydrogen injecting causes.
Scheme (3): in the doping situation take the hydrogen injecting ion as N-shaped, the hydrogen that injects on back of the body surface can produce defective at back of the body near surface, the hydrogen that injects can see through defective and go to back of the body surface, too many hydrogen is gone to the back side can cause harmful effect, this programme is before or after hydrogen injecting, inject nitrogen on back of the body surface, inject the degree of depth less than 0.5um, the implantation dosage scope is 1 * 10
12/ cm
3To 5 * 10
14/ cm
3, the nitrogen of injection can stop that the hydrogen particle sees through defective and goes to back of the body surface.
Scheme (4): when the surperficial Implanted n-Type dopant of the back of the body, if only use single injector angle, single Implantation Energy, single dosage or single N-shaped dopant species, then the doping concentration distribution of formed N-shaped buffering area is single.This programme is with different injector angles, or different Implantation Energies, or different implantation dosages, can form non-single, the doping concentration distribution of the N-shaped buffering area of optimization; Except with above different doping injection parameter, also can be with different N-shaped dopant species, such as the phosphorus hydrogenation, add the doping concentration distribution of the N-shaped buffering area that different doping injection directions and Implantation Energy form optimization, the injection order that different doping is injected successively can be random.
Scheme (5): after silicon chip has just been finished the wear down operation, before also not injecting any dopant, just at silicon chip back of the body surface sputtering or deposition minimum layer of metal layer 104 is arranged, gross thickness is less than 1um, metal material can be aluminium, silver or titanium or other metal, then just dopant implant agent, after finishing dopant implant, again sputter or deposit required multiple layer metal layer and finish the backplate metallization step.Annealing can be processed before the metallization after finishing dopant implant, also can carry out in the middle of metallization step or afterwards.Annealing conditions is to be 300 ℃ to 450 ℃ in temperature range, anneals 30 minutes to 100 minutes.In the benefit of just enclosing as early as possible metal after the wear down operation be: the surface after (i) the wear down operation has just been finished at the back side does not have contaminated, and it is best at this moment enclosing the formed metal-semiconductor contact of metal.(ii) metal level enclosed of the back side can add a stress on the thin silicon sheet, and this can offset a part from the passivation layer of silicon chip front and the stress of metal level, the clean stress that is attached on the silicon chip is reduced, thereby make the thin silicon sheet that stronger opposing breaking capacity be arranged.The step of dopant implant agent in the scheme (5), available the above scheme (1), or scheme (2), or scheme (3), or the method for scheme (4).
The above each back side preparation method's scheme can be used for semiconductor power device such as IGBT or MCT or GTO; Also can be used for semiconductor power device such as FRRD or power MOS pipe, can just only need to take away the p type island region doping step in the above each back side preparation method's the scheme.
Description of drawings
Accompanying drawing is used to provide a further understanding of the present invention, is used for together with embodiments of the present invention explaining the present invention, be not construed as limiting the invention, in the accompanying drawings:
Fig. 1 is the surface texture schematic diagram of the formation power device of the embodiment of the invention 1;
Fig. 2 is the schematic diagram behind the grinding step of finishing of the embodiment of the invention 1;
Fig. 3 is that p-type doping ion schematic diagram is injected on the back of the body surface to silicon chip 100 of the embodiment of the invention 1 take implant angle as 7 degree;
Fig. 4 be the embodiment of the invention 1 to the back of the body surface of silicon chip 100 take implant angle as 0 degree Implanted n-Type doping ion schematic diagram;
Fig. 5 is activating p-type doping and the N-shaped doping be injected into back of the body surface with annealing heat treatment and forming p type island region 102 and N-shaped buffering area 101 schematic diagrames of the embodiment of the invention 1;
Fig. 6 is that the back of the body surface deposition multiple layer metal layer at silicon chip of the embodiment of the invention 1 forms backplate 103 schematic diagrames;
Fig. 7 is that the work silicon chip 10 wear downs form first minimum layer of metal layer 104 to desired thickness after of the embodiment of the invention 5 injects schematic diagram.
The reference symbol table:
1 passivation layer
2 aluminium alloy layers
3 inter-level dielectrics
4 highly doped polysilicons
5 N-type source regions
The P type high-doped zone of 6 contact hole channel bottoms
7 P type bases
Substrate before the 10 original not attenuates
100 finish the substrate after the wear down operation
101 N-shaped buffering areas
The p type island region of 102 collector junctions
103 backplates (being collector electrode)
104 silicon chips, 10 wear downs are to desired thickness, and the minimum that formed before dopant implant matter has the layer of metal layer
The surface texture of 200 power devices
The current collection interface that 201 p type island regions and N-shaped buffering area form
Embodiment
Embodiment 1:
As shown in Figure 1, the manufacturing process of the chip of whole power device can be divided into preceding working procedure and later process, preceding working procedure is the surface cell of device, be manufactured on the front surface of silicon chip 10 such as the UMOS unit of IGBT device surface, it is the inter-level dielectric 3 of UMOS unit on the front surface of silicon chip, metal level 2 (titanium/titanium nitride layer, tungsten and aluminium alloy) and passivation layer 1.Being manufactured on silicon chip 10 lip-deep devices also can be MCT or GTO, silicon chip described here is FZn type silicon chip, or CZn type silicon chip, resistance value is decided on the withstand voltage of manufacturing device, as withstand voltage be 1200V, the resistance value scope is about 50 Ω .cm to 120 Ω .cm, and thickness is general conventional employed thickness before the attenuate not, is about 400um to 720um thick.
Such as Fig. 2, to desired thickness, as making the withstand voltage device of 1200V, after then the wear down operation was finished, thickness was about 110um silicon chip 10 wear downs of finishing front road technique, and silicon chip 10 becomes silicon chip 100.
As shown in Figure 3, to the back of the body surface B Implanted dopant of silicon chip 100, implant angle is 7 degree, and dosage range is 1 * 10
13/ cm
3To 1 * 10
16/ cm
3, the Implantation Energy scope is 20KeV to 200KeV.
As shown in Figure 4, to the back of the body surface hydrogen injecting dopant of silicon chip 100, implant angle is 0 degree, and dosage range is 1 * 10
12/ cm
3To 5 * 10
15/ cm
3, the Implantation Energy scope is 100KeV to 2MeV.
As shown in Figure 5, it is 300 ℃ to 450 ℃ that silicon chip 100 is placed temperature range, annealing 30mins to 100mins, and annealing steps activates the boron that injects and hydrogen doping agent, forms p type island region and the N-type buffering area of collector junction.
As shown in Figure 6, with sputter or deposition process silicon chip 100 is carried on the back surface metalations, as the backplate of device, metal layer material can be Al/Ti/Ni/Ag or Ti/Ni/Ag or Al/Ti/Ni/Au etc.In embodiment 1, annealing also can or be carried out in the middle of the electrode metal step after finishing the backplate metallization overleaf.
Embodiment 2:
The technical scheme of the present embodiment and embodiment 1 are roughly the same, and its difference only is:
In above-described embodiment 1, in silicon chip 10 wear downs to desired thickness; With sputter or deposition process silicon chip 100 back of the body surface metalations before, to the back of the body surface of silicon chip 100 except B Implanted dopant and hydrogen doping agent; Also inject nitrogen or helium, inject the degree of depth surperficial less than 0.5um from the back of the body, dosage range is 1 * 10
12/ cm
3To 5 * 10
14/ cm
3The boron ion that injects, or hydrogen ion, or the order of nitrogen ion or helium ion successively can be random, finish and just anneal after all inject, annealing region is 300 ℃ to 450 ℃, and the time is 30mins to 100mins, and annealing also can or be carried out in the middle of the electrode metal step after finishing the backplate metallization overleaf.
Embodiment 3:
The technical scheme of the present embodiment and embodiment 1 are roughly the same, and its difference only is:
In above-described embodiment 1, to the back of the body of silicon chip 100 surface hydrogen injecting dopant instead of injecting the helium ion, or phosphonium ion or arsenic ion or sulphion, implant angle is 0 degree, dosage range is 1 * 10
12/ cm
3To 5 * 10
15/ cm
3, the Implantation Energy scope is 200KeV to 2MeV.
Embodiment 4:
The technical scheme of the present embodiment and embodiment 1 are roughly the same, and its difference only is:
In above-described embodiment 1, when the back of the body surface hydrogen injecting to silicon chip 100 mixes, hydrogen injecting doping number of times is more than once, injection parameter each time is different from the injection parameter of another time, injection parameter comprises implant angle, implantation dosage and Implantation Energy, for example hydrogen injecting doping secondary, wherein once implant angle is 0 degree, and dosage range is 1 * 10
12/ cm
3To 5 * 10
13/ cm
3, the Implantation Energy scope is 300KeV to 2MeV; The implant angle of another time is 0 degree, and dosage range is 5 * 10
13/ cm
3To 5 * 10
15/ cm
3, the Implantation Energy scope is 100KeV to 500KeV, also can be other combinations.
Embodiment 5:
The technical scheme of the present embodiment and embodiment 4 are roughly the same, and its difference only is:
In above-described embodiment 4, to the back of the body of silicon chip 100 surface hydrogen injecting dopant more than once instead of injecting phosphorus more than once, or inject arsenic more than once, or inject sulphur more than once, and or hydrogen injecting and phosphorus, or hydrogen injecting and phosphorus are more than once, or hydrogen injecting and helium, or hydrogen injecting and arsenic, or hydrogen injecting and arsenic is more than once, or hydrogen injecting and sulphur, or hydrogen injecting and sulphur are more than once, injection parameter each time is different from the injection parameter of another time, and injection parameter comprises implant angle, implantation dosage and Implantation Energy, Implanted n-Type doping secondary for example, hydrogen injecting dopant wherein, implant angle are 0 degree, dosage 1 * 10
12/ cm
3To 5 * 10
13/ cm
3, Implantation Energy is 300KeV to 2MeV; The injection phosphorus dopant of another time, implant angle are 0 degree, and dosage is 5 * 10
13/ cm
3To 5 * 10
15/ cm
3, Implantation Energy is 500KeV to 2MeV.
Embodiment 6:
The technical scheme of the present embodiment and embodiment 4 are roughly the same, and its difference only is:
In above-described embodiment 4, in silicon chip 10 wear downs to desired thickness; With sputter or deposition process silicon chip 100 back of the body surface metalations before, to the back of the body surface of silicon chip 100 except the B Implanted dopant with inject more than the hydrogen doping agent; Also inject nitrogen or helium, inject the degree of depth surperficial less than 0.5um from the back of the body, dosage range is 1 * 10
12/ cm
3To 5 * 10
14/ cm
3, the boron of injection can be random more than the order of once hydrogen and nitrogen or helium, finish and just anneal after all inject, annealing temperature is 300 ℃ to 450 ℃, and the time is 30mins to 100mins, and annealing also can or be carried out in the middle of the electrode metal step after finishing the backplate metallization overleaf.
Embodiment 7:
The technical scheme of the present embodiment and embodiment 1 are roughly the same, and its difference only is:
In above-described embodiment 1, in silicon chip 10 wear downs to desired thickness; Before any injection is done on the back of the body surface of silicon chip 100, form minimum layer of metal layer 104 with sputter or deposition process on silicon chip 100 back of the body surfaces first, metal level can be aluminium, or aluminium alloy, or silver, or gold, or titanium, or titanium nitride, or tungsten, thickness is about 0.05um to 1.0um, injects afterwards, and step is identical as described in Example 1 with the step such as surface metalation in annealing.
Other embodiment:
The technical scheme of other embodiment and embodiment 2, or embodiment 3, or embodiment 4, or embodiment 5, or embodiment 6 is roughly the same, and its difference only is:
In the various embodiments described above, in silicon chip 10 wear downs to desired thickness; Before any injection is done on the back of the body surface of silicon chip 100, form minimum layer of metal layer 104 with sputter or deposition process on silicon chip 100 back of the body surfaces first, metal level can be aluminium, or aluminium alloy, or silver, or gold, or titanium, or titanium nitride, or tungsten, thickness is about 0.05um to 1.0um, inject afterwards, annealing and the step such as surface metalation such as each embodiment in to state step identical.
It should be noted that at last: above only is the preferred embodiments of the present invention; be not limited to the present invention; the present invention (for example can be used for relating to the manufacturing semiconductor power device; insulated trench gate bipolar transistor Trench IGBT or MCT or GTO); the summary of the invention of presents and embodiment make an explanation with the N-type passage device; the present invention also can be used for P type passage device; although with reference to embodiment the present invention is had been described in detail; for a person skilled in the art; it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing; perhaps part technical characterictic wherein is equal to replacement; but within the spirit and principles in the present invention all; any modification of doing; be equal to replacement; improve etc., all should be included within protection scope of the present invention.
Claims (18)
1. the preparation method at a semiconductor power device back side is characterized in that, may further comprise the steps:
(1) a kind of Semiconductor substrate (10) has the first interarea respect to one another (20) and the second interarea (30), forms the surface texture (200) of power device in the first interarea side of described Semiconductor substrate;
(2) grind second interarea (30) of the Semiconductor substrate that has formed the power device surface texture to desired thickness;
(3) the second interarea after Semiconductor substrate is finished grinding step forms p-type district (102), and the production process in p-type district comprises injection p-type doping ion to described second interarea of described Semiconductor substrate, and the implant angle scope is that 5 degree are to 7 degree;
(4) the second interarea after Semiconductor substrate is finished grinding step forms N-shaped buffering area (101), the production process of N-shaped buffering area comprises Implanted n-Type doping ion to described second interarea of described Semiconductor substrate, and the implant angle scope is that 0 degree is to 3 degree;
(5) described p-type and N-shaped Implantation are activated by same annealing heat treatment behind the second interarea;
(6) form backplate (103) at described the second interarea, have the multiple layer metal layer, connect described p-type district (102).
2. the preparation method at the semiconductor power device back side of putting down in writing according to claim 1, it is characterized in that: described semiconductor power device is IGBT or MCT or GTO.
3. the preparation method at the semiconductor power device back side of putting down in writing according to claim 1 is characterized in that: the injection parameter at the injection p-type doping ion described in the step (3) is that injector angle equals 7 degree, and the implantation dosage scope is 1 * 10
13/ cm
3To 1 * 10
16/ cm
3, inject the degree of depth less than 0.5um, injecting kind is the boron ion; Injection parameter at the Implanted n-Type doping ion described in the step (4) is that injector angle equals 0 degree, and the implantation dosage scope is 1 * 10
12/ cm
3To 5 * 10
15/ cm
3, inject the degree of depth greater than 0.5um, the injection kind is hydrogen ion, or the helium ion, or phosphonium ion, or sulphion; The injection order of described injection p-type foreign ion and described Implanted n-Type foreign ion successively can be random.
4. the preparation method at the semiconductor power device back side of putting down in writing according to claim 1, it is characterized in that: be in the hydrionic situation at the Implanted n-Type doping described in the step (4), additional helium ion or the nitrogen ion of injecting, inject the degree of depth less than 0.5um, the injector angle scope be 0 the degree to 7 the degree, the implantation dosage scope is 1 * 10
12/ cm
3To 5 * 10
14/ cm
3The injection order of the B Implanted ion described in described hydrogen injecting ion or injection helium ion or injecting nitrogen ion or the step (3) successively can be random.
5. the preparation method at the semiconductor power device back side of putting down in writing according to claim 1, it is characterized in that: at the Implanted n-Type foreign ion described in the step (4), minimum has two kinds of different injection parameters, and injection parameter includes the injection degree of depth, implantation dosage injects kind; The N-shaped foreign ion of injection different parameters and the injection order of the injection p-type foreign ion described in the step (3) successively can be random.
6. the preparation method at the semiconductor power device back side of putting down in writing according to claim 1, it is characterized in that: described in the step (5) annealing heat treated annealing conditions be 300 ℃ to 450 ℃ of temperature ranges, annealed 30 minutes to 100 minutes, annealing heat treatment can be carried out after completing steps (3) and step (4); Also can carry out behind the completing steps (6) or in step (6) is carried out, finish.
7. the preparation method at the semiconductor power device back side of putting down in writing according to claim 1, it is characterized in that: in backplate described in the step (6), having the metal level that stacks gradually from described the second interarea side is aluminium lamination, titanium layer, nickel dam and silver layer; The metal level that stacks gradually also can be aluminium lamination, titanium layer, nickel dam and gold layer, or titanium layer, nickel dam and silver layer.
8. the preparation method at a semiconductor power device back side is characterized in that, may further comprise the steps:
(1) a kind of Semiconductor substrate 10 has the first interarea respect to one another (20) and the second interarea (30), forms the surface texture (200) of power device in the first interarea side of described Semiconductor substrate;
(2) grind second interarea of Semiconductor substrate of the surface texture formed power device to desired thickness;
(3) after Semiconductor substrate has just been finished the wear down operation, also do not inject any dopant before, just at the second interarea surface sputtering of Semiconductor substrate or deposit minimum layer of metal layer (104);
(4) the second interarea of finishing after back of the body surface sputtering or deposition layer of metal in Semiconductor substrate forms p-type district (102), the production process in p-type district comprises injection p-type doping ion to described second interarea of described Semiconductor substrate, and the implant angle scope is that 0 degree is to 7 degree;
(5) the second interarea of finishing after back of the body surface sputtering or deposition layer of metal in Semiconductor substrate forms N-shaped buffering area (101), the production process of N-shaped buffering area comprises Implanted n-Type doping ion to described second interarea of described Semiconductor substrate, and the implant angle scope is that 0 degree is to 7 degree;
(6) described p-type and N-shaped Implantation are activated by same annealing heat treatment behind the second interarea;
(7) form backplate (103) at described the second interarea, have the multiple layer metal floor and connect described p-type district (102).
9. the preparation method at the semiconductor power device back side of putting down in writing according to claim 8, it is characterized in that: described semiconductor power device can be IGBT or MCT or GTO.
10. the preparation method at the semiconductor power device back side of putting down in writing according to claim 8 is characterized in that: the injection parameter at the injection p-type doping ion described in the step (4) is that injector angle equals 7 degree, and the implantation dosage scope is 1 * 10
13/ cm
3To 1 * 10
16/ cm
3, inject the degree of depth less than 0.5um, injecting kind is the boron ion; Injection parameter at the Implanted n-Type doping ion described in the step (5) is that injector angle equals 0 degree, and the implantation dosage scope is 1 * 10
12/ cm
3To 5 * 10
15/ cm
3, inject the degree of depth greater than 0.5um, the injection kind is hydrogen ion, or the helium ion, or phosphonium ion, or sulphion; The injection order of described injection p-type foreign ion and described Implanted n-Type foreign ion successively can be random.
11. the preparation method at the semiconductor power device back side of putting down in writing according to claim 8, it is characterized in that: be in the hydrionic situation at the Implanted n-Type doping described in the step (5), additional helium ion or the nitrogen ion of injecting, inject the degree of depth less than 0.5um, the injector angle scope be 0 the degree to 7 the degree, the implantation dosage scope is 1 * 10
12/ cm
3To 5 * 10
14/ cm
3The injection order of the B Implanted ion described in described hydrogen injecting ion or injection helium ion or injecting nitrogen ion or the step (4) successively can be random.
12. the preparation method at the semiconductor power device back side of putting down in writing according to claim 8, it is characterized in that: at the Implanted n-Type foreign ion described in the step (5), minimum has two kinds of different injection parameters, and injection parameter includes the injection degree of depth, implantation dosage injects kind; The injection order of the N-shaped foreign ion of injection different parameters and step (4) injection p-type foreign ion successively can be random.
13. the preparation method at the semiconductor power device back side of putting down in writing according to claim 8, it is characterized in that: described in the step (6) annealing heat treated annealing conditions be 300 ℃ to 450 ℃ of temperature ranges, annealed 30 minutes to 100 minutes, annealing heat treatment can be carried out after complete step (4) and step (5); Also can carry out behind the completing steps (7) or in step (7) is carried out, finish.
14. the preparation method at the semiconductor power device back side of record according to claim 8 is characterized in that: described in the step (3) at the second interarea surface sputtering of Semiconductor substrate or deposit minimum layer of metal layer 104; Metal layer material can be aluminium, or aluminium alloy, or silver, or gold, or titanium, or titanium nitride, or tungsten, and thickness is 0.05um to 1.0um.
15. the preparation method at the semiconductor power device back side of putting down in writing according to claim 8, it is characterized in that: in backplate described in the step (7), having the metal level that stacks gradually from described the second interarea side is aluminium lamination, titanium layer, nickel dam and silver layer; The metal level that stacks gradually also can be aluminium lamination, titanium layer, nickel dam and gold layer, or titanium layer, nickel dam and silver layer.
16. the preparation method at a semiconductor power device back side is characterized in that, may further comprise the steps:
(1) a kind of Semiconductor substrate (10) has the first interarea respect to one another (20) and the second interarea (30), forms the surface texture of power device in the first interarea side of described Semiconductor substrate;
(2) grind second interarea of Semiconductor substrate of the surface texture formed power device to desired thickness;
(3) after Semiconductor substrate has just been finished the wear down operation, also do not inject any dopant before, just at the second interarea surface sputtering of Semiconductor substrate or deposit minimum layer of metal layer (104);
(4) afterwards in the second interarea formation N-shaped district of Semiconductor substrate, the production process in N-shaped district comprises Implanted n-Type doping ion to described second interarea of described Semiconductor substrate, and the implant angle scope is that 0 degree is to 7 degree;
(5) activate the N-shaped foreign ion that is injected into the second interarea with annealing heat treatment;
(6) form backplate at described the second interarea, have multiple layer metal and connect described N-shaped district.
17. the preparation method at the semiconductor power device back side of putting down in writing according to claim 16, it is characterized in that: described semiconductor power device can be fast-recovery commutation diode or power MOS pipe.
18. the preparation method at the semiconductor power device back side of record according to claim 16 is characterized in that: the injection parameter of the Implanted n-Type doping ion described in the step (4) be the implant angle scope be 0 degree to 7, the implantation dosage scope is 1 * 10
14/ cm
3To 1 * 10
16/ cm
3, the Implantation Energy scope is 200KeV to 2MeV, injecting kind can be arsenic ion, or phosphonium ion, or the helium ion, or hydrogen ion, or sulphion, or arsenic ion adds hydrogen ion.
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| CN108624844A (en) * | 2017-03-17 | 2018-10-09 | 株洲中车时代电气股份有限公司 | A kind of wafer rear metallic film and preparation method thereof |
| CN109659235A (en) * | 2018-12-14 | 2019-04-19 | 武汉华星光电半导体显示技术有限公司 | Preparation method, TFT, array substrate and the display device of TFT |
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