JP4123913B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4123913B2
JP4123913B2 JP2002340773A JP2002340773A JP4123913B2 JP 4123913 B2 JP4123913 B2 JP 4123913B2 JP 2002340773 A JP2002340773 A JP 2002340773A JP 2002340773 A JP2002340773 A JP 2002340773A JP 4123913 B2 JP4123913 B2 JP 4123913B2
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JP2003224281A (en
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達也 内藤
道生 根本
正人 大月
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Fuji Electric Co Ltd
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Fuji Electric Device Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Description

【０００１】
【発明の属する技術分野】
この発明は、電力用半導体整流素子（以下、単にダイオードという）などの半導体装置の製造方法に関する。
【０００２】
【従来の技術】
ダイオードはインバータをはじめ様々な電力変換装置の用途に利用されているが、近年ではインバータの高効率化のために高周波化が図られ１０ｋＨｚ以上のスイッチングスピードで開閉するＩＧＢＴ等のトランジスタのＦＷＤとしても使われるようになり、逆回復動作時間を短くすることが強く求められている。図６は、従来ダイオードであるｐｉｎダイオードの要部断面図である。ｎ+ カソード層１となる高濃度基板上にエピタキシャル成長でｎ層を形成し、このｎ層の表面層にｐアノード層３ａを形成する。ｎ+ カソード層１とｐアノード層３ａに挟まれたｎ層がｎドリフト層２となる。ｐアノード層３ａは、７×１０13ｃｍ-2のドーズ量で加速電圧１００ｋｅＶでイオン注入を１回行い、１１５０℃で９０分の高温アニ−ル（高温熱処理）を行い形成する。ｎ+ カソード層１上、ｐアノード層３ａ上にそれぞれカソード電極４、アノード電極５を形成する。
【０００３】
このｐｉｎダイオードは、耐圧の確保が容易であるが、正孔の注入効率を高めてオン電圧を低下させるために、ｐアノード層３ａを高濃度で形成する。そのため、逆回復特性においては、逆回復電流Ｉｒｒのピーク値Ｉｒｐが高くなり、ハードリカバリーとなる。また、ｐｉｎダイオードは、逆回復電流と逆回復電圧の積により、ダイオードに大きな電気的損失を生じる。この逆回復損失を小さくし、さらにスイッチング速度を高速化することが近年強く要求されている。現在、ダイオードの逆回復特性を改善するために、重金属拡散や電子線照射などを用いた少数キャリアのライフタイム制御が広く用いられている。すなわち、ライフタイムを小さくすることで、定常状態におけるキャリア濃度を減少させ逆回復中に空間電荷領域の広がりで掃き出されるキャリア濃度を減少させ、逆回復時間や逆回復電流および逆回復電荷を小さくして、逆回復損失を低減させることができる。
【０００４】
また、逆回復電流をソフトリカバリー化する手段としては、アノードからの少数キャリアの注入効率を抑制する構造がある。その代表的な構造としては、ショットキー接合とｐｎ接合を併設したＭＰＳ（Ｍｅｒｇｅｄ ｐｉｎ／Ｓｃｈｏｔｔｋｙ）ダイオードやｐアノード層の濃度を低くし、厚みを薄くしたＳＦＤ（Ｓｏｆｔ ａｎｄ Ｆａｓｔ Ｒｅｃｏｖｅｒｙ Ｄｉｏｄｅ）などが挙げられる。
【０００５】
【特許文献１】
米国特許第４６４１１７４号明細書
【特許文献２】
特許第３１４９４８３号（図１）
【特許文献３】
特開平７−２２６５２１号公報（図３）
【特許文献４】
特開平９−３２１３２０号公報（図１）
【特許文献５】
特開平１０−２００１３２号公報（図１）
【特許文献６】
特開平１０−３２１８７６号公報（図１）
【０００６】
【発明が解決しようとする課題】
しかし、図６のｐｉｎダイオードや前記のＭＰＳダイオードにおいて、さらに逆回復電流Ｉｒｒと逆回復損失を共に小さくし、一層のソフトリカバリー化を図ることが求められている。また、特許文献２〜６のダイオードでは、高濃度の浅いアノード層と低濃度で深いアノード層が記載されているが、これらは高濃度のアノード層を高温の熱処理で形成しているため、活性化率がほぼ１００％の高注入であり、逆回復特性が好ましくない。この発明の目的は、前記の課題を解決して、従来ダイオードと比べて、逆回復電流の低減、逆回復損失の低減および一層のソフトリカバリー化を図ることができる半導体装置とその製造方法を提供することにある。
【０００７】
【課題を解決するための手段】
前記の目的を達成するために、第１導電型の半導体基板と、該半導体基板の一方の表面層に形成した第２導電型の低濃度の第１アノード層と、該第１アノード層の表面層に形成した第２導電型の高濃度の第２アノード層と、該第２アノード層表面に形成したアノード電極と、他方の表面に形成した第１導電型のカソード層と、該カソード層表面に形成したカソード電極とを具備する半導体装置の製造方法において、前記第１アノード層が、第２アノード層のドーズ量より低いドーズ量をイオン注入し、高温熱処理して２μｍ以上の拡散深さに形成し、その後、第２アノード層を３×１０ 12 ｃｍ -2 以上３×１０ 13 ｃｍ -2 以下のドーズ量をイオン注入し、３５０℃以上６００℃以下の低温アニール又はレーザアニールの低温熱処理して１μｍ以下の深さに形成する。また、前記第１アノード層と第２アノード層の少なくとも一方を複数個互いに離して形成する。
【０００８】
【０００９】
また、第１導電型の半導体基板と、該半導体基板の一方の表面層に複数個互いに離して形成した第２導電型の低濃度の第１アノード層と、該第１アノード層のそれぞれの表面層に形成した第２導電型の高濃度の第２アノード層と、前記第２アノード層と半導体基板の各表面に形成したアノード電極と、他方の表面に形成した第１導電型のカソード層と、該カソード層表面に形成したカソード電極とを具備する半導体装置の製造方法において、前記第１アノード層が、第２アノード層のドーズ量より低いドーズ量をイオン注入し、高温熱処理して２μｍ以上の拡散深さで複数の第１アノード層が互いに半導体基板表面で重なり合う領域を有するように形成し、その後、第２アノード層を３×１０12ｃｍ-2以上３×１０13ｃｍ-2以下のドーズ量をイオン注入し、３５０℃以上６００℃以下の低温アニール又はレーザアニールの低温熱処理して１μｍ以下の深さに形成する。
【００１０】
【００１１】
【発明の実施の形態】
以下の説明で、第１導電型をｎ型、第２導電型をｐ型とする。勿論、逆であっても構わない。また、図６と同一箇所には同一の符号を記した。図１は、この発明の一実施例のｐｉｎダイオードの要部断面図である。ｎ+ カソード層１となる高濃度基板上にエピタキシャル成長でｎ層を形成し、このｎ層の表面層にｐアノード層３を形成する。ｎ+ カソード層１とｐアノード層３に挟まれたｎ層がｎドリフト層２となる。ｐアノード層３は、１×１０12ｃｍ-2程度の極めて低いドーズ量で、加速電圧１００ｋｅＶでイオン注入を行い、高温アニールして形成し、さらに、ＰＳＧ（リンガラス）膜を９００℃程度の熱処理温度で被覆した後、コンタクト部分とする箇所のＰＳＧ膜をエッチングで除去し、３×１０13ｃｍ-2のドーズ量で、加速電圧４５ｋｅＶでイオン注入を行い４００℃の低温アニールを行うことで１μｍ以下の高濃度のｐアノード層３ｃ（この高濃度のｐアノード層３ｃはコンタクト層を兼ねる）を形成する。また、低濃度のアノード層３ｂと高濃度のアノード層３ｃを合わせたｐアノード層３の拡散深さ（低濃度ｐアノード層３ｂの深さと一致する）は、ｐアノード層３内の空乏層がアノード電極５に到達しないように、２μｍ以上とする。
【００１２】
この低いドーズ量で、１００ｋｅＶの高い加速電圧でイオン注入された低濃度のｐアノード層３ｂは、高温アニールとＰＳＧ膜処理温度により、打ち込まれた不純物原子は殆ど活性化し、また、イオン注入で導入された欠陥はほとんど消滅する。一方、高いドーズ量で、４５ｋｅＶの低い加速電圧でイオン注入された高濃度のｐアノード層３ｃでは、４００℃の低温アニールのために、イオン注入で導入された欠陥は多数残留する。この欠陥で、高濃度のｐアノード層３ｃのライフタイムは低下する。また、低温アニールの温度は６００℃を超えるとイオン注入で導入された欠陥の消滅割合が多く、また３５０℃未満ではイオン注入された不純物原子の活性化率がよくない。そのため、低温アニールの温度が３５０℃以上６００℃以下が好ましい。また、低温アニールをレーザアニールで行うことで打ち込まれた不純物原子の活性化率を向上させることができて、正孔の注入効率が低下し過ぎるのを抑制できる。
【００１３】
低濃度のｐアノード層３ｂと高濃度のｐアノード層３ｃのライフタイムの低下により、ｐアノード層３からｎドリフト層２への正孔の注入が抑制される。その結果、逆回復電流と逆回復損失は低下し、ｎ+ カソード層１付近のキャリア濃度がｐアノード層３付近のキャリア濃度より高くなり、一層のソフトリカバリー化を図ることができる。また、低濃度のｐアノード層３ｂの拡散深さを２μｍ以上とすることで、定格電圧で空乏層がアノード電極５へ到達すること防止することができる。図２は、拡散プロフィルとライフタイム分布の関係を示す図であり、同図（ａ）は拡散プロフィルを示す図であり、図中の３ａは従来品のプロフィル、３は本発明品のｐアノード層全体のプロフィルで、３ｂは本発明品の低濃度部分、３ｃは高濃度部分のプロフィルであり、同図（ｂ）は従来品のライフタイム分布を示す図、同図（ｃ）は本発明品のライフタイム分布を示す図である。同図（ｂ）は従来品ダイオードのライフタイム分布を推定したものであるが、拡散プロフィル的に本発明品と類似している特許第３１４９４８３号公報に開示されているダイオードのライフタイムもこれと同じと推定される。従来品は、高温アニールしているために、ｐアノード層３ａのライフタイムは比較的大きい値となる。この従来品と比べると、本発明品は低温アニールしているために、ｐアノード層３ｂのライフタイムの値は小さくなる。
【００１４】
図３は、従来型のｐｉｎダイオードと本発明のｐｉｎダイオードの逆回復波形図である。本発明のｐｉｎダイオード（発明品）は、従来型のｐｉｎダイオード（従来品）に比べて、ｐアノード層３の濃度が極めて低いために、逆回復電流Ｉｒｒのピーク値Ｉｒｐは大幅に低減する。さらに、正孔の注入が低いため、順電流を通電した状態で、カソード側にキャリアが多い分布となり、ソフトリカバリーな波形となる。本発明を用いることで、従来、ソフトリカバリー化が困難とされる数十μｍの薄いドリフト層を有する６００Ｖ程度の高耐圧のダイオードをソフトリカバリー化することができる。つまり、数十μｍと薄いドリフト層を有する６００Ｖ程度以上の高耐圧のＭＰＳダイオードを逆回復過程で、電圧・電流波形が発振せず、また損失の少ないダイオードとすることができる。
【００１５】
尚、この発明を、特願２０００−３１１４４２号に記載されたダイオードやＭＰＳダイオードのｐアノード領域に適用することで、図１の構成の場合と同様の効果が得られる。
図４は、特願２０００−３１１４４２号に記載されたダイオードに本発明を適用した構成を示す要部断面図である。図１と異なる点は、ｐアノード層３が重なり箇所を有するように低濃度のｐアノード層３ｂを形成し、その低濃度のｐアノード層３ｂの表面全体に高濃度のｐアノード層３ｃを形成している点である。ｐアノード層３ｂは、複数の拡散層が互いに半導体基板表面で重なり合う重なり箇所を有し、該重なり箇所の最高濃度が、ｎドリフト層２の濃度の１倍以上１０倍以下となっている。図５は、ＭＰＳダイオードに本発明を適用した構成を示す要部断面図である。図５では、分散して形成した低濃度のｐアノード層３ｂの表面に高濃度のｐアノード層３ｃを形成している。
【００１６】
図７は、高濃度のｐアノード層３ｃのボロンのドーズ量を変えた場合の漏れ電流と逆回復ピーク電流（Ｉｒｐ）の関係を示した特性図である。図７において、ボロンのドーズ量が３×１０12ｃｍ-2以下であると漏れ電流が急激に増加している。これは、ドーズ量が少ないと空乏層が半導体基板表面にまで拡がりパンチスルーするためである。また、逆回復ピーク電流はボロンのドーズ量が３×１０13ｃｍ-2以上になると急激に増加している。この逆回復ピーク電流の増加はホールの注入が増えることによる。よって、高濃度のｐアノード層３ｃのドーズ量は、３×１０12ｃｍ-2以上３×１０13ｃｍ-2以下であることが望ましい。
【００１７】
図８は、熱処理温度を変えた場合の深さ方向の不純物分布を示した図である。図８において、ｐアノード層３をボロンのドーズ量を７×１０13ｃｍ-2として熱処理温度を１１５０℃の高温熱処理（従来技術に相当）と４００℃の低温熱処理（本発明）とした場合の深さ方向の不純物の拡散の分布を比較した。高温熱処理では、拡散深さが３．５μｍとなり、実効的なドーズ量は５．０×１０13ｃｍ-2となり活性化率がほぼ１００％である。これに対して、本発明の低温熱処理では、拡散深さが０．６μｍとなり、実効的なドーズ量は５．２×１０12ｃｍ-2となり活性化率が１０％以下である。低温熱処理を行うことで不純物の実効的なドーズ量を下げることができる。
【００１８】
図９は、本発明での漏れ電流の熱処理温度依存性と不純物活性化率の熱処理温度依存性を示した図である。６００℃以下で熱処理を施すと不純物活性化率は１０％程度となり、８００℃以上の熱処理を施すと不純物活性化率は１００％程度となる。これに対して逆漏れ電流は温度に依存せず、ほぼ一定である。なお、ＭＰＳ構造のようにｐｎ接合の他にショットキー接合が混在する場合は、漏れ電流が増加する。本発明では、このＭＰＳ構造よりも漏れ電流を減少させることができる。図１０は、逆回復ピーク電流の熱処理温度依存性を示した図である。図１０において、ＳＳＤダイオードでは逆回復ピーク電流が４６Ａであり、ＭＰＳダイオードでは逆回復ピーク電流が２５Ａである。本発明において、熱処理温度を６００℃以下とすることでＭＰＳダイオード並の逆回復ピーク電流値とすることができる。よって、第２アノード層の熱処理温度は３００℃以上６００℃以下であることが望ましい。
【００１９】
図１１は、異なる実施例の要部断面図である。図１１において、その低濃度のｐアノード層３ｂの形成された活性領域の表面全体に高濃度のｐアノード層３ｃを形成している。このように活性領域の表面全体に高濃度のｐアノード層３ｃを形成することで、図５のショットキ接合部を有する構造に比してショットキ接合部が存在しないので、漏れ電流を大幅に減少させることができる。これにより基板表面に電極を形成後にボンディングワイヤのワイヤをボンディングした場合の漏れ電流の不良を低減することができる。図１２は、拡散プロフィルとライフタイム分布の関係を示す図であり、同図（ａ）は拡散プロフィルを示す図であり、図中の３ｂは本発明品の低濃度部分、３ｃは高濃度部分のプロフィルであり、同図（ｂ）は従来品と本発明品のライフタイム分布を示す図である。従来品は、高温アニールしているために、ｐアノード層３ａのライフタイムは比較的大きい値となる。この従来品と比べると、本発明品は低温アニールしているために、ｐアノード層３ｂのライフタイムの値は小さくなる。同図（ｃ）は本発明のダイオードにライフタイムキラーとして白金拡散（Ｐｔ）と電子線照射（ＥＩ）を用いた場合のライフタイム分布を示した。ＥＩの場合は一様なライフタイム分布となる。Ｐｔの場合は欠陥がアノード側に偏析するためにアノード側のライフタイムが短くなる。
【００２０】
図１３、１４は異なる実施例の不純物分布を示す図である。図１３の（ａ）は、カソード電極とｎカソード層の間に高濃度層（ｎ＋層）をＡｓのイオン注入で形成したものである。まず、半導体基板表面にｐアノード層を形成後に半導体基板の裏面を削り、裏面からＡｓ（砒素）をドーズ量２×１０14ｃｍ-2加速電圧１００ｋｅＶでイオン注入し、その後熱処理を１１００℃で行うことで１μｍ程度の高濃度ｎ+層を形成する。更に、カソード電極にＴｉを用いて、この高濃度ｎ+層とオーミック接触をするように蒸着にて形成する。この裏面から行うイオン注入はＰ（リン）でも良いが、Ａｓの方がＰと比べて拡散係数が小さく熱拡散が浅くできるため表面濃度を高くすることができるので望ましい。またイオン注入後の拡散温度は１１００℃で行うと、拡散係数などの関係からＡｓの拡散深さは１μｍ以上とはならない。この実施例では低Ｖｆ（順電圧）にすることができる。図１３の（ｂ）は、ｎ-ドリフト層を２段で形成した構造である。この構造により逆回復中での電界の拡がりを抑制しカソード側にキャリアを多く残すことで発振現象を抑制することができる。図１３の（ｃ）は、ｎ-層にｎ+層を拡散した構造である。ｎ-層からｎ+層にかけて徐々に不純物濃度が増加する分布とすることで逆回復電荷（Ｑｒｒ）が増加するが、ソフトリカバリには効果的である。図１３の（ｄ）は、ｎ-層からｎ+層にかけて少しずつ不純物濃度が増加していて、その増加分を２回に分けて行っている２段勾配構造である。この構造では、（ｃ）の構造よりも損失を少なくすることができ、かつソフトリカバリ化にも効果的である。図１４の（ａ）は、バルクウエハを用いてアノード側からカソード側にかけて徐々に不純物濃度が増加していて、かつ半導体基板裏面からイオン注入で数μｍのｎ+層を形成した構造である。この構造はｎ＋層からの電子の注入を抑制し、かつ電界の拡がりを徐々に抑制するため、ソフトリカバリで低損失な特性が得られる。図１４の（ｂ）は、ｎ-層中にｎ-層よりも高濃度なｎ層（バッファ層）を数μｍ程度の厚さ形成した構造である。この構造では逆回復中の電界の拡がりをこのバッファ層で抑制し、カソード側により多くのキャリアを残すことで発振現象を抑制することができる。図１４の（ｃ）は、ｎ-層の中心に向かって不純物濃度が徐々に増加していく構造である。図１４の（ｂ）の構造と同じく電界の拡がりを抑制することができるが、更に電界変化をなだらかにすることができるためにｄｖ／ｄｔを小さくすることができる。
【００２１】
図１５は本発明の活性領域を上からみた要部平面図である。（ａ）は高濃度で低温熱処理のｐ+アノード層３ｃを活性領域の全面に形成し、低濃度で高温熱処理のｐアノード層３ｂをセル状に形成した構造である。（ｂ）は高濃度で低温熱処理のｐ+アノード層３ｃをセル状に形成し、低濃度で高温熱処理のｐアノード層３ｂを活性領域の全面に形成した構造である。（ｃ）と（ｄ）は、ストライプ状に形成した構造である。（ｅ）は高濃度で低温熱処理のｐ+アノード層３ｃを活性領域の全面に形成し、低濃度で高温熱処理のｐアノード層３ｂをセル状に形成し更にｐアノード層３ｂ内にｐ+アノード層３ｃを形成したリングセル構造である。（ｆ）は（ｅ）と各層が逆転した構造である。
【００２２】
図１６は、本発明のエッジ構造を示す要部断面図である。（ａ）において、図の点線の紙面右側が活性領域、左側がエッジ部である。これは、一般的なエッジ構造であり、ガードリング６と、ストッパ領域７、ストッパ電極８、フィールドプレート９、フィールド酸化膜１０を備えている。（ｂ）は、活性領域とエッジ部の間のフィールド酸化膜を（ａ）よりも長くし、逆回復時にエッジ部の下にキャリアを入れにくくし、逆回復耐量を高めた構造である。図１７は、本発明のエッジ構造を示す斜視断面図である。
【００２３】
【発明の効果】
この発明において、ｐアノード層を、低ドーズ量のイオン注入し、高温熱処理して形成した第１アノード層と、高ドーズ量のイオン注入し、３５０℃以上６００℃以下の低温アニール又はレーザアニールの低温熱処理して１μｍ以下の深さに形成した第２アノード層で構成することで、従来品より、逆回復電流と逆回復損失の低減を図り、一層のソフトリカバリー化を図ることができる。その結果、高速・低損失化とソフトリカバリー化の間のトレードオフを改善することができる。また、ｐアノード層の拡散深さを２μｍ以上とすることで、所定の耐圧を確保することができ、活性領域の全面に形成した場合はショットキー接合による漏れ電流の増加を防ぐことができる。
【図面の簡単な説明】
【図１】 この発明の一実施例のｐｉｎダイオードの要部断面図
【図２】 従来のｐｉｎダイオードと本発明のｐｉｎダイオードのｐアノード層のライフタイムを比較した図
【図３】 従来型のｐｉｎダイオードと本発明のｐｉｎダイオードの逆回復波形図
【図４】 特願２０００−３１１４４２号に記載されたダイオードに本発明を適用した構成を示す要部断面図
【図５】 ＭＰＳダイオードに本発明を適用した構成を示す要部断面図
【図６】 従来ダイオードであるｐｉｎダイオードの要部断面図
【図７】 本発明の実施例である高濃度のｐアノード層のドーズ量を変えた場合の漏れ電流と逆回復ピーク電流の関係を示した特性図
【図８】 熱処理温度を変えた場合の深さ方向の不純物分布を示した図
【図９】 本発明での漏れ電流の熱処理温度依存性と不純物活性化率の熱処理温度依存性を示した図
【図１０】 逆回復ピーク電流の熱処理温度依存性を示した図
【図１１】 異なる実施例の要部断面図
【図１２】 従来のｐｉｎダイオードと本発明のｐｉｎダイオードのｐアノード層のライフタイムを比較した図
【図１３】 異なる実施例の不純物分布を示した図
【図１４】 異なる実施例の不純物分布を示した図
【図１５】 本発明の活性領域を上からみた要部平面図
【図１６】 本発明のエッジ構造を示す要部断面図
【図１７】 本発明のエッジ構造を示す斜視断面図
【符号の説明】
１ ｎ+ カソード層
２ ｎドリフト層
３ ｐアノード層（本発明品）
３ａ ｐアノード層（従来品）
３ｂ 低濃度のｐアノード層（本発明品）
３ｃ 高濃度のｐアノード層（本発明品）
４ カソード電極
５ アノード電極[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device such as a power semiconductor rectifier (hereinafter simply referred to as a diode).
[0002]
[Prior art]
Diodes are used for various power converter applications including inverters, but in recent years, they have been used as FWDs for transistors such as IGBTs that open and close at a switching speed of 10 kHz or higher in order to increase the efficiency of inverters. There is a strong demand to shorten the reverse recovery operation time. FIG. 6 is a cross-sectional view of a main part of a pin diode which is a conventional diode. An n layer is formed by epitaxial growth on a high-concentration substrate to be the n + cathode layer 1, and a p anode layer 3a is formed on the surface layer of the n layer. The n layer sandwiched between the n + cathode layer 1 and the p anode layer 3 a becomes the n drift layer 2. The p anode layer 3a is formed by performing ion implantation once at an acceleration voltage of 100 keV at a dose of 7 × 10 13 cm −2 and high temperature annealing (high temperature heat treatment) at 1150 ° C. for 90 minutes. A cathode electrode 4 and an anode electrode 5 are formed on the n + cathode layer 1 and the p anode layer 3a, respectively.
[0003]
This pin diode is easy to secure a withstand voltage, but the p anode layer 3a is formed at a high concentration in order to increase the hole injection efficiency and lower the on-voltage. Therefore, in the reverse recovery characteristic, the peak value Irp of the reverse recovery current Irr becomes high, and hard recovery is performed. In addition, the pin diode causes a large electrical loss in the diode due to the product of the reverse recovery current and the reverse recovery voltage. In recent years, there has been a strong demand for reducing the reverse recovery loss and further increasing the switching speed. Currently, in order to improve the reverse recovery characteristics of a diode, lifetime control of minority carriers using heavy metal diffusion or electron beam irradiation is widely used. That is, by reducing the lifetime, the carrier concentration in the steady state is reduced, the carrier concentration that is swept away by the expansion of the space charge region during reverse recovery is reduced, and the reverse recovery time, reverse recovery current, and reverse recovery charge are reduced. Thus, reverse recovery loss can be reduced.
[0004]
Further, as a means for soft recovery of the reverse recovery current, there is a structure that suppresses the injection efficiency of minority carriers from the anode. Typical examples of the structure include an MPS (Merged pin / Schottky) diode having a Schottky junction and a pn junction, and an SFD (Soft and Fast Recovery Diode) in which the concentration of the p anode layer is reduced and the thickness is reduced. It is done.
[0005]
[Patent Document 1]
US Pat. No. 4,641,174 [Patent Document 2]
Japanese Patent No. 3149483 (FIG. 1)
[Patent Document 3]
Japanese Patent Laid-Open No. 7-226521 (FIG. 3)
[Patent Document 4]
JP-A-9-321320 (FIG. 1)
[Patent Document 5]
JP-A-10-200132 (FIG. 1)
[Patent Document 6]
Japanese Patent Laid-Open No. 10-321876 (FIG. 1)
[0006]
[Problems to be solved by the invention]
However, in the pin diode of FIG. 6 and the MPS diode described above, it is required to further reduce the reverse recovery current Irr and the reverse recovery loss to achieve further soft recovery. Further, in the diodes of Patent Documents 2 to 6, a high-concentration shallow anode layer and a low-concentration deep anode layer are described. However, since these high-concentration anode layers are formed by high-temperature heat treatment, they are active. The conversion rate is almost 100% and the reverse recovery characteristic is not preferable. An object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can solve the above-described problems and can achieve a reduction in reverse recovery current, a reduction in reverse recovery loss, and further soft recovery as compared with a conventional diode. There is to do.
[0007]
[Means for Solving the Problems]
To achieve the above object, a first conductivity type semiconductor substrate, a second conductivity type low concentration first anode layer formed on one surface layer of the semiconductor substrate, and a surface of the first anode layer A second conductivity type high concentration second anode layer formed on the layer, an anode electrode formed on the surface of the second anode layer, a first conductivity type cathode layer formed on the other surface, and the surface of the cathode layer In the method of manufacturing a semiconductor device comprising the cathode electrode formed on the first anode layer, the first anode layer is ion-implanted with a dose amount lower than the dose amount of the second anode layer, and is subjected to a high temperature heat treatment to a diffusion depth of 2 μm or more. After that, the second anode layer is ion-implanted with a dose amount of 3 × 10 12 cm −2 or more and 3 × 10 13 cm −2 or less and subjected to low temperature annealing of 350 ° C. or more and 600 ° C. or less or low temperature heat treatment of laser annealing. Less than 1μm Form to depth. In addition, at least one of the first anode layer and the second anode layer is formed apart from each other.
[0008]
[0009]
A first conductivity type semiconductor substrate; a plurality of second conductivity type low-concentration first anode layers formed on one surface layer of the semiconductor substrate; and a surface of each of the first anode layers. A second conductivity type high-concentration second anode layer formed on the layer; an anode electrode formed on each surface of the second anode layer and the semiconductor substrate; a first conductivity type cathode layer formed on the other surface; In the method of manufacturing a semiconductor device comprising a cathode electrode formed on the surface of the cathode layer, the first anode layer is ion-implanted with a dose amount lower than the dose amount of the second anode layer, and is subjected to high-temperature heat treatment for 2 μm or more. A plurality of first anode layers are formed so as to have a region where they overlap each other on the surface of the semiconductor substrate with a diffusion depth of 3 × 10 12 cm −2 or more and 3 × 10 13 cm −2 or less. Dose amount ON injection, 350 ° C. or higher 600 ° C. with low-temperature heat treatment of the following low-temperature annealing or laser annealing to form below a depth of 1 [mu] m.
[0010]
[0011]
DETAILED DESCRIPTION OF THE INVENTION
In the following description, the first conductivity type is n-type and the second conductivity type is p-type. Of course, the reverse is also possible. Moreover, the same code | symbol was described in the same location as FIG. FIG. 1 is a cross-sectional view of an essential part of a pin diode according to an embodiment of the present invention. An n layer is formed by epitaxial growth on a high-concentration substrate to be the n + cathode layer 1, and a p anode layer 3 is formed on the surface layer of the n layer. The n layer sandwiched between the n + cathode layer 1 and the p anode layer 3 becomes the n drift layer 2. The p anode layer 3 is formed by ion implantation at an acceleration voltage of 100 keV at a very low dose of about 1 × 10 12 cm −2 and annealing at a high temperature. Further, a PSG (phosphorus glass) film is formed at about 900 ° C. After coating at the heat treatment temperature, the PSG film at the contact portion is removed by etching, ion implantation is performed at an acceleration voltage of 45 keV at a dose of 3 × 10 13 cm −2 , and low temperature annealing at 400 ° C. is performed. A high concentration p anode layer 3c of 1 μm or less (this high concentration p anode layer 3c also serves as a contact layer) is formed. Further, the diffusion depth of the p anode layer 3 (which matches the depth of the low concentration p anode layer 3b), which is a combination of the low concentration anode layer 3b and the high concentration anode layer 3c, is determined by the depletion layer in the p anode layer 3 The thickness is set to 2 μm or more so as not to reach the anode electrode 5.
[0012]
The low-concentration p anode layer 3b ion-implanted at a high acceleration voltage of 100 keV with this low dose is almost activated by the high-temperature annealing and PSG film processing temperature, and is introduced by ion implantation. Most of the defects made disappear. On the other hand, in the high-concentration p anode layer 3c ion-implanted with a high dose and a low acceleration voltage of 45 keV, a large number of defects introduced by ion implantation remain due to low-temperature annealing at 400 ° C. Due to this defect, the lifetime of the high-concentration p anode layer 3c is lowered. If the temperature of the low-temperature annealing exceeds 600 ° C., the rate of disappearance of defects introduced by ion implantation is large, and if it is lower than 350 ° C., the activation rate of the ion-implanted impurity atoms is not good. Therefore, the temperature of the low temperature annealing is preferably 350 ° C. or higher and 600 ° C. or lower. Further, the activation rate of the implanted impurity atoms can be improved by performing the low-temperature annealing by laser annealing, and it is possible to suppress the hole injection efficiency from being excessively lowered.
[0013]
By reducing the lifetimes of the low-concentration p anode layer 3b and the high-concentration p anode layer 3c, injection of holes from the p anode layer 3 to the n drift layer 2 is suppressed. As a result, the reverse recovery current and reverse recovery loss are reduced, the carrier concentration in the vicinity of the n + cathode layer 1 becomes higher than the carrier concentration in the vicinity of the p anode layer 3, and further soft recovery can be achieved. Further, by setting the diffusion depth of the low-concentration p anode layer 3b to 2 μm or more, it is possible to prevent the depletion layer from reaching the anode electrode 5 at the rated voltage. FIG. 2 is a diagram showing the relationship between the diffusion profile and the lifetime distribution. FIG. 2A is a diagram showing the diffusion profile, in which 3a is the profile of the conventional product and 3 is the p anode of the product of the present invention. 3b is the low concentration part of the product of the present invention, 3c is the profile of the high concentration part, FIG. 5B is a diagram showing the lifetime distribution of the conventional product, and FIG. It is a figure which shows lifetime distribution of goods. FIG. 4B is an estimation of the lifetime distribution of the conventional diode, but the lifetime of the diode disclosed in Japanese Patent No. 3149483, which is similar to the product of the present invention in terms of diffusion profile, is also the same. Presumed to be the same. Since the conventional product is annealed at a high temperature, the lifetime of the p anode layer 3a has a relatively large value. Compared with this conventional product, the product of the present invention is annealed at a low temperature, so the lifetime value of the p anode layer 3b is small.
[0014]
FIG. 3 is a reverse recovery waveform diagram of the conventional pin diode and the pin diode of the present invention. Since the concentration of the p anode layer 3 is extremely low in the pin diode of the present invention (invention product) compared to the conventional pin diode (conventional product), the peak value Irp of the reverse recovery current Irr is significantly reduced. Furthermore, since the injection of holes is low, a distribution with a large amount of carriers on the cathode side in a state where a forward current is applied, and a soft recovery waveform is obtained. By using the present invention, it is possible to soft-recover a diode having a high breakdown voltage of about 600 V having a thin drift layer of several tens of μm, which is conventionally difficult to achieve soft recovery. In other words, an MPS diode having a high breakdown voltage of about 600 V or more having a drift layer as thin as several tens of μm can be made into a diode that does not oscillate in voltage / current waveform and has little loss during reverse recovery.
[0015]
By applying the present invention to the p-anode region of the diode or MPS diode described in Japanese Patent Application No. 2000-311442, the same effect as in the configuration of FIG. 1 can be obtained.
FIG. 4 is a cross-sectional view of an essential part showing a configuration in which the present invention is applied to a diode described in Japanese Patent Application No. 2000-311442. The difference from FIG. 1 is that a low-concentration p-anode layer 3b is formed so that the p-anode layer 3 has an overlapping portion, and a high-concentration p-anode layer 3c is formed on the entire surface of the low-concentration p-anode layer 3b. This is the point. The p anode layer 3 b has an overlapping portion where a plurality of diffusion layers overlap each other on the surface of the semiconductor substrate, and the maximum concentration of the overlapping portion is 1 to 10 times the concentration of the n drift layer 2. FIG. 5 is a cross-sectional view of a principal part showing a configuration in which the present invention is applied to an MPS diode. In FIG. 5, a high concentration p anode layer 3c is formed on the surface of a low concentration p anode layer 3b formed in a dispersed manner.
[0016]
FIG. 7 is a characteristic diagram showing the relationship between leakage current and reverse recovery peak current (Irp) when the boron dose of the high-concentration p anode layer 3c is changed. In FIG. 7, when the boron dose is 3 × 10 12 cm −2 or less, the leakage current increases rapidly. This is because when the dose is small, the depletion layer extends to the surface of the semiconductor substrate and punches through. The reverse recovery peak current increases rapidly when the boron dose is 3 × 10 13 cm −2 or more. This increase in reverse recovery peak current is due to an increase in hole injection. Therefore, the dose amount of the high-concentration p anode layer 3c is desirably 3 × 10 12 cm −2 or more and 3 × 10 13 cm −2 or less.
[0017]
FIG. 8 is a diagram showing the impurity distribution in the depth direction when the heat treatment temperature is changed. In FIG. 8, when the p anode layer 3 is boron dose of 7 × 10 13 cm −2 , the heat treatment temperature is 1150 ° C. high temperature heat treatment (corresponding to the prior art) and 400 ° C. low temperature heat treatment (present invention). The diffusion distribution of impurities in the depth direction was compared. In the high-temperature heat treatment, the diffusion depth is 3.5 μm, the effective dose is 5.0 × 10 13 cm −2 , and the activation rate is almost 100%. In contrast, in the low temperature heat treatment of the present invention, the diffusion depth is 0.6 μm, the effective dose is 5.2 × 10 12 cm −2 , and the activation rate is 10% or less. By performing low-temperature heat treatment, the effective dose of impurities can be reduced.
[0018]
FIG. 9 is a diagram showing the heat treatment temperature dependence of leakage current and the heat treatment temperature dependence of impurity activation rate in the present invention. When heat treatment is performed at 600 ° C. or lower, the impurity activation rate is about 10%, and when heat treatment is performed at 800 ° C. or higher, the impurity activation rate is about 100%. On the other hand, the reverse leakage current does not depend on the temperature and is almost constant. In addition, when the Schottky junction is mixed in addition to the pn junction as in the MPS structure, the leakage current increases. In the present invention, the leakage current can be reduced as compared with the MPS structure. FIG. 10 is a graph showing the heat treatment temperature dependence of the reverse recovery peak current. In FIG. 10, the reverse recovery peak current is 46 A for the SSD diode, and the reverse recovery peak current is 25 A for the MPS diode. In the present invention, by setting the heat treatment temperature to 600 ° C. or less, it is possible to obtain a reverse recovery peak current value comparable to that of an MPS diode. Therefore, the heat treatment temperature of the second anode layer is desirably 300 ° C. or higher and 600 ° C. or lower.
[0019]
FIG. 11 is a cross-sectional view of a main part of a different embodiment. In FIG. 11, a high concentration p anode layer 3c is formed on the entire surface of the active region where the low concentration p anode layer 3b is formed. By forming the high-concentration p anode layer 3c on the entire surface of the active region in this way, the Schottky junction does not exist as compared with the structure having the Schottky junction shown in FIG. be able to. As a result, it is possible to reduce leakage current defects when bonding wires of bonding wires after electrodes are formed on the substrate surface. FIG. 12 is a diagram showing the relationship between the diffusion profile and the lifetime distribution. FIG. 12A is a diagram showing the diffusion profile, in which 3b is a low concentration portion of the product of the present invention, and 3c is a high concentration portion. FIG. 5B is a diagram showing the lifetime distribution of the conventional product and the product of the present invention. Since the conventional product is annealed at a high temperature, the lifetime of the p anode layer 3a has a relatively large value. Compared with this conventional product, the product of the present invention is annealed at a low temperature, so the lifetime value of the p anode layer 3b is small. FIG. 4C shows the lifetime distribution when platinum diffusion (Pt) and electron beam irradiation (EI) are used as the lifetime killer in the diode of the present invention. In the case of EI, the lifetime distribution is uniform. In the case of Pt, since the defects are segregated to the anode side, the lifetime on the anode side is shortened.
[0020]
13 and 14 are diagrams showing impurity distributions of different examples. FIG. 13A shows a high concentration layer (n + layer) formed by As ion implantation between a cathode electrode and an n cathode layer. First, after forming a p-anode layer on the surface of the semiconductor substrate, the back surface of the semiconductor substrate is shaved, and As (arsenic) is ion-implanted from the back surface with a dose amount of 2 × 10 14 cm −2 acceleration voltage 100 keV, and then heat treatment is performed at 1100 ° C. Thus, a high concentration n + layer of about 1 μm is formed. Further, Ti is used for the cathode electrode and is formed by vapor deposition so as to be in ohmic contact with the high concentration n + layer. The ion implantation performed from the back surface may be P (phosphorus), but As is preferable because P has a smaller diffusion coefficient and shallower thermal diffusion, so that the surface concentration can be increased. If the diffusion temperature after ion implantation is 1100 ° C., the diffusion depth of As will not be 1 μm or more because of the diffusion coefficient. In this embodiment, a low Vf (forward voltage) can be achieved. FIG. 13B shows a structure in which the n − drift layer is formed in two stages. With this structure, it is possible to suppress the oscillation phenomenon by suppressing the expansion of the electric field during reverse recovery and leaving many carriers on the cathode side. FIG. 13C shows a structure in which the n + layer is diffused in the n − layer. Although the reverse recovery charge (Qrr) increases by making the impurity concentration gradually increase from the n − layer to the n + layer, it is effective for soft recovery. FIG. 13D shows a two-stage gradient structure in which the impurity concentration increases little by little from the n − layer to the n + layer, and the increase is divided into two. With this structure, the loss can be reduced as compared with the structure of (c), and it is effective for soft recovery. FIG. 14A shows a structure in which an impurity concentration is gradually increased from the anode side to the cathode side using a bulk wafer, and an n + layer of several μm is formed by ion implantation from the back surface of the semiconductor substrate. Since this structure suppresses the injection of electrons from the n + layer and gradually suppresses the expansion of the electric field, a low loss characteristic can be obtained by soft recovery. (B) in FIG. 14, n - n in the layer - which is a high concentration n-layer structure formed of several μm (the buffer layer) thickness than the layers. In this structure, the expansion of the electric field during reverse recovery is suppressed by this buffer layer, and the oscillation phenomenon can be suppressed by leaving more carriers on the cathode side. FIG. 14C shows a structure in which the impurity concentration gradually increases toward the center of the n − layer. Although the expansion of the electric field can be suppressed as in the structure of FIG. 14B, the dv / dt can be reduced because the electric field change can be further smoothed.
[0021]
FIG. 15 is a plan view of the main part of the active region of the present invention as seen from above. (A) is a structure in which a p + anode layer 3c of high concentration and low temperature heat treatment is formed on the entire surface of the active region, and a p anode layer 3b of low concentration and high temperature heat treatment is formed in a cell shape. (B) is a structure in which a p + anode layer 3c of high concentration and low temperature heat treatment is formed in a cell shape, and a p anode layer 3b of low concentration and high temperature heat treatment is formed on the entire active region. (C) and (d) are structures formed in stripes. (E) shows a p + anode layer 3c of high concentration and low temperature heat treatment formed on the entire active region, a p anode layer 3b of low concentration and high temperature heat treatment formed in a cell shape, and a p + anode in the p anode layer 3b. It is a ring cell structure in which the layer 3c is formed. (F) is a structure in which each layer is reversed from (e).
[0022]
FIG. 16 is a cross-sectional view of the main part showing the edge structure of the present invention. In (a), the right side of the dotted line in the figure is the active region, and the left side is the edge portion. This is a general edge structure, and includes a guard ring 6, a stopper region 7, a stopper electrode 8, a field plate 9, and a field oxide film 10. (B) is a structure in which the field oxide film between the active region and the edge portion is made longer than that in (a), making it difficult for carriers to enter under the edge portion during reverse recovery, and increasing the reverse recovery tolerance. FIG. 17 is a perspective sectional view showing the edge structure of the present invention.
[0023]
【The invention's effect】
In the present invention, the p anode layer is ion-implanted with a low dose amount and subjected to a high-temperature heat treatment, and a high dose ion-implantation is performed for low-temperature annealing or laser annealing at 350 ° C. to 600 ° C. By constituting the second anode layer formed at a depth of 1 μm or less by low-temperature heat treatment , the reverse recovery current and reverse recovery loss can be reduced and further soft recovery can be achieved compared to the conventional product. As a result, it is possible to improve the trade-off between high speed and low loss and soft recovery. In addition, by setting the diffusion depth of the p anode layer to 2 μm or more, a predetermined breakdown voltage can be secured, and when formed on the entire surface of the active region, an increase in leakage current due to a Schottky junction can be prevented.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of an essential part of a pin diode according to an embodiment of the present invention. FIG. 2 is a diagram comparing lifetimes of p anode layers of a conventional pin diode and a pin diode of the present invention. FIG. 4 is a cross-sectional view of a principal part showing a configuration in which the present invention is applied to a diode described in Japanese Patent Application No. 2000-31442. FIG. 5 is a diagram illustrating an MPS diode according to the present invention. FIG. 6 is a cross-sectional view of a main part of a pin diode that is a conventional diode. FIG. 7 is a case where the dose amount of a high-concentration p anode layer is changed according to an embodiment of the present invention. Fig. 8 is a characteristic diagram showing the relationship between leakage current and reverse recovery peak current. Fig. 8 is a graph showing the impurity distribution in the depth direction when the heat treatment temperature is changed. Fig. 9 is the heat treatment temperature dependence of leakage current in the present invention. FIG. 10 is a diagram showing the heat treatment temperature dependence of the impurity activation rate and the impurity activation rate. FIG. 10 is a diagram showing the heat treatment temperature dependence of the reverse recovery peak current. FIG. The figure which compared the lifetime of the p anode layer of a diode and the pin diode of this invention [FIG. 13] The figure which showed the impurity distribution of a different Example [FIG. 14] The figure which showed the impurity distribution of a different Example [FIG. 15] FIG. 16 is a fragmentary sectional view showing the edge structure of the present invention. FIG. 17 is a perspective sectional view showing the edge structure of the present invention.
1 n + cathode layer
2 n drift layer
3 p anode layer (product of the present invention)
3a p anode layer (conventional product)
3b Low concentration p anode layer (product of the present invention)
3c High-concentration p anode layer (product of the present invention)
4 Cathode electrode
5 Anode electrode

Claims (3)

第１導電型の半導体基板と、該半導体基板の一方の表面層に形成した第２導電型の低濃度の第１アノード層と、該第１アノード層の表面層に形成した第２導電型の高濃度の第２アノード層と、該第２アノード層表面に形成したアノード電極と、他方の表面に形成した第１導電型のカソード層と、該カソード層表面に形成したカソード電極とを具備する半導体装置の製造方法において、
前記第１アノード層が、第２アノード層のドーズ量より低いドーズ量をイオン注入し、高温熱処理して２μｍ以上の拡散深さに形成し、その後、第２アノード層を３×１０12ｃｍ-2以上３×１０13ｃｍ-2以下のドーズ量をイオン注入し、３５０℃以上６００℃以下の低温アニール又はレーザアニールの低温熱処理して１μｍ以下の深さに形成することを特徴とする半導体装置の製造方法。A first conductivity type semiconductor substrate; a second conductivity type low-concentration first anode layer formed on one surface layer of the semiconductor substrate; and a second conductivity type semiconductor substrate formed on the surface layer of the first anode layer. A high-concentration second anode layer; an anode electrode formed on the surface of the second anode layer; a cathode layer of the first conductivity type formed on the other surface; and a cathode electrode formed on the surface of the cathode layer. In a method for manufacturing a semiconductor device,
The first anode layer is ion-implanted with a dose amount lower than the dose amount of the second anode layer, and is heat-treated to form a diffusion depth of 2 μm or more, and then the second anode layer is 3 × 10 12 cm −. A semiconductor device characterized by forming a depth of 1 μm or less by ion implantation of a dose of 2 or more and 3 × 10 13 cm −2 or less and low-temperature annealing of 350 ° C. or more and 600 ° C. or less and low-temperature heat treatment of laser annealing. Manufacturing method. 前記第１アノード層と第２アノード層の少なくとも一方を複数個互いに離して形成することを特徴とする請求項１に記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1 , wherein at least one of the first anode layer and the second anode layer is formed apart from each other. 第１導電型の半導体基板と、該半導体基板の一方の表面層に複数個互いに離して形成した第２導電型の低濃度の第１アノード層と、該第１アノード層のそれぞれの表面層に形成した第２導電型の高濃度の第２アノード層と、前記第２アノード層と半導体基板の各表面に形成したアノード電極と、他方の表面に形成した第１導電型のカソード層と、該カソード層表面に形成したカソード電極とを具備する半導体装置の製造方法において、
前記第１アノード層が、第２アノード層のドーズ量より低いドーズ量をイオン注入し、高温熱処理して２μｍ以上の拡散深さで複数の第１アノード層が互いに半導体基板表面で重なり合う領域を有するように形成し、その後、第２アノード層を３×１０12ｃｍ-2以上３×１０13ｃｍ-2以下のドーズ量をイオン注入し、３５０℃以上６００℃以下の低温アニール又はレーザアニールの低温熱処理して１μｍ以下の深さに形成することを特徴とする半導体装置の製造方法。A first conductivity type semiconductor substrate, a plurality of second conductivity type low-concentration first anode layers formed on one surface layer of the semiconductor substrate, and a surface layer of the first anode layer, respectively. A second anode layer of high concentration of the second conductivity type formed, an anode electrode formed on each surface of the second anode layer and the semiconductor substrate, a cathode layer of the first conductivity type formed on the other surface, In a manufacturing method of a semiconductor device comprising a cathode electrode formed on a cathode layer surface,
The first anode layer has a region in which a plurality of first anode layers overlap each other on the surface of the semiconductor substrate with a diffusion depth of 2 μm or more by ion implantation with a dose amount lower than that of the second anode layer and heat treatment at a high temperature. After that, the second anode layer is ion-implanted with a dose amount of 3 × 10 12 cm −2 or more and 3 × 10 13 cm −2 or less, and low temperature annealing of 350 ° C. or more and 600 ° C. or less or laser annealing. A method of manufacturing a semiconductor device, wherein the semiconductor device is formed to a depth of 1 μm or less by heat treatment.
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