JP2003224281A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the same which enables reduction of reverse recovery current, reduction of reverse recovery loss and enhancement of soft recovery in comparison with an existing diode. <P>SOLUTION: A p-anode layer 3b is formed by low dose-rate ion implantation with a high acceleration voltage, and a p-anode layer 3c serving as a contact layer is formed by a high dose-rate ion implantation with low acceleration voltage, followed by low-temperature annealing. As a result, a number of flaws are allowed to stay behind the p-anode layer 3c, and with these flaws, the life time of the p-anode layer 3c is lowered, which results in lowering reverse recovery current and reverse recovery loss, and enhancing soft recovery. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a power semiconductor rectifier (hereinafter, simply referred to as a diode).

[0002]

2. Description of the Related Art Diodes are used in various inverters and other devices.
It has been used for power converters, but in recent years
Higher frequency is achieved to improve the efficiency of the burner, 10 kHz
IGBTs and other switches that open and close at the above switching speeds
It has also come to be used as the FWD of the randista, and the reverse turn
There is a strong demand for shortening the return operation time. Figure 6
Is the cross section of the main part of a conventional pin diode
It is a figure. n⁺Epi on the high-concentration substrate that becomes the cathode layer 1.
An n-layer is formed by the axial growth, and p is formed on the surface layer of this n-layer.
The anode layer 3a is formed. n⁺Cathode layer 1 and p-ano
The n layer sandwiched between the ground layers 3a becomes the n drift layer 2. p
The anode layer 3a is 7 × 10¹³cm ^-2Accelerate with dose amount
Ion implantation is performed once at a voltage of 100 keV and at 1150 ° C.
90 minutes high temperature annealing (high temperature heat treatment) to form
It n⁺On the cathode layer 1 and on the p anode layer 3a respectively
Then, the cathode electrode 4 and the anode electrode 5 are formed.

In this pin diode, it is easy to ensure the breakdown voltage, but the p anode layer 3a is formed with a high concentration in order to increase the hole injection efficiency and lower the ON voltage. Therefore, in the reverse recovery characteristic, the peak value Irp of the reverse recovery current Irr becomes high, and hard recovery occurs. Further, the pin diode causes a large electrical loss in the diode due to the product of the reverse recovery current and the reverse recovery voltage. In recent years, there has been a strong demand for reducing the reverse recovery loss and further increasing the switching speed. At present, minority carrier lifetime control using heavy metal diffusion or electron beam irradiation is widely used in order to improve the reverse recovery characteristics of a diode. That is, by reducing the lifetime, the carrier concentration in the steady state is reduced and the carrier concentration swept out by the expansion of the space charge region during reverse recovery is reduced, and the reverse recovery time, reverse recovery current and reverse recovery charge are reduced. Then, the reverse recovery loss can be reduced.

As a means for softening the reverse recovery current, there is a structure for suppressing the injection efficiency of minority carriers from the anode. As its typical structure,
MPS with a Schottky junction and a pn junction (Mer
Ged pin / Schottky) SFD (So
ft and Fast Recovery Period
e) and the like.

[0005]

[Patent Document 1] US Pat. No. 4,641,174

[Patent Document 2] Japanese Patent No. 3149483 (FIG. 1)

[Patent Document 3] Japanese Patent Laid-Open No. 7-226521 (FIG. 3)

[Patent Document 4] Japanese Patent Laid-Open No. 9-321320 (FIG. 1)

[Patent Document 5] Japanese Patent Laid-Open No. 10-200132 (FIG. 1)

[Patent Document 6] Japanese Patent Laid-Open No. 10-321876 (FIG. 1)

[0006]

However, the pin shown in FIG. 6 is used.
In the diode and the MPS diode described above, it is required to further reduce both the reverse recovery current Irr and the reverse recovery loss to achieve further soft recovery. Further, in the diodes of Patent Documents 2 to 6, a high-concentration shallow anode layer and a low-concentration deep anode layer are described, but these are active because the high-concentration anode layer is formed by high-temperature heat treatment. The high recovery with a conversion rate of almost 100% is not preferable for the reverse recovery characteristic. An object of the present invention is to solve the above problems and provide a semiconductor device and a method of manufacturing the same capable of achieving a reduction in reverse recovery current, a reduction in reverse recovery loss, and further soft recovery as compared with a conventional diode. To do.

[0007]

In order to achieve the above-mentioned object, a first conductivity type semiconductor substrate, a second conductivity type anode layer formed on one surface layer of the semiconductor substrate, and the anode layer. A semiconductor device comprising an anode electrode formed on a surface, a first conductivity type cathode layer formed on the other surface, and a cathode electrode formed on the cathode layer surface, wherein the anode layer has a low concentration and a deep anode. Layer and a high concentration and shallow anode layer formed on the surface layer of the low concentration anode layer, and the dose amount of the high concentration anode layer is 3
The depth is not less than × 10 ¹² cm ^{−2 and not} more than 3 × 10 ¹³ cm ⁻² , and the low concentration anode layer has a depth of not less than 2 μm. Further, the low concentration and deep anode layer has a region where a plurality of diffusion layers overlap each other on the surface of the semiconductor substrate, and the maximum concentration of the region is preferably 1 to 10 times the concentration of the semiconductor substrate.

Further, the semiconductor substrate of the first conductivity type and the semiconductor
The second conductive type of low concentration formed on one surface layer of the body substrate
Formed on the first anode layer and a surface layer of the first anode layer;
And a high concentration second anode layer of the second conductivity type, and the second anode
Anode electrode formed on the surface of the cathode layer and
The formed first conductivity type cathode layer and the cathode layer surface
Method for manufacturing semiconductor device having formed cathode electrode
Wherein the first anode layer is a second anode layer
Ion implantation at a dose lower than the dose and high temperature heat treatment
And then form a second anode layer 3 × 10¹²cm
^-23 x 10 or more ¹³cm^-2Ion implantation with the following doses
Then, it is formed by low temperature heat treatment.

The first conductivity type semiconductor substrate, a plurality of second conductivity type low concentration first anode layers formed on one surface layer of the semiconductor substrate so as to be separated from each other, and the first anode layer A second conductive type high-concentration second anode layer formed on each surface layer, an anode electrode formed on each surface of the second anode layer and the semiconductor substrate, and a first conductive type second electrode formed on the other surface. In a method of manufacturing a semiconductor device comprising a cathode layer and a cathode electrode formed on the surface of the cathode layer, the first anode layer is ion-implanted with a dose amount lower than that of the second anode layer, and is heat-treated at a high temperature. Then, the second anode layer is formed by ion implantation with a dose amount of 3 × 10 ¹² cm ⁻² or more and 3 × 10 ¹³ cm ⁻² or less and heat treatment at low temperature.

The temperature of the low temperature heat treatment is preferably 350 ° C. or higher and 600 ° C. or lower. Further, the low temperature heat treatment may be performed by laser annealing. The predetermined diffusion depth of the first anode layer may be 2 μm or more.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, the first conductivity type is n.
And the second conductivity type is p-type. Of course, the reverse is also possible. Further, the same parts as those in FIG. 6 are designated by the same reference numerals.
FIG. 1 is a sectional view of a main part of a pin diode according to an embodiment of the present invention. An n layer is formed by epitaxial growth on a high-concentration substrate to be the n ⁺ cathode layer 1, and a p anode layer 3 is formed on the surface layer of the n layer. The n layer sandwiched between the n ⁺ cathode layer 1 and the p anode layer 3 becomes the n drift layer 2. p
The anode layer 3 is ion-implanted at an acceleration voltage of 100 keV with an extremely low dose amount of about 1 × 10 ¹² cm ^-2 .
It is formed by high-temperature annealing, and a PSG (phosphorus glass) film is further coated at a heat treatment temperature of about 900 ° C., and then the PSG film at the contact portion is removed by etching, and a dose of 3 × 10 ¹³ cm ^-2 is used. The acceleration voltage is 45 ke depending on the quantity
Ion implantation is performed at V and low-temperature annealing at 400 ° C. is performed to form a high-concentration p anode layer 3c of 1 μm or less (the high-concentration p anode layer 3c also serves as a contact layer). In addition, the diffusion depth of the p anode layer 3 including the low concentration anode layer 3b and the high concentration anode layer 3c (which matches the depth of the low concentration p anode layer 3b) is equal to 2 so as not to reach the anode electrode 5
At least μm.

With this low dose amount, a low-concentration p anode layer 3b ion-implanted with a high acceleration voltage of 100 keV.
With the high temperature annealing and the PSG film processing temperature, most of the implanted impurity atoms are activated and most of the defects introduced by ion implantation disappear. On the other hand, in the high-concentration p anode layer 3c, which is ion-implanted with a high dose amount and a low acceleration voltage of 45 keV, many defects introduced by ion implantation remain due to the low temperature annealing at 400 ° C.
This defect reduces the lifetime of the high-concentration p anode layer 3c. Further, when the temperature of the low temperature annealing exceeds 600 ° C., the annihilation ratio of defects introduced by ion implantation is high,
If the temperature is lower than 350 ° C., the activation rate of the ion-implanted impurity atoms is not good. Therefore, the low temperature annealing temperature is 3
It is preferably 50 ° C. or higher and 600 ° C. or lower. Further, by performing the low temperature annealing by laser annealing, the activation rate of the implanted impurity atoms can be improved, and it is possible to prevent the hole injection efficiency from being lowered too much.

Due to the decrease in the lifetime of the low-concentration p anode layer 3b and the high-concentration p anode layer 3c, injection of holes from the p anode layer 3 to the n drift layer 2 is suppressed.
As a result, the reverse recovery current and the reverse recovery loss decrease, the carrier concentration near the n ⁺ cathode layer 1 becomes higher than the carrier concentration near the p anode layer 3, and further soft recovery can be achieved. Further, by setting the diffusion depth of the low-concentration p anode layer 3b to 2 μm or more, it is possible to prevent the depletion layer from reaching the anode electrode 5 at the rated voltage. FIG. 2 is a diagram showing the relationship between the diffusion profile and lifetime distribution. FIG. 2 (a) is a diagram showing the diffusion profile. In the figure, 3a is a conventional product profile, 3 is a p-anode of the present invention product. The profile of the entire layer, 3b is the low-concentration portion of the product of the present invention, 3c is the high-concentration portion profile
The figure (b) is a figure which shows the lifetime distribution of a conventional product, and the figure (c) is a figure which shows the lifetime distribution of this invention product.
The figure (b) is an estimate of the lifetime distribution of the conventional diode, but the lifetime of the diode disclosed in Japanese Patent No. 3149483 which is similar to the product of the present invention in terms of diffusion profile is also estimated. Estimated to be the same. Since the conventional product is annealed at a high temperature, the p anode layer 3a has a relatively long lifetime. Compared with this conventional product, the product of the present invention is annealed at a low temperature, so that the lifetime value of the p anode layer 3b becomes smaller.

FIG. 3 is a reverse recovery waveform diagram of the conventional pin diode and the pin diode of the present invention. Since the pin diode (invention product) of the present invention has an extremely low concentration of the p anode layer 3 as compared with the conventional pin diode (conventional product), the peak value Irp of the reverse recovery current Irr is significantly reduced. Furthermore, since the injection of holes is low, a distribution with a large number of carriers is formed on the cathode side in the state where a forward current is applied, resulting in a soft recovery waveform. By using the present invention, a diode with a high breakdown voltage of about 600 V having a thin drift layer of several tens of μm, which is conventionally difficult to realize soft recovery, can be soft recovered. That is, an MPS diode having a high breakdown voltage of about 600 V or more, which has a drift layer as thin as several tens of μm, can be used as a diode in which the voltage / current waveform does not oscillate and the loss is small in the reverse recovery process.

The present invention is applied to Japanese Patent Application No. 2000-3114.
P of the diode and MPS diode described in No. 42
By applying it to the anode region, the same effect as in the case of the configuration of FIG. 1 can be obtained. FIG. 4 shows Japanese Patent Application No. 2000-3114.
42 is a sectional view of a key portion showing a configuration in which the present invention is applied to the diode described in No. 42. FIG. The difference from FIG. 1 is that the low concentration p anode layer 3b is formed so that the p anode layer 3 has an overlapping portion, and the high concentration p anode layer 3c is formed on the entire surface of the low concentration p anode layer 3b. That is the point. FIG. 5 is a sectional view of an essential part showing a configuration in which the present invention is applied to an MPS diode. In FIG. 5, the high concentration p anode layer 3c is formed on the surface of the low concentration p anode layer 3b formed dispersedly.

FIG. 7 is a characteristic diagram showing the relationship between the leakage current and the reverse recovery peak current (Irp) when the dose amount of boron in the high-concentration p anode layer 3c is changed. In FIG. 7, when the dose amount of boron is 3 × 10 ¹² cm ⁻² or less, the leakage current sharply increases. This is because when the dose amount is small, the depletion layer spreads to the surface of the semiconductor substrate and punches through. The reverse recovery peak current sharply increases when the dose amount of boron is 3 × 10 ¹³ cm ⁻² or more. This increase in the reverse recovery peak current is due to the increase in hole injection. Therefore, the dose amount of the high-concentration p anode layer 3c is 3 × 10 ¹² cm ⁻² or more and 3 ×.
It is preferably 10 ¹³ cm ⁻² or less.

FIG. 8 is a diagram showing the impurity distribution in the depth direction when the heat treatment temperature is changed. In FIG. 8, the p anode layer 3 has a boron dose amount of 7 × 10 ¹³ cm ^−2.
As a result, the distribution of impurity diffusion in the depth direction was compared when the heat treatment temperature was 1150 ° C. high temperature heat treatment (corresponding to the prior art) and 400 ° C. low temperature heat treatment (present invention). In the high temperature heat treatment, the diffusion depth becomes 3.5 μm, the effective dose amount becomes 5.0 × 10 ¹³ cm ⁻² , and the activation rate is almost 1
It is 00%. On the other hand, in the low temperature heat treatment of the present invention, the diffusion depth is 0.6 μm, the effective dose amount is 5.2 × 10 ¹² cm ⁻² , and the activation rate is 10% or less. By performing the low temperature heat treatment, the effective dose of impurities can be reduced.

FIG. 9 is a diagram showing the heat treatment temperature dependence of the leakage current and the heat treatment temperature dependence of the impurity activation rate in the present invention. When the heat treatment is performed at 600 ° C. or lower, the impurity activation rate is about 10%, and when the heat treatment is performed at 800 ° C. or higher, the impurity activation rate is about 100%. On the other hand, the reverse leakage current does not depend on the temperature and is almost constant. In addition, MP
When the Schottky junction is mixed with the pn junction as in the S structure, the leakage current increases. In the present invention, this M
The leakage current can be reduced as compared with the PS structure. FIG. 10 is a diagram showing the heat treatment temperature dependence of the reverse recovery peak current. In FIG. 10, the SSD diode has a reverse recovery peak current of 46 A, and the MPS diode has a reverse recovery peak current of 25 A. In the present invention, by setting the heat treatment temperature to 600 ° C. or lower, the reverse recovery peak current value comparable to that of the MPS diode can be obtained. Therefore, the heat treatment temperature of the second anode layer is preferably 300 ° C. or higher and 600 ° C. or lower.

FIG. 11 is a sectional view of the essential parts of a different embodiment. In FIG. 11, a high concentration p anode layer 3c is formed on the entire surface of the active region in which the low concentration p anode layer 3b is formed. By forming the high-concentration p anode layer 3c on the entire surface of the active region in this manner, the Schottky junction does not exist as compared with the structure having the Schottky junction shown in FIG. 5, so that the leakage current is significantly reduced. be able to. As a result, it is possible to reduce leakage current defects when the bonding wires are bonded after the electrodes are formed on the substrate surface. FIG. 12 is a diagram showing the relationship between the diffusion profile and the lifetime distribution. FIG. 12 (a) is a diagram showing the diffusion profile. In the figure, 3b is a low-concentration portion of the product of the present invention, and 3c is a high-concentration portion. FIG. 3B is a profile showing the lifetime distribution of the conventional product and the product of the present invention. Since the conventional product is annealed at a high temperature, the p anode layer 3a has a relatively long lifetime. Compared with this conventional product, the product of the present invention is annealed at a low temperature, so that the lifetime value of the p anode layer 3b becomes smaller. FIG. 6C shows a lifetime distribution when platinum diffusion (Pt) and electron beam irradiation (EI) are used as the lifetime killer in the diode of the present invention. In the case of EI, the lifetime distribution is uniform. Pt
In this case, the defects segregate on the anode side, and the lifetime on the anode side is shortened.

FIGS. 13 and 14 are diagrams showing the impurity distribution of different embodiments. FIG. 13A shows a cathode electrode and n
A high concentration layer (n + layer) is formed between the cathode layers by As ion implantation. First, after forming the p anode layer on the surface of the semiconductor substrate, the back surface of the semiconductor substrate is shaved, and As (arsenic) is ion-implanted from the back surface at a dose amount of 2 × 10 ¹⁴ cm ⁻² accelerating voltage of 100 keV, and then heat treatment is performed at 1100.
A high concentration n ⁺ layer having a thickness of about 1 μm is formed by performing the treatment at a temperature of ° C.
Further, Ti is used for the cathode electrode, and it is formed by vapor deposition so as to make ohmic contact with this high-concentration n ⁺ layer. The ion implantation performed from the back surface may be P (phosphorus), but As
Compared with P, this is preferable because it has a smaller diffusion coefficient and shallower thermal diffusion, so that the surface concentration can be increased. If the diffusion temperature after ion implantation is 1100 ° C., the diffusion depth of As does not exceed 1 μm due to the diffusion coefficient and other factors. In this embodiment, a low Vf (forward voltage) can be achieved. FIG. 13B shows a structure in which the n ⁻ drift layer is formed in two stages. With this structure, it is possible to suppress the oscillation phenomenon by suppressing the spread of the electric field during reverse recovery and leaving a large amount of carriers on the cathode side. FIG. 13C shows
This is a structure in which an n ⁺ layer is diffused into an n ⁻ layer. from n ⁻ layer to n ⁺
The reverse recovery charge (Qrr) increases by making the distribution in which the impurity concentration gradually increases over the layer, but it is effective for soft recovery. FIG. 13D shows the n ⁻ layer to the n ⁺ layer.
This is a two-stage gradient structure in which the impurity concentration gradually increases over the layers and the increase is divided into two times. With this structure, the loss can be reduced as compared with the structure of (c), and it is also effective for soft recovery. Figure 1
4 (a) is a structure in which the impurity concentration is gradually increased from the anode side to the cathode side using a bulk wafer, and an n ⁺ layer of several μm is formed from the back surface of the semiconductor substrate by ion implantation. This structure suppresses the injection of electrons from the n + layer and gradually suppresses the spread of the electric field, so that soft recovery and low loss characteristics can be obtained. (B) in FIG. 14, n ^- n in the layer ^- which is a high concentration n-layer structure formed of several μm (the buffer layer) thickness than the layers. In this structure, the expansion of the electric field during reverse recovery can be suppressed by this buffer layer, and the oscillation phenomenon can be suppressed by leaving more carriers on the cathode side. FIG. 14C shows n
^- a structure that the impurity concentration toward the center of the layer gradually increases. Although the spread of the electric field can be suppressed as in the structure of FIG. 14B, dv / dt can be reduced because the electric field change can be further smoothed.

FIG. 15 is a plan view of an essential part of the active region of the present invention seen from above. (A) shows a structure in which the p ⁺ anode layer 3c of high concentration and low temperature heat treatment is formed on the entire surface of the active region, and the p anode layer 3b of low concentration and high temperature heat treatment is formed in a cell shape. (B) is a high-concentration, low-temperature heat-treated p ⁺ anode layer 3c
Is formed in a cell shape, and the p anode layer 3b subjected to high temperature heat treatment at a low concentration is formed on the entire surface of the active region. (C) and (d) are structures formed in stripes. (E)
Forms a high concentration and low temperature heat-treated p ⁺ anode layer 3c on the entire surface of the active region, and a low concentration and high temperature heat treatment p anode layer 3c.
This is a ring cell structure in which b is formed in a cell shape, and ap ⁺ anode layer 3c is further formed in the p anode layer 3b. (F) is a structure in which each layer is reversed from (e).

FIG. 16 is a cross-sectional view of an essential part showing the edge structure of the present invention. In (a), the active area is on the right side of the dotted line in the figure, and the edge part is on the left side. This is a general edge structure and includes a guard ring 6, a stopper region 7,
A stopper electrode 8, a field plate 9 and a field oxide film 10 are provided. (B) is a structure in which the field oxide film between the active region and the edge portion is made longer than that in (a) to make it difficult for carriers to enter under the edge portion during reverse recovery, and the reverse recovery withstand capability is increased. FIG. 17 is a perspective sectional view showing the edge structure of the present invention.

[0023]

According to the present invention, the p anode layer is formed by ion-implanting a low dose of ions and heat-treating at high temperature.
By constructing the anode layer and the second anode layer formed by high-dose ion implantation and low-temperature heat treatment, the reverse recovery current and reverse recovery loss are reduced compared to the conventional product, and further soft recovery is achieved. Can be planned. As a result, it is possible to improve the drapoff between high speed / low loss and soft recovery. Further, by setting the diffusion depth of the p anode layer to 2 μm or more, a predetermined breakdown voltage can be secured, and when formed on the entire surface of the active region, an increase in leakage current due to the Schottky junction can be prevented.

[Brief description of drawings]

FIG. 1 is a sectional view of a main part of a pin diode according to an embodiment of the present invention.

FIG. 2 is a diagram comparing lifetimes of p anode layers of a conventional pin diode and a pin diode of the present invention.

FIG. 3 is a reverse recovery waveform diagram of a conventional pin diode and a pin diode of the present invention.

FIG. 4 is a sectional view of an essential part showing a configuration in which the present invention is applied to a diode described in Japanese Patent Application No. 2000-31142.

FIG. 5 is a sectional view of an essential part showing a configuration in which the present invention is applied to an MPS diode.

FIG. 6 is a cross-sectional view of a main part of a pin diode which is a conventional diode

FIG. 7 is a characteristic diagram showing the relationship between the leakage current and the reverse recovery peak current when the dose amount of the high-concentration p anode layer according to the embodiment of the present invention is changed.

FIG. 8 is a diagram showing the impurity distribution in the depth direction when the heat treatment temperature is changed.

FIG. 9 is a diagram showing the heat treatment temperature dependence of the leakage current and the heat treatment temperature dependence of the impurity activation rate in the present invention.

FIG. 10 is a diagram showing the heat treatment temperature dependence of the reverse recovery peak current.

FIG. 11 is a cross-sectional view of main parts of a different embodiment.

FIG. 12 is a diagram comparing lifetimes of p anode layers of a conventional pin diode and a pin diode of the present invention.

FIG. 13 is a diagram showing the impurity distribution of different examples.

FIG. 14 is a diagram showing the impurity distribution of different examples.

FIG. 15 is a plan view of an essential part of the active region of the present invention seen from above.

FIG. 16 is a sectional view of an essential part showing an edge structure of the present invention.

FIG. 17 is a perspective sectional view showing an edge structure of the present invention.

[Explanation of symbols]

1 n ⁺ cathode layer 2 n drift layer 3 p anode layer (product of the present invention) 3a p anode layer (conventional product) 3b low concentration p anode layer (product of the present invention) 3c high concentration p anode layer (product of the present invention) 4 Cathode electrode 5 Anode electrode

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masato Otsuki             1-1 Tanabe Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa             Within Fuji Electric Co., Ltd. F-term (reference) 4M104 BB14 CC01 CC03 DD19 DD26                       DD78 DD81 GG02 GG03 GG18                       HH20

Claims (7)

[Claims] 1. A semiconductor substrate of a first conductivity type, and an anode layer of a second conductivity type formed on one surface layer of the semiconductor substrate,
A semiconductor device comprising an anode electrode formed on the surface of the anode layer, a cathode layer of the first conductivity type formed on the other surface, and a cathode electrode formed on the surface of the cathode layer, wherein the anode layer has a low concentration. A deep anode layer and a high concentration and shallow anode layer formed on the surface layer of the low concentration anode layer, and the dose amount of the high concentration anode layer is 3 × 1.
A semiconductor device having a depth of 0 ¹² cm ⁻² or more and 3 × 10 ¹³ cm ⁻² or less, and a depth of the low-concentration anode layer is 2 μm or more. 2. The low concentration and deep anode layer has a region in which a plurality of diffusion layers overlap each other on a semiconductor substrate surface,
The maximum concentration of the region is 1 times or more the concentration of the semiconductor substrate 10
The semiconductor device according to claim 1, wherein the semiconductor device has a number of times less than or equal to twice. 3. A first conductivity type semiconductor substrate, a second conductivity type low concentration first anode layer formed on one surface layer of the semiconductor substrate, and a surface layer of the first anode layer. Second
A conductive type high-concentration second anode layer, an anode electrode formed on the surface of the second anode layer, a first conductive type cathode layer formed on the other surface, and a cathode electrode formed on the surface of the cathode layer In the method of manufacturing a semiconductor device, the first anode layer is formed by ion-implanting a dose amount lower than that of the second anode layer and performing high temperature heat treatment,
After that, the second anode layer is formed with a thickness of 3 × 10 ¹² cm ⁻² or more and 3 × 1.
A method of manufacturing a semiconductor device, which comprises ion-implanting a dose amount of 0 ¹³ cm ^-2 or less, and performing heat treatment at a low temperature. 4. A first-conductivity-type semiconductor substrate, a plurality of second-conductivity-type low-concentration first anode layers formed on one surface layer of the semiconductor substrate so as to be separated from each other; A second conductive type high-concentration second anode layer formed on each surface layer, an anode electrode formed on each surface of the second anode layer and the semiconductor substrate, and a first electrode formed on the other surface.
In a method of manufacturing a semiconductor device comprising a conductive type cathode layer and a cathode electrode formed on the surface of the cathode layer, the first anode layer is ion-implanted at a dose amount lower than that of the second anode layer, Formed by high temperature heat treatment,
After that, the second anode layer is formed with a thickness of 3 × 10 ¹² cm ⁻² or more and 3 × 1.
A method of manufacturing a semiconductor device, which comprises ion-implanting a dose amount of 0 ¹³ cm ^-2 or less, and performing heat treatment at a low temperature. 5. The temperature of the low temperature heat treatment is 350 ° C. or higher. 6
The method for manufacturing a semiconductor device according to claim 3, wherein the temperature is 00 ° C. or lower. 6. The method of manufacturing a semiconductor device according to claim 3, wherein the low temperature heat treatment is performed by laser annealing. 7. The predetermined diffusion depth of the first anode layer is set to 2
The method for manufacturing a semiconductor device according to claim 3, wherein the thickness is at least μm.