CN105895678A

CN105895678A - Back surface structure, of semiconductor power device, manufactured on epitaxial wafer

Info

Publication number: CN105895678A
Application number: CN201510025366.9A
Authority: CN
Inventors: 苏冠创; 黄升晖
Original assignee: Nanjing Lisheng Semiconductor Technology Co Ltd
Current assignee: Nanjing Lisheng Semiconductor Technology Co Ltd
Priority date: 2015-01-14
Filing date: 2015-01-14
Publication date: 2016-08-24

Abstract

The invention discloses a back surface structure, of a semiconductor power device, manufactured on an epitaxial wafer. The back surface of the device is characterized in that: a main doping region of the back surface of the device is introduced when growing an epitaxial layer, wherein the a P+ region 14 is formed by ditching a slot in the surface of a substrate, filling the slot with a P+ epitaxial layer and then removing an epitaxy on the surface of the substrate, or formed by growing the epitaxial layer at least one time. The greatest difference between the back part structure of a PT-IGBT and the back surface structure is that the back surface structure provided by the invention comprises an electronic channel, when the semiconductor power device is switched off, electrons can flow to a back surface electrode quickly via the electronic channel, thereby the switching-off loss is reduced, a wafer is thinned to near the middle of the P+ region 14 through wearing after completing the previous process, and then the wafer is subjected to back surface metallization to form the back surface electrode.

Description

A kind of manufacture is in the structure of epitaxial silicon chip semiconductor-on-insulator power device

Technical field:

The present invention relates to the structure of a kind of semiconductor power device, manufactures outside more particularly to one Prolong the structure of silicon chip semiconductor-on-insulator power device.

Background technology:

1980, RCA Corp. of the U.S. applied for first IGBT patent, and within 1985, Toshiba Corp makes First industrial IGBT.From device physically for, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT-is abbreviated as PT-IGBT).PT-IGBT It is to manufacture on epitaxial silicon chip, is usually at P⁺One layer of N-type relief area of Grown, grows a N the most again^- District, the resistance to voltage device of 1200V to be manufactured, just need to grow a N-type relief area, doping content is about 1×10¹⁷/cm³, thickness is about 10um, and then regrowth one epitaxy layer thickness is about 110um, and doping content is about It is 5 × 10¹³/cm³To 1 × 10¹⁴/cm³N^-District, this is relatively thicker epitaxial layer.Pressure higher to manufacture PT-IGBT, as pressure for 2500V or 3300V, then N^-District needs thicker and higher resistivity.Growth So the extension of specification, technically has any problem, and cost can drastically increase, so, PT-IGBT is general only Be applicable to pressure for 400V to 1200V in the range of.

The turn-off time of PT-IGBT in early days is relatively long, there are about several microsecond, in order to shorten the turn-off time, carries High switching speed, after the nineties, the most all quote high energy particle irradiation technique (such as electron irradiation, hydrogen from Son or helium ion irradiation etc.) reduce excess carrier lifetime in device.This method can improve PT-IGBT's Switching speed, but on state voltage can be made to reduce to negative temperature coefficient.The most in the on-state, if be maintained to flow through Collector current is constant, then the voltage difference between current collection best generating pole can raise with temperature and reduce.Answering Used time, if device somewhere local temperature is higher, then having more conducting electric current and flow through at this, this can make this Place's temperature becomes higher, it is possible to make device enter a positive feedback state, finally device is burnt, this Voltage reduces to the performance deficiency that negative temperature coefficient is PT-IGBT.

As it was previously stated, PT-IGBT be typically only applicable to pressure for 400V to 1200V in the range of, to manufacture Pressure for 1700V or 2500V or 3300V or more than, in early days all use non-punch through IGBT (Non-punchthrough IGBT, be abbreviated as NPT-IGBT), device is fabricated directly in thickness to be had hundreds of micro- In the FZ N-type silicon chip of rice, p type island region or the p-type/N-type region of device collector junction are formed by ion implanting. The voltage of this non-punch through IGBT reduces to positive temperature coefficient.The structure of this collector junction is also used for device such as MCT or GTO etc..Owing to the doping of collector junction is formed by ion implanting, the dosage of injection can arbitrarily control, if The P-type dopant amount injected is high, then can form general high hole injection efficiency collector junction (i.e. strong colelctor electrode)； If the P-type dopant amount injected is little, then hole injection efficiency is low, and electronics can via diffusion effectively Flowing through p type island region to metal contact position, this kind of collector junction is referred to as weak collector junction or transparent collector junction and (or is referred to as thoroughly Bright colelctor electrode).During 94 and 95 years, weak collector junction was once used for NPT-IGBT and GTO, if weak collection Electricity knot method is used for manufacturing 600V or 1200V IGBT, then the collector junction of IGBT needs to make at only about 60um Or on the FZ N-type silicon chip back side of about 120um thickness, during 94 and 95 years, industrial quarters does not also have this super Thin silicon wafer technological ability.

In 1996, motorola inc delivered an article and has described the research about manufacturing non-break-through IGBT, Stressing how to manufacture in thin silicon wafer the technique of colelctor electrode, the thinnest about 170um of FZ N-type silicon chip used is thick. In next year, Infineon company has also delivered the NPT-IGBT making 600V by the FZ N-type silicon chip that 100um is thick. About 99 years, the IGBT of industrial a new generation started to go into operation, and the IGBT of this new generation is that a kind of high speed is opened Closing device, its voltage reduces to positive temperature coefficient, and it need not shorten in device few with heavy metal or irradiation In the sub-life-span, main technology is that ultra thin silicon wafers technique is plus weak collector junction (or the most transparent collector junction). Infineon company is referred to as field cut-off IGBT, the following years, company's all phases of each main production IGBT Continue and release similar product.From that time, IGBT has obtained qualitative leap on electric property, quickly grows And dominated the market of medium power range.This field cut-off IGBT manufacturing process can be divided into preceding working procedure and Later process, preceding working procedure is the surface cell device and terminal structure, such as the UMOS on IGBT device surface Unit, manufactures the front surface at silicon chip, after front road technique completes, silicon chip wear down to desired thickness, as wanted Manufacturing the resistance to voltage device of 400V, desired thickness is about 40um, then the back surface of silicon chip is injected N type dopant And P-type dopant, then with annealing steps, the N type dopant injected and P-type dopant are activated, formed The p type island region of collector junction and N-type relief area, metallize silicon chip back surface with sputtering or deposition process afterwards, As the backplate of device, metal layer material can be Al/Ti/Ni/Ag or Ti/Ni/Ag or Al/Ti/Ni/Au Deng.

Before described later process, back side implantation step of making the silicon chip after wear down therein is to have very much challenge , how this step is put into the silicon chip after wear down in ion implantation apparatus or taking-up etc. from ion implantation apparatus Non-easy thing, when carrying out ion implanting, silicon chip makees high speed rotating, how can carry out injecting and will not It is directed at that to make the silicon chip of high speed rotating broken be a great problem, it is understood that, once silicon chip is broken in ion implantation apparatus Falling is to need to expend a great deal of time the tiny broken silicon wafers removed in ion implantation apparatus, and this technique will be overcome difficult Topic, is very difficult for volume production, can be slightly easy to pressure higher device such as 1700V, because Silicon chip after wear down has 170um thick, the thinnest, more disposable；But to pressure relatively low device such as 200V Will be extremely difficult, because the silicon chip after wear down may only have 20um thick, this is the most intractable, except right Thin slice injects, and also to manage to activate the adulterant injected, because just having aluminum metal after completing preceding working procedure at silicon The surface of sheet, this makes the annealing temperature in the technique of back be limited in 450C, and these process difficulties all make Field cut-off IGBT must be manufactured be not easy.

Summary of the invention:

The above silicon chip back side after wear down said carries out ion implanting and annealing steps is all to manufacture field to cut Only the very difficult technique of device, the most disposable, it is an object of the invention to propose one and is avoided that above-mentioned work The difficult point of skill and the structure of a kind of semiconductor power device of practical, the present invention cuts with field before Only the most significantly different part of back structures of device be the present invention be to manufacture on epitaxial silicon chip, device back side master The doped region wanted introduces when grown epitaxial layer, and extension is usually in low-doped Grown, front road After technique completes, near silicon chip wear down to epitaxial layer and substrate intersection, what then removal grinding caused lacks Fall into, then carry out back face metalization and form backplate.The present invention and manufacture are on epitaxial silicon chip The most significantly different part of back structures of PT-IGBT is that the back structures of the present invention has electron channel, works as device When turning off in the case of inductive load, electronics can flow to backplate rapidly via electron channel, thus Increase turn-off speed, reduce turn-off power loss.

Implement the present invention and have following several different scheme for IGBT:

Scheme (1): be the structure cross section of general punch IGBT device with reference to Fig. 1 and Fig. 2, Fig. 1 Schematic diagram, the substrate of this device is thicker, is p-type, as device conducting time hole emission pole, grind Still it is thicker than 100um after mill, and structure does not has electron channel, Fig. 2 to be the structure of device of the present invention Cross sectional representation, the main doped region at the back side of the device of the present invention introduces when grown epitaxial layer, Extension is usually in substrate doping less than 1 × 10¹⁸/cm³Grown, the structure of device is extremely Include less with lower part:

(1) in a quasiconductor back surface at least independent P+ district 14, width is more than 10um, this P+ district While the formation Ohmic contact that is connected with back metal, another side is N-type relief area 10, and this P+ district mixes Miscellaneous maximum concentration scope is 5 × 10¹⁸/cm³To 1 × 10²⁰/cm³, when device is in conducting, this P+ doped region is It is used for into injection hole；

(2) near a quasiconductor back surface at least N-type relief area 10, width is more than 10um, this N Type relief area 10 near quasiconductor back surface while there being segment boundary Shi Yu P+ district 14 to be connected, have portion Point border is to be connected with substrate 12, and another side is low concentration doped N-type base 9, this N-type relief area Doping maximum concentration scope is 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, the district between P+ doped region is electron channel, When device turns off in the case of inductive load, electronics can flow to backplate rapidly via electron channel；

(3) quasiconductor back surface has two kinds of different doped regions and back metal contacts, and both is different Doped region be P+ district 14 and substrate 12, wherein P+ district is to fill out extension at low-doped substrate surface digging groove Removing (with reference to figures 11 to Figure 16) that the epitaxial layer on substrate surface is formed after Ceng again, substrate doping is less than 1×10¹⁸/cm³, or at growth at least one times, prolong (referring to figures 19 through Figure 26) that layer is formed；

(4) quasiconductor back surface is connected with metal layer on back formation backplate, wherein metal level with P+ district 14 forms Ohmic contact and forms non-ohmic contact with substrate 12.

After front road technique completes, near the centre at silicon chip back side wear down to P+ district 14, then remove grinding and draw The defect risen, then carries out back face metalization and forms backplate, such structure and processing technology Can be avoided and ion implanting is done at the thin slice back side.

In order to make the starting voltage of conducting drop lower, can be big through the width making P+ district, the some of them back side 14 In certain size, such as 100um, the P+ district of this bigger width can make the starting voltage of conducting be reduced to 0.7V or Lower.

Scheme (2): with reference to Fig. 3, the main doped region at the back side of the device of the present invention is to introduce when grown epitaxial layer , extension is usually in substrate doping less than 1 × 10¹⁸/cm³Grown, device the back side knot Structure at least includes with lower part:

(1) in a quasiconductor back surface at least independent P+ district 14, width is more than 10um, this P+ district While the formation Ohmic contact that is connected with back metal, another side is N-type relief area 10, N-type relief area Doping maximum concentration scope is 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, the doping maximum concentration scope in this P+ district is 5×10¹⁸/cm³To 1 × 10²⁰/cm³, when device is in conducting, the injection in hole is essentially from this P+ doped region；

(2) at the p type island region 16 near a quasiconductor back surface at least independent low concentration doping, width More than 10um, the p type island region 16 of this low concentration doping is between P+ doped region, the P of this low concentration doping Type district 16 has while being connected with back metal, and having is N-type relief area 10, the P of this low concentration doping The doping maximum concentration scope in type district 16 is 1 × 10¹⁴/cm³To 1 × 10¹⁸/cm³, low dense between P+ doped region The p type island region 16 of degree doping is electron channel, and when device turns off in the case of inductive load, electronics can be through Backplate it is flow to rapidly by electron channel；

(3) having four kinds of different doped regions near semiconductor back surface, the doped region that these four is different is P+ district 14, the p type island region 16 of low concentration doping, N-type relief area 10 and N-type base 9, wherein N-type buffering District 10 and N-type base 9 are formed during grown epitaxial layer, and wherein district of P+ district 14 is low-doped Substrate surface digging groove removes the (technological process that the epitaxial layer on substrate surface is formed again after filling out epitaxial layer Refer to Figure 11 to Figure 16), substrate doping is less than 1 × 10¹⁸/cm³, or at growth at least one times Prolong (technological process refers to Figure 19 to Figure 26) that layer is formed；Wherein the p type island region 16 of low concentration doping is permissible During grown epitaxial layer, (device Structure of cross section refers to Fig. 3,4 and 5 in formation；Technological process can With reference to figures 11 to Figure 16 with referring to figures 19 through Figure 26), can also be to be noted by ion after completing grinding back surface Enter (device Structure of cross section refers to Fig. 6) formed；

(4) quasiconductor back surface have two kinds of different doped regions be connected with metal layer on back formation the back side Electrode, wherein has two kinds of situations: the first situation (device Structure of cross section refers to Fig. 3,5 and 6)；Wherein P+ district 14 and metal level form the p type island region 16 of Ohmic contact and low concentration doping and form non-ohm with metal level Contact, the second situation (device Structure of cross section refers to Fig. 4) is that wherein P+ district 14 is formed with metal level Ohmic contact and low concentration doping substrate 12 form non-ohmic contact with metal level.

Structure can make the width in P+ district, the some of them back side 14 more than certain size, and such as 100um, this is relatively The P+ district of big width can make the starting voltage of conducting be reduced to 0.7V or lower.

After front road technique completes, near the centre at silicon chip back side wear down to P+ district 14, then remove grinding and draw The defect risen, then carries out back face metalization and forms backplate, such structure and making.

Scheme (3) is with reference to Fig. 7, and the present invention is to can be used for RC-IGBT, the main doping at the back side of the device of the present invention District introduces when grown epitaxial layer, and the structure of device at least includes with lower part:

(1) near a quasiconductor back surface at least independent P+ district 14, width is more than 10um, this P+ district while the formation Ohmic contact that is connected with back metal, another side is N-type relief area 10, and N-type buffers The doping maximum concentration scope in district is 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, the doping maximum concentration model in this P+ district Enclose is 5 × 10¹⁸/cm³To 1 × 10²⁰/cm³, when device is in conducting, the injection in hole is mixed essentially from this P+ Miscellaneous district；

(2) near a quasiconductor back surface at least independent N+ district 18, width is more than 10um, this N+ district is at least while the formation Ohmic contact that is connected with back metal, the doping maximum concentration scope in this N+ district It is 5 × 10¹⁸/cm³To 1 × 10²⁰/cm³；

(3) having three kinds of different doped regions near semiconductor back surface, the doped region that these three is different is P+ district 14, N+ type district 18 and N-type relief area 10, these three doped region is shape during grown epitaxial layer Become, have several different method can form district 14 of N+ district 18 and P+:

Method one: wherein P+ district 14 is to remove after N+ type doped substrate surface digging groove fills out P+ epitaxial layer again Being epitaxially formed on substrate surface, P+ to be ground to district, the back side 14 just stops near the centre in N+ district 18 Carry out back face metalization；

Method two: wherein P+ district 14 is to remove after filling out P+ epitaxial layer at low-doped substrate surface digging groove again Extension on substrate surface, injects N-type high-dopant concentration to silicon face afterwards, and during by method two, the back side to be ground Neighbouring just stopping carries out back face metalization with the centre in N+ district to be milled to P+ district 14；

Method three: prolong what layer was formed through at least growing once place, notes through mask plate as delayed outside growth ground floor Enter p-type high-dopant concentration and N-type high-dopant concentration forms district 18 of P+ district 14 and N+ partly, the longest Second layer extension, is then poured into p-type high-dopant concentration and N-type high-dopant concentration forms P+ district 14 partly With N+ district 18 (with reference to Fig. 7 and Fig. 9), the district of P+ district 14 and N+ 18 formed afterwards with formed before P+ district 14 is connected with N+ district 18, forms a district 18 of continuous print P+ district 14 and N+, or only implanting p-type is high Doping content forms the P+ district 14 (with reference to Fig. 8 and Figure 10) of part；The P+ district 14 formed afterwards is therewith The P+ district 14 of front formation is connected, and forms a continuous print P+ district 14, P+ to be ground to district, the back side 14 and N+ Just stop near the centre in district 18 and carry out back face metalization；

Doped region between P+ doped region is electron channel, when device turns off in the case of inductive load, and electronics Backplate can be flow to rapidly via electron channel；

(4) quasiconductor back surface at least two kinds of different doped regions are connected with metal layer on back formation Backplate, wherein metal level and type district 18 of P+ district 14 and N+ form Ohmic contact.

This structure is somewhat like anode in short circuit, and the starting voltage of conducting may be a little big, solves this problem The width that can make P+ district, the some of them back side 14 is more than certain size, such as 100um, the P+ of this bigger width District can make the starting voltage of conducting be reduced to 0.7V or lower.

After front road technique completes, near the centre at silicon chip back side wear down to type district of P+ district 14 and N+, then go Except grinding the defect caused, then carry out back face metalization and form backplate, wherein metal level and P+ district 14 and N+ type districts 18 form Ohmic contact, and such structure and processing technology can be avoided thin slice Ion implanting is done at the back side.

The above some scheme is more suitable for IGBT or RC-IGBT, and some is more suitable for FRRD, greatly In cause the scheme of each structure be used equally to semiconductor power device such as IGBT or RC-IGBT or FRRD or IGBT Yu FRRD is integrated on the same chip or MCT or GTO or power MOS pipe.

Accompanying drawing explanation

Accompanying drawing is used for providing a further understanding of the present invention, is used for explaining this together with embodiments of the present invention Invention, is not intended that limitation of the present invention, in the accompanying drawings:

Fig. 1 is the cross-sectional structure schematic diagram of general punch IGBT device；

Fig. 2 is the structure cross sectional representation of the device of the present invention program (1)；

Fig. 3 is the structure cross sectional representation of the device of the present invention program (2)；

Fig. 4 is the structure cross sectional representation of another device of the present invention program (2)；

Fig. 5 is the structure cross sectional representation of another device of the present invention program (2)

Fig. 6 is the structure cross sectional representation of another device of the present invention program (2)；

Fig. 7 is the structure cross sectional representation of the device of the present invention program (3)；

Fig. 8 is the structure cross sectional representation of another device of the present invention program (3)；

Fig. 9 is the structure cross sectional representation of another device of the present invention program (3)；

Figure 10 is the structure cross sectional representation of another device of the present invention program (3)；

Figure 11 is exposure oxide layer schematic diagram in the embodiment of the present invention 1；

Figure 12 is groove schematic diagram in the embodiment of the present invention 1；

Figure 13 is to grow P+ epitaxial layer with silicon chip surface in groove in the embodiment of the present invention 1；

Figure 14 is with the epitaxial layer schematic diagram on plane chemistry etching away substrate surface in the embodiment of the present invention 1；

Figure 15 is that the embodiment of the present invention 1 is to silicon chip surface implanting p-type adulterant (p type island region 16) schematic diagram；

Figure 16 is that the embodiment of the present invention 1 completes to grow N-type buffering epitaxial layer 10 and a low-mix at silicon chip surface Miscellaneous N-type epitaxy layer 9；

Figure 17 is the embodiment of the present invention 1 horizontal stroke of device architecture after completing to grow all epitaxial layers and preceding working procedure Schematic cross-section；

Figure 18 is that the embodiment of the present invention 1 cross section of device architecture after completing preceding working procedure and later process shows It is intended to；

Figure 19 is to expose oxide layer in the embodiment of the present invention 2 silicon chip surface of non-grown epitaxial layer is injected P Type adulterant (P+ district 14) schematic diagram；

Figure 20 is, in the embodiment of the present invention 2, silicon chip surface second time is injected P+ district 14 schematic diagram；

Figure 21 be in the embodiment of the present invention 2 silicon chip complete second time P+ district 14 inject cleaned schematic surface；

Figure 22 is that the embodiment of the present invention 2 completes to grow N-type buffering epitaxial layer 10 and a low-mix at silicon chip surface Miscellaneous N-type epitaxy layer 9；

Figure 23 is the embodiment of the present invention 2 device structure transversal after completing preceding working procedure and later process Face schematic diagram；

Figure 24 is that the embodiment of the present invention 3 completes to grow N-type buffering epitaxial layer 10 and a low-mix at silicon chip surface Miscellaneous N-type epitaxy layer 9；

Figure 25 is the cross sectional representation of device structure after the embodiment of the present invention 3 procedure in the completed；

Figure 26 is the cross section signal of another device structure after the embodiment of the present invention 3 procedure in the completed Figure.

Reference marks table:

1 passivation layer

2 aluminium alloy layers

3 inter-level dielectrics

4 highly doped polysilicons

5 N-type source regions

The p-type high-doped zone of 6 contact hole channel bottoms

7 p-type bases

The N-type region of 8 trench bottom

9 N-type bases

10 N-type cushions

11 complete the P+ substrate after wear down operation

12 substrates (can be N-type, it is also possible to be p-type)

13 are used as to stop the surface oxide layer of ion implanting

The P+ type district that 14 are connected with back metal

The surface thin oxide layer of protection silicon face it is used as during 15 ion implanting

16 near the low-doped p type island region of back metal

17 grooves dug at substrate surface

The N+ type district that 18 are connected with back metal

20 backplates

Near 100 epitaxial layers and substrate intersection

Epitaxial layer on 101 silicon faces

Detailed description of the invention

Embodiment 1:

The manufacturing process of whole power device chip can be divided into grown epitaxial layer, preceding working procedure and later process, front Procedure is the active area of device and terminal structure manufacture at the front surface of epitaxial silicon chip, and device can be IGBT Or FRRD or MCT or GTO or IGBT and FRRD is integrated on the same chip.Epitaxial silicon chip described here Resistance value regarding manufactured device pressure depending on, be 1200V as pressure, resistance value scope is about 50 Ω .cm To 120 Ω .cm, thickness is the most conventional the most thinning thickness used, about 400um to 720um Thick.After front road technique completes, near silicon chip wear down to epitaxial layer and substrate intersection, then remove grinding and draw The defect risen, then carries out back face metalization and forms backplate, such structure and processing technology Can be avoided and ion implanting is done at the thin slice back side.

As shown in figure 11, first long-pending being used above of silicon chip substrate (substrate can be N-type, it is also possible to be p-type) Form sediment or thermally grown mode forms oxide layer 13 (thickness is 0.3um to 2.0um), accumulation one again in oxide layer Layer photoetching coating, then forms pattern by P+14 mask and exposes the some parts of oxide layer, to P+14 After the oxide layer that mask formation pattern exposes carries out dry corrosion, expose the surface of silicon chip substrate, then dispose Lithography coating.

As shown in figure 12, forming groove 17 by etching, this groove 17 degree of depth is more than 3.0um, and width is 0.4um To 4.0um, extend in silicon substrate.

As shown in figure 13, after formation of the groove, groove is carried out sacrificial oxidation (time be 10 minutes to 100 Minute, temperature is 1000 DEG C to 1200 DEG C), the silicon layer destroyed by plasma in grooving process with elimination, Then all oxide layers are disposed, outside the sidewall that then expose at groove and bottom and silicon chip surface growth P+ Prolong layer.

As shown in figure 14, then it is planarized learning the extension that corrosion treatmentCorrosion Science is removed on substrate surface.

As shown in figure 15, form oxide layer 15 (thickness is 0.02um to 0.05um) by accumulation or thermally grown mode, Afterwards silicon chip surface being reinjected P-type dopant, it is not necessary to mask plate, dosage range is 1 × 10¹²/cm²Extremely 1×10¹⁵/cm², Implantation Energy scope is 20KeV to 2000KeV.

As shown in figure 16, remove all oxide layers in surface cleaned, then grow a N-type buffering epitaxial layer 10 (thick Spending about 1um to 10um, high-dopant concentration is about 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, then growth one is low Doped N-type epitaxial layer 9, low doping concentration and thickness visual organ part pressure depending on, as pressure for 400V device, Then thickness is minimum for about 40um, and concentration is about 1 × 10¹⁴/cm³To 5 × 10¹⁵/cm³。

As shown in figure 17, then by preceding working procedure the surfaced active district of device and terminal structure, such as IGBT device The UMOS unit on surface, manufactures the front surface at epitaxial silicon chip, on the active area of silicon chip front surface is The inter-level dielectric 3 of UMOS unit, metal level 2 (titanium/titanium nitride layer, tungsten and aluminium alloy) and passivation layer 1.

As shown in figure 18, completing the silicon chip wear down of front road technique near the centre in P+ district 14, then remove and grind The defect that mill causes, then carries out back face metalization and forms backplate, such structure and making Technique can be avoided does ion implanting to the thin slice back side.

Embodiment 2:

P+ district 14 prolongs floor at a secondary growth and is formed.

As shown in figure 19, first on low-doped substrate (substrate can be N-type, it is also possible to p-type) silicon chip Accumulation or thermally grown mode is used to form oxide layer 13 (thickness is 0.3um to 2.0um), in oxide layer again Accumulation one layer photoetching coating, then forms pattern by P+ district 14 mask and exposes the some parts of oxide layer, After the oxide layer exposing P+ district 14 mask formation pattern carries out dry corrosion, expose the surface of silicon chip, the most clearly Removing lithography coating, to silicon chip surface implanting p-type adulterant, (dosage is 1 × 10¹⁵/cm²To 2 × 10¹⁶/cm², Implantation Energy scope is 20KeV to 2000KeV).

As shown in figure 20, remove all oxide layers in surface cleaned, then grow a p-type epitaxial layer 16 (thickness About 1um to 10um, high-dopant concentration is about 1 × 10¹⁵/cm³To 1 × 10¹⁸/cm³, then in silicon chip substrate Accumulation is used above or thermally grown mode forms oxide layer 13 (thickness is 0.3um to 2.0um), oxidation Accumulation one layer photoetching coating again on layer, then forms pattern by P+14 mask and exposes some portions of oxide layer Point, after the oxide layer exposing P+14 mask formation pattern carries out dry corrosion, expose the surface of silicon chip substrate, Then disposing lithography coating, then afterwards silicon chip surface is reinjected P-type dopant, dosage range is 1×10¹⁵/cm²To 2 × 10¹⁶/cm², Implantation Energy scope is 20KeV to 2000KeV.

As shown in figure 21, all oxide layers in surface are removed cleaned.

As shown in figure 22, then grow a N-type buffering epitaxial layer 10 (thickness about 1um to 10um, the most highly doped Concentration is about 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, then grow a low-doped n type epitaxial layer 9, low-doped dense Degree and thickness visual organ part pressure depending on, as pressure for 400V device, then thickness is minimum for about 40um, dense Degree is about 1 × 10¹⁴/cm³To 4 × 10¹⁵/cm³。

As shown in figure 23, then by preceding working procedure the active area of device surface and terminal structure manufacture at epitaxial silicon chip Front surface, afterwards completing the silicon chip wear down of front road technique near the centre in district 14, p type island region 16 and P+ Place, then removes and grinds the defect caused, and then carries out back face metalization and forms backplate, such Structure and processing technology can be avoided does ion implanting to the thin slice back side.

Embodiment 3:

P+ district 14 prolongs floor at two secondary growths and is formed.

Step is the most same as in Example 2, and simply ground floor extension can be p-type doping, concentration and p type island region 16 Quite, it is also possible to be n-type doping, concentration range is 1 × 10¹⁴/cm³To 1 × 10¹⁸/cm³。

As shown in figure 24, the step in P+ district 14 is injected as described in Example 2 from beginning to ground floor epitaxial surface (with reference to Figure 21), simply ground floor extension can be p-type doping, and concentration is suitable with p type island region 16, it is possible to To be n-type doping, concentration range is 1 × 10¹⁴/cm³To 1 × 10¹⁸/cm³, complete ground floor epitaxial surface is noted Just all oxide layers in surface are removed cleaned, then growth second layer extension, outside the second layer after entering P+ district 14 Prolonging can be p-type doping, and concentration is suitable with p type island region 16, it is also possible to be n-type doping, and concentration range is 1×10¹⁴/cm³To 1 × 10¹⁸/cm³, then grow a N-type buffering epitaxial layer 10 (thickness about 1um to 10um, High-dopant concentration is about 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, then grow a low-doped n type epitaxial layer 9, Low doping concentration and thickness visual organ part pressure depending on, as pressure for 400V device, then thickness is minimum for 40um Left and right, concentration is about 1 × 10¹⁴/cm³To 4 × 10¹⁵/cm³, the ground floor of Figure 24 and second layer extension be all with As a example by p-type.

As illustrated in figs. 25 and 26, then by preceding working procedure, active area and the terminal structure manufacture of device surface are existed The front surface of epitaxial silicon chip, afterwards completing the silicon chip wear down of front road technique to ground floor p type island region 16 and P+ The lmme alphaiaie (Figure 25) in district 14, it is also possible in the middle of wear down to district 14, second layer p type island region 16 and P+ is Vicinity (Figure 26), then removes and grinds the defect caused, and then carries out back face metalization and forms back side electricity Pole, such structure and processing technology can be avoided does ion implanting to the thin slice back side.

Finally should be not limited to the present invention it is noted that these are only the preferred embodiments of the present invention, The present invention can be used for relating to manufacturing semiconductor power device (such as, insulated trench gate bipolar transistor Trench IGBT or FRRD or MCT or GTO), the summary of the invention of presents and embodiment are to make with N-type passage device Going out explanation, the present invention also can be used for p-type passage device, although having carried out the present invention in detail with reference to embodiment Explanation, for a person skilled in the art, it still can be to the skill described in foregoing embodiments Art scheme is modified, or wherein portion of techniques feature is carried out equivalent, but all the present invention's Within spirit and principle, any modification, equivalent substitution and improvement etc. made, should be included in the present invention's Within protection domain.

Claims

1. manufacture and include front structure and a structure, front structure at epitaxial silicon chip semiconductor-on-insulator power device Being to manufacture on silicon epitaxy layer surface, structure at least includes with lower part:

(1) in a quasiconductor back surface at least independent P+ district 14, width is more than 10um, this P+ district While the formation Ohmic contact that is connected with back metal, another side is N-type relief area 10, and this P+ district mixes Miscellaneous maximum concentration scope is 5 × 10¹⁸/cm³To 1 × 10²⁰/cm³；

(2) near a quasiconductor back surface at least N-type relief area 10, width is more than 10um, this N Type relief area 10 near quasiconductor back surface while there being segment boundary Shi Yu P+ district 14 to be connected, have portion Point border is to be connected with substrate 12, and another side is low concentration doped N-type base 9, this N-type relief area Doping maximum concentration scope is 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³；

(3) quasiconductor back surface has two kinds of different doped regions and back metal contacts, and both is different Doped region be P+ district 14 and substrate 12, wherein P+ district is to fill out extension at low-doped substrate surface digging groove Remove what the epitaxial layer on substrate surface was formed after Ceng again, or via prolonging what layer was formed at growth at least one times, Substrate doping is less than 1 × 10¹⁸/cm³；

The most according to claim 1 at the quasiconductor back surface of part (4), it is characterised in that its formation is complete After becoming device front portion structure, it is ground the silicon substrate back side processing, grinds substrate attached to the centre at P+ district 14 Closely, the defect that grinding causes then is removed.

The most according to claim 1 in the P+ district 14 of part (1), it is characterised in that there is more than one P+14 district, its In the width in an at least P+ district 14 more than 100um.

4. manufacture and include front structure and a structure, front structure at epitaxial silicon chip semiconductor-on-insulator power device Being to manufacture on silicon epitaxy layer surface, structure at least includes with lower part:

(1) in a quasiconductor back surface at least independent P+ district 14, width is more than 10um, this P+ district While the formation Ohmic contact that is connected with back metal, another side is N-type relief area 10, N-type relief area Doping maximum concentration scope is 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, the doping maximum concentration scope in this P+ district is 5×10¹⁸/cm³To 1 × 10²⁰/cm³；

(2) at the p type island region 16 near a quasiconductor back surface at least independent low concentration doping, width More than 10um, the p type island region 16 of this low concentration doping is between P+ doped region, the P of this low concentration doping Type district 16 has while being connected with back metal, and having is N-type relief area 10, the P of this low concentration doping The doping maximum concentration scope in type district 16 is 1 × 10¹⁴/cm³To 1 × 10¹⁸/cm³；

(3) having four kinds of different doped regions near semiconductor back surface, the doped region that these four is different is P+ district 14, the p type island region 16 of low concentration doping, N-type relief area 10 and N-type base 9, wherein N-type buffering District 10 and N-type base 9 are formed during grown epitaxial layer, and wherein district of P+ district 14 is low-doped Substrate surface digging groove removes what the P+ epitaxial layer on substrate surface was formed again after filling out P+ epitaxial layer, or warp Cross and at growth at least one times, prolong what layer was formed；Wherein the p type island region 16 of low concentration doping can be in growth extension Formed during Ceng, can also be formed by ion implanting after completing grinding back surface；

(4) quasiconductor back surface have two kinds of different doped regions be connected with metal layer on back formation the back side Electrode, wherein has two kinds of situations: the first situation is that wherein P+ district 14 and metal level form Ohmic contact and low The p type island region 16 of doped in concentrations profiled forms non-ohmic contact with metal level, the second situation be wherein P+ district 14 with Metal level forms Ohmic contact and low concentration doping substrate 12 forms non-ohmic contact with metal level.

The most according to claim 4 in the P+ district 14 of part (1), it is characterised in that there is more than one P+14 district, its In the width in an at least P+ district 14 more than 100um.

6. manufacture and include front structure and a structure, front structure at epitaxial silicon chip semiconductor-on-insulator power device Being to manufacture on silicon epitaxy layer surface, structure at least includes with lower part:

(1) near a quasiconductor back surface at least independent P+ district 14, width is more than 10um, this P+ District while the formation Ohmic contact that is connected with back metal, and another side is N-type relief area 10, N-type relief area Doping maximum concentration scope be 1 × 10¹⁵/cm³To 5 × 10¹⁸/cm³, the doping maximum concentration scope in this P+ district It is 5 × 10¹⁸/cm³To 1 × 10²⁰/cm³；

(3) having three kinds of different doped regions near semiconductor back surface, the doped region that these three is different is P+ district 14, N+ type district 18 and N-type relief area 10, these three doped region is shape during grown epitaxial layer Become, have several different method can form district 14 of N+ district 18 and P+；

(4) quasiconductor back surface be silicon chip back side wear down to type district of P+ district 14 and N+ at centre attached Closely, it is connected with metal layer on back formation back side electricity at quasiconductor back surface at least two kinds of different doped regions Pole, wherein metal level and type district 18 of P+ district 14 and N+ form Ohmic contact.

The most according to claim 6, several different method that has in part (3) can form N+ district 18 and P+ District 14；It is characterized in that one of which method is that wherein P+ district 14 is at N+ type doped substrate surface digging groove Remove being epitaxially formed on substrate surface after filling out P+ epitaxial layer again, after front road technique completes, silicon chip is carried on the back To P+ district 14, neighbouring just stopping carries out back face metalization to face wear down with the centre in N+ district 18.

The most according to claim 6, several different method that has in part (3) can form N+ district 18 and P+ District 14；It is characterized in that one of which method is that wherein P+ district 14 is at low-doped substrate surface digging groove Remove the extension on substrate surface after filling out P+ epitaxial layer again, afterwards silicon face injected N-type high-dopant concentration, After front road technique completes, just stop near the centre in silicon chip back side wear down to P+ district 14 and N+ district 18 into Row back face metalization.

The most according to claim 6, several different method that has in part (3) can form N+ district 18 and P+ District 14；It is characterized in that one of which method is formed, such as growth regulation via at least growing an epitaxial layer The P+ forming part through mask plate implanting p-type high-dopant concentration and N-type high-dopant concentration is delayed outside one layer District 18 of district 14 and N+, growth second layer extension, is then poured into p-type high-dopant concentration and N-type is highly doped afterwards Concentration forms the district 18 of P+ district 14 and N+ of part, the district of P+ district 14 and N+ 18 formed afterwards and shape before Cheng P+ district 14 is connected with N+ district 18, forms a district 18 of continuous print P+ district 14 and N+, and front road technique is complete Cheng Hou, carries out back metal just stopping near the silicon chip back side wear down to P+ district 14 centre with N+ district 18 Change.

The most according to claim 6, several different method that has in part (3) can form N+ district 18 and P+ District 14；It is characterized in that one of which method is formed, such as growth regulation via at least growing an epitaxial layer The P+ forming part through mask plate implanting p-type high-dopant concentration and N-type high-dopant concentration is delayed outside one layer District 18 of district 14 and N+, afterwards growth second layer extension, be then poured into p-type high-dopant concentration and form part P+ district 14, the P+ district 14 formed afterwards is connected with the P+ district 14 formed before, forms a continuous print P+ district 14, after front road technique completes, just stop near the silicon chip back side wear down to P+ district 14 centre with N+ district 18 Carry out back face metalization.

11. according to claim 6 in the P+ district 14 of part (1), it is characterised in that have more than one P+14 district, The width at least one of which P+ district 14 is more than 100um.