CN105895525A

CN105895525A - Technological method for preparing back doped regions of semiconductor device

Info

Publication number: CN105895525A
Application number: CN201410571084.4A
Authority: CN
Inventors: 苏冠创
Original assignee: Nanjing Lisheng Semiconductor Technology Co Ltd
Current assignee: Nanjing Lisheng Semiconductor Technology Co Ltd
Priority date: 2014-10-21
Filing date: 2014-10-21
Publication date: 2016-08-24

Abstract

The invention discloses a technological method for preparing back doped regions of a semiconductor device. The technological method for preparation is characterized in that through combination of the doping concentration of an FZ silicon wafer, the thickness of a mask plate, characteristic patterns of holes in the mask plate, different ion implantation directions, wherein the implantation directions are deviation to the left, deviation to the right or the center, different implantation angles, wherein the implantation angles are greater than 10 degrees or less than 10 degrees, different implantation doses, energy, types, annealing conditions and the like, more than two types of doped regions can be prepared at the back of the thinned silicon wafer so as to be contacted with back metal.

Description

A kind of process preparing semiconductor devices back side doped region

Technical field:

The present invention relates to a kind of process preparing back of semiconductor power device doped region, more specifically The process of doped region is prepared at the back side relating to a kind of semi-conductor silicon chip after wear down.

Background technology:

1980, RCA Corp. of the U.S. applied for first IGBT patent, and within 1985, Toshiba Corp makes First industrial IGBT.From device physically for, it is non-transparent collector punch IGBT, referred to as punch IGBT (Punchthrough IGBT-is abbreviated as PT-IGBT).PT-IGBT It is to manufacture on epitaxial silicon chip, the extension of growth thickness thickness what 110um, technically have any problem, Er Qiecheng This can drastically increase, so, PT-IGBT be typically only applicable to pressure for 400V to 1200V in the range of.If Manufacture pressure for 1700V or 2500V or 3300V or more than, in early days all use non-punch through IGBT (Non-punchthrough IGBT, be abbreviated as NPT-IGBT), device is fabricated directly in thickness to be had hundreds of micro- In the FZ N-type silicon chip of rice, p type island region or the p-type/N-type region of device collector junction are formed by ion implanting. Owing to the doping of collector junction is formed by ion implanting, the dosage of injection can arbitrarily control, if the p-type injected is mixed Miscellaneous dosage is high, then can form general high hole injection efficiency collector junction (i.e. strong colelctor electrode)；If the P injected Type dopant dose is little, then hole injection efficiency is low, and electronics can effectively flow through p type island region via diffusion To metal contact position, this kind of collector junction is referred to as weak collector junction or transparent collector junction (or referred to as transparent collector). During 94 and 95 years, weak collector junction was once used for NPT-IGBT and GTO, if weak collector junction method is used Manufacture 600V or 1200V IGBT, then the collector junction of IGBT needs to make at only about 60um or about 120um On the thick FZ N-type silicon chip back side, during 94 and 95 years, industrial quarters does not also have this ultra thin silicon wafers technique Ability.

In 1996, motorola inc delivered an article and has described the research about manufacturing non-break-through IGBT, Stressing how to manufacture in thin silicon wafer the technique of colelctor electrode, the thinnest of FZ N-type silicon chip used there are about 170um Thick.In next year, the FZ N-type silicon chip that Infineon company has also delivered with 100um is thick makes 600V's NPT-IGBT.About 99 years, the IGBT of industrial a new generation started to go into operation, and the IGBT of this new generation is A kind of high-speed switching devices, its voltage reduces to positive temperature coefficient, and it need not subtract with heavy metal or irradiation Minority carrier life time in short device, it is (or the most transparent plus weak collector junction that main technology is ultra thin silicon wafers technique Collector junction).Infineon company is referred to as field cut-off IGBT, the following years, each main production IGBT Company all release one after another similar product.From that time, IGBT has obtained qualitative leap on electric property, Quickly grow and dominated the market of medium power range.

Along with the development of power device IGBT technology, the switching speed of IGBT is increasingly faster, in application system, The IGBT with high-speed switch needs to ask the diode (FRD) using fast quick-recovery as fly-wheel diode. Switching device IGBT is each time from opening to turn off process, and fly-wheel diode can be become cutting from conducting state Only state.And this is crossed range request diode and has the softest recovery characteristics.In application process, it is desirable to be The power consumption of system is little, and the electromagnetic noise that reliability is high and less, IGBT and FRD is had high requirements, so by this And, in a very long time, industry ignores the exploitation of fast diode, because the performance of FRD is not with On, becoming the usefulness limiting whole system, the performance of right IGBT is fine, also cannot bring into play, quick two The effect of pole pipe receives the attention of height.Since two thousand, the work of IGBT is made by thin silicon wafer technique Skill quickly grows, the maturation made along with thin silicon wafer IGBT, and naturally corresponding technology is also used to make soon Quick-recovery diode (FRD).

In early days thin silicon wafer technique mainly write power in how wear down silicon chip, how how to process the back of the body after grinding The back side of silicon chip after wear down is done ion implanting and how to do the technologic problem of annealing etc., in early days field cut-off The structure of IGBT is fairly simple as shown in Figure 1.With thin slice technique make FRD then as in figure 2 it is shown, this A little structure are all only a kind of doped regions such as 11 or 13 and back metal contacts, the doped region at this back side It is that the back side of the silicon chip towards wear down of land used batt is made ion implanting and formed, during injection, is without covering Film version.

In about 2010, the notice of technique started to turn to and how to make in more complicated back side doped region structure, The 5th generation IGBT flown such as English and eighth generation IGBT of American I R company, the structure of these devices is So simple through unlike before, only a kind of doped region and back metal contacts.Such as the RC-IGBT in Fig. 3, There are P+ that doping content is high and the high N+ the two region of doping content and back metal contacts, the FRD of Fig. 4 There are highly doped N+ district and low-doped N district and back metal contacts.This have two kinds of doped regions to contact with metal Technique relatively before complexity, but still simple at last, easy what produces, and these devices are than only there being a kind of doped region There is more preferable electric property with the device of back metal contacts, but still can optimize further.

The technique manufacturing 400V to 1200V FRD by FZ N-type silicon chip, is broadly divided into two large divisions, Ji Qian road Operation and later process.Preceding working procedure is mainly made the front structure of device on the surface of FZ N-type silicon chip On.Preceding working procedure complete after just FZ silicon chip wear down to desired thickness, as pressure for 1200V, then required thick Degree is about about 120um.Subsequently into later process, later process needs inject overleaf and mix accordingly The miscellaneous dose of doped region formed needed for the back side, if a kind of doped region in the back side and back metal contacts, note Fashionable, be without mask plate, more than one doped region just need mask plate.

When device is backed with more than one doped region and back metal contacts, and it is the most singly blanket type that backside particulate injects , need similar photoetching process that dopant ion is injected into pattern image part, this time is general Photoetching process is met difficulty, and has metal because completing on the silicon chip surface of preceding working procedure, and some completes wear down Silicon chip after technique is the thinnest, it is not easy to carry out the process of general photoetching process, at this moment will be dopant ion It is injected into the pattern image part of silicon chip back side and has two kinds of methods:

(1) employing is bonded with method for bonding and separating temporarily: this method is to be bonded one before silicon chip with carrier Rising, silicon chip back side just can carry out general photoetching and ion implantation technology afterwards, and dopant ion is injected into The pattern image part of silicon chip back side, after completing required step, just uses bonding partition method silicon chip nondestructively Being detached from the carrier out, this technique is prepared more complicated, is unfavorable for cost and manufacture.

(2) thin slice mask is used: with the perforate of pattern image part on thin slice mask, this method is handle Silicon chip needs the one side of ion implanting to be placed on above the thin slice mask space of a whole page, just can carry out silicon chip after fixing Ion implanting, does not has the part of perforate not to be injected on the thin slice mask space of a whole page, has the part of perforate, doping Agent can be injected on silicon chip surface formed needed for mix region, this technique relatively before simple cheap, easy what produce. The method using the preparation of thin slice mask plate to be backed with two kinds of doped regions is: one of which adulterant land used batt The back side of the silicon chip towards wear down inject, without mask, another kind of doping is to note through mask Entering, the doping content injected with mask is higher than what ground batt was injected, just can form two at back surface after activation The region of kind of different levels of doping, cannot prepare in this way as shown in Figure 5 have three kinds of differences overleaf The region of doping content contacts with back metal, and this shortcoming is to be improved.

Summary of the invention:

Field cut-off IGBT, RC-IGBT or the FRD that the above is said, the structure of its back side doped region is to device Performance is the most crucial, it is an object of the invention to propose a kind of more optimization and the one of practical to wear down Technique and the method for ion implanting is made at the back side of rear semiconductor wafer, the present invention with before the most significantly different it Place is that the present invention can be used to preparation and contacts with back metal more than the region of two kinds of different levels of doping.This Relative position and the concentration in the region of a little different levels of doping are to pass through the doping content of FZ silicon chip own, cover The thickness of film version, the pattern image of perforate on mask plate, the injection direction of ion implanting, injector angle, injects Dosage, energy, kind and annealing conditions etc. determine, repeatable and can simply implement, and are suitable for The devices such as what produces, and this preparation method can be used for preparing field cut-off IGBT, RC-IGBT and FRD, MCT and GTO.

The material of foregoing thin slice mask plate can be silicon wafer, and outer surface can have one silica layer, The thickness of mask plate is between 100um to 400um, and wherein pattern image perforation lithographic method is formed, Lithographic method therein can be dry etching or wet etching or wet-dry change mixing etching, wherein etching depth It is between 100um to 400um, does not then at least have the thickness of etching to grind off another side with Ginding process, After make the hole etched can pass entirely through full wafer silicon wafer.

Above thin slice mask plate is used as differential annealing, one side to be annealed is placed on mask plate, so Being radiated on mask plate with laser or other illuminaton thermal source afterwards, laser or other thermal source irradiated can be through figures Shape is bored a hole, and the thermal source passed can play annealing effect at its position passed, not have the position base of thermal source break-through Do not anneal in basis generation.

Accompanying drawing explanation

Accompanying drawing is used for providing a further understanding of the present invention, is used for explaining this together with embodiments of the present invention Invention, is not intended that limitation of the present invention, in the accompanying drawings:

Fig. 1 is the cross-sectional structure schematic diagram of general field cut-off IGBT device；

Fig. 2 is the cross-sectional structure schematic diagram of the FRD typically manufactured by thin silicon wafer technique；

Fig. 3 is the cross-sectional structure schematic diagram having two kinds of doped regions with the RC-IGBT of back metal contacts；

Fig. 4 is the cross-sectional structure schematic diagram having two kinds of doped regions with the FRD of back metal contacts；

Fig. 5 is the cross-sectional structure schematic diagram having three kinds of doped regions with the device of back metal contacts；

Fig. 6 is the schematic diagram that can form different doped region with same mask plate but different injector angle；

Fig. 7 is the surface texture schematic diagram forming power device of the embodiment of the present invention 1；

Fig. 8 be the embodiment of the present invention 1 complete schematic diagram after grinding step；

Fig. 9 is that the back surface to silicon chip 200 of the embodiment of the present invention 1 is to inject boron doping ion schematic diagram；

Figure 10 is that the back surface to silicon chip of embodiment 1 injects hydrogen doping agent schematic diagram；

Figure 11 is that the back surface to silicon chip of embodiment 1 injects P31 doping ion schematic diagram through mask plate；

Figure 12 be embodiment 1 the back surface to silicon chip through the same mask plate of back inject boron doping from Sub-schematic diagram；

Figure 13 is that the embodiment of the present invention 1 completes the cross-sectional structure schematic diagram of device after backplate 14.

Reference symbol table:

1 passivation layer

2 aluminium alloy layers

3 inter-level dielectrics

4 highly doped polysilicons

5 N-type source regions

The p-type high-doped zone of 6 contact hole channel bottoms

7 p-type bases

The N-type region of 8 trench bottom

9 N-type bases

10 N-type cushions

11 near the p type island region of back metal

12 near the P+ type district of back metal

13 near the N+ type district of back metal

14 backplates

100 originally thinning before substrate

200 complete the substrate after wear down operation

Detailed description of the invention

Below in conjunction with accompanying drawing, the preferred embodiments of the present invention are illustrated, it will be appreciated that described herein Preferred embodiment is merely to illustrate and explains the present invention, is not intended to limit the present invention.Of the present invention it is The technique of a kind of back surface of semiconductor wafer doped region being used for after preparing wear down and method, the method bag that it is prepared Include herein below step: the general thickness of thin slice mask plate is about from 50um to 1000um, if thin slice is Silicon chip, then thickness can be between 100um to 400um, and the width in the hole on thin slice is generally higher than 30um, The thickness assuming mask plate is 300um, has three kinds of aperture widths, for 260um, 160um and 60um, if mixing Miscellaneous dose of kind I is injected from the left side, implant angle be 15 degree (set vertical with mask version plane as 0 degree), Dopant species II is injected from the right, and implant angle is 15 degree, and dopant species III is from direction, center note Entering, the ratio of the adulterant relative concentration of injection is: kind I compares equal to 1 to 1 than kind III than kind II 0.1, it is assumed that respective Implantation Energy is to make each doped region have roughly the same junction depth, then can obtain the different back side Can Ji district is as shown in Figure 6.

Embodiment 1:

As it is shown in fig. 7, the manufacturing process of the chip of whole power device can be divided into preceding working procedure and later process, front Procedure is the surface cell of device, if the UMOS unit making on IGBT device surface is before silicon chip 100 Surface, is the inter-level dielectric 3 of UMOS unit on the front surface of silicon chip, metal level 2 (titanium/titanium nitride layer, Tungsten and aluminium alloy) and passivation layer 1.The device manufactured on silicon chip 100 surface can also be MCT or GTO, Silicon chip described here is FZ N-type silicon chip, or CZ N-type silicon chip, and resistance value regards the resistance to of manufactured device Depending on pressure, being 1200V as pressure, resistance value scope is about 50 Ω .cm to 120 Ω .cm, and thickness is the most not The conventional thickness used before thinning, about 400um to 720um is thick.

As shown in Figure 8, completing silicon chip 100 wear down of front road technique to desired thickness, such as 1200V to be manufactured Resistance to voltage device, then after wear down operation completes, thickness is about 110um, and silicon chip 100 becomes silicon chip 200.

As it is shown in figure 9, the back surface of silicon chip 200 is injected boron dope agent, implant angle is 0 degree to 7 degree scope Between, dosage range is 1 × 10¹³/cm²To 1 × 10¹⁶/cm², Implantation Energy scope is 20KeV to 200KeV, This step is used for being formed the P-type layer 11 of structure.

As shown in Figure 10, the back surface of silicon chip 200 being injected hydrogen doping agent, implant angle is 0 degree, dosage range It is 1 × 10¹²/cm²To 5 × 10¹⁵/cm², Implantation Energy scope is 100KeV to 2MeV, and this step is used for being formed The N-type cushion 10 of structure.

As shown in figure 11, the back surface of silicon chip 200 is injected N type dopant such as P31, injector angle through mask plate Degree is more than 10 degree, and dosage range is 1 × 10¹²/cm²To 1 × 10¹⁶/cm², Implantation Energy scope is 100KeV To 2MeV, this step is used for being formed the N+ type district 13 of Figure 13 structure.

As shown in figure 12, after previous step completes ion implanting, keep mask plate and the relative position before silicon chip, Then the back surface to silicon chip 200 passes through the mask plate injection boron dope agent of previous step, and implant angle is 0 Between 7 degree of scopes, dosage range is 1 × 10¹⁵/cm²To 1 × 10¹⁶/cm², Implantation Energy scope is 20KeV To 200KeV, this step is used for being formed the P+ type district 12 of Figure 13 structure.

As shown in figure 13, it is 300 DEG C to 450 DEG C that silicon chip 200 is placed in temperature range, and anneal 30mins to 100mins, Annealing steps activates the hydrogen injected, boron and P31 adulterant, formation type cushion 10, P-type layer 11, P+ Type district 13 of type district 12 and N+, metallizes silicon chip 200 back surface with sputtering or deposition process afterwards, as The backplate 14 of device, metal layer material can be Al/Ti/Ni/Ag or Ti/Ni/Ag or Al/Ti/Ni/Au Deng, after completing metallization step, the Structure of cross section of device is as shown in figure 13.

It is last it is noted that the parameter implementing this injection used by invention and doping has a lot of combination, at this not Can state the most to the greatest extent, these are only the preferred embodiments of the present invention, be not limited to the present invention, this Bright can be used for relates to manufacturing semiconductor power device (such as, insulated trench gate bipolar transistor Trench IGBT Or MCT or GTO), the summary of the invention of presents and embodiment are to make an explanation with N-type passage device, this Bright also can be used for p-type passage device, although the present invention being described in detail with reference to embodiment, for For those skilled in the art, the technical scheme described in foregoing embodiments still can be repaiied by it Change, or wherein portion of techniques feature carried out equivalent, but all the spirit and principles in the present invention it In, any modification, equivalent substitution and improvement etc. made, should be included within the scope of the present invention.

Claims

1. the process preparing semiconductor devices back side doped region at least includes with lower part:

(1) semiconductor back surface at least three kinds of different doped regions contact with back metal, at least a part of which There are two kinds of doped regions to be formed by ion injection method, and the most at least one is ion permeable mask Version is injected；

(2) thickness of mask plate at least 50um is thick, and mask plate has the pattern image of perforation, perforation The width range of pattern image between 30um to 3000um；

(3) before ion implanting, afterwards or between, annealing steps at least once.

The most according to claim 1, be that ion permeable mask plate injects a kind of of part (1), it is special Levying and be that the incidence angle of this ion implanting is more than 7 degree, incidence angle is defined as injection direction and hangs down mutually with silicon chip plane Nogata to angle, Implantation Energy is from 20KeV to 2.0MeV.

The most according to claim 1 at the mask plate of part (2), it is characterised in that the material of this mask plate is silicon wafer Disk, outer surface can have one silica layer, and the thickness of mask plate is between 100um to 400um, Qi Zhongte Levying patterned perforation lithographic method to be formed, lithographic method therein can be dry etching or wet etching Or wet-dry change mixing etching, wherein etching depth is between 100um to 400um, then uses Ginding process handle Another side does not at least have the thickness of etching to grind off, and finally makes the hole etched can pass entirely through full wafer Silicon Wafer Sheet.

The most according to claim 1, at the mask plate of part (2), its feature is used as local at this mask plate Annealing, is placed on one side to be annealed on mask plate, is then radiated at covers with laser or other illuminaton thermal source In film version, laser or other thermal source irradiated can pass patterned perforation, and the thermal source passed can be in its portion passed Annealing effect is played in position, and annealing occurs not to have the position of thermal source break-through there is no.

Ion implanting the most according to claim 2, it is characterised in that wherein some ion injected can not Through the hole of mask plate, some ion injected can be through the hole on mask plate, for arbitrary break-through Hole, it is impossible to be about (d x tan θ) through the ion dose in this hole and the ratio of the ion dose that can pass: (L-d x tan θ), wherein d is the thickness of mask plate, and θ is incidence angle, and L is to open on mask plate The width of logical perforation, if L is less than (d x tan θ), then can pass at this entirely without ion.