CN108109922A - A kind of method for reducing metal-oxide-semiconductor stress effect - Google Patents
A kind of method for reducing metal-oxide-semiconductor stress effect Download PDFInfo
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- CN108109922A CN108109922A CN201711378886.3A CN201711378886A CN108109922A CN 108109922 A CN108109922 A CN 108109922A CN 201711378886 A CN201711378886 A CN 201711378886A CN 108109922 A CN108109922 A CN 108109922A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 230000000694 effects Effects 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000005516 engineering process Methods 0.000 claims abstract description 38
- 238000002347 injection Methods 0.000 claims abstract description 37
- 239000007924 injection Substances 0.000 claims abstract description 37
- 239000002245 particle Substances 0.000 claims abstract description 28
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 23
- 238000002955 isolation Methods 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 15
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical group [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 7
- 125000004432 carbon atom Chemical group C* 0.000 claims 3
- 238000012545 processing Methods 0.000 abstract description 3
- 239000000243 solution Substances 0.000 abstract description 3
- 150000001721 carbon Chemical group 0.000 description 19
- 150000002500 ions Chemical class 0.000 description 12
- -1 phosphonium ion Chemical class 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 229940085991 phosphate ion Drugs 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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Abstract
The invention discloses a kind of methods for reducing metal-oxide-semiconductor stress effect, belong to the technology of field of semiconductor processing, including：Step S1 prepares area to the source-drain electrode with one first particle and carries out one first injection technology；Step S2 prepares area to the source-drain electrode with one second particle and carries out one second injection technology；Step S3 prepares area to the source-drain electrode with one the 3rd particle and carries out one the 3rd injection technology；Step S4 prepares area to the source-drain electrode and carries out heat treatment process.The advantageous effect of the technical solution is：Invention increases the ion concentrations in the source region or drain region formed after ion implanting, reduce the stress effect in metal-oxide-semiconductor.
Description
Technical field
The present invention relates to a kind of technologies of field of semiconductor processing, are specifically a kind of reduction metal-oxide-semiconductor stress effect
Method.
Background technology
The generation early start of shallow grooved-isolation technique (Shallow Trench Isolation, STI) was in 80 years last century
Generation, but initially there are with high costs, and the problem of being still not perfect and just start quilt until last century Mo in terms of technology
It accepts extensively and quotes.Shallow grooved-isolation technique be different from before technology, it is completely flat a kind of new
Isolation technology, and shallow trench isolation technology avoid completely before processing technology used in high temperature technological problems；And
It can guarantee effective area of the device in active area；It is put down in addition, the surface of silicon substrate and spacer medium is all completely disposed in one
On face；In addition shallow-trench isolation technology also improves the problem of junction capacity is with minimum isolating partition, and more important point is low temperature
Technique also potentially improves board yield, reduces the cost of production, and the above advantage is but also STI isolation technologies become
The essential isolation technology in Deep submicron devi8 field at present.
Shallow-trench isolation technology is that a kind of technique of the isolated area between transistor active area is made in wafer substrate, can be had
Effect ensures that N-type and P-doped zone can thoroughly be separated.Shallow trench isolation technology is in N-type and P-doped zone first by mask definition
Silicon area etch away, be allowed to form a shallow trench, then insert the material of insulation into groove again, presently act as this
The mainly silica of packing material, so as to have the function that insulation.Compared to traditional native oxide isolation technology, shallow trench every
Can be than the breakdown voltage of native oxide isolation technology bigger from technology, and interelectrode leakage current can be reduced.
STI technique is widely used in current metal-oxide-semiconductor because of the advantages that its isolation performance is excellent, and leakage current is small and prepares
In technique.But using STI technique after, stress effect can be generated.Stress effect (i.e. LOD effects) refers to that STI isolation generates not
Sizing or uneven twin shaft compression, it is uneven so as to cause the stress distribution of active area, influence the expansion of active area intermediate ion
It dissipates, and then harmful effect can be generated to every electric property of device.
Improve the common method of LOD effects at present as change wires design, but this method can reduce the integrated level of metal-oxide-semiconductor.
The content of the invention
The present invention proposes a kind of method for reducing metal-oxide-semiconductor stress effect for deficiencies of the prior art.This hair
The bright ion concentration added in the source region formed after ion implanting or drain region, reduces the stress effect in metal-oxide-semiconductor.
The present invention is achieved by the following technical solutions：
The present invention relates to a kind of methods for the stress effect for reducing metal-oxide-semiconductor, provide a substrate, shallow in being formed on the substrate
Groove isolation construction, the fleet plough groove isolation structure separate the substrate to form at least one active area, described have in each
Source region forms gate patterns and prepares area to separate the active area and form source-drain electrode；
It is further comprising the steps of：
Step S1 prepares area to the source-drain electrode with one first particle and carries out one first injection technology；
Step S2 prepares area to the source-drain electrode with one second particle and carries out one second injection technology；
Step S3 prepares area to the source-drain electrode with one the 3rd particle and carries out one the 3rd injection technology；
Step S4 prepares area to the source-drain electrode and carries out heat treatment process.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, in the step S1, the first injection work
The particle injection direction of skill has a predetermined angle with the substrate.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, the predetermined angle is 90 degree.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, in the step S1, first particle is
Carbon atom.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, the Implantation Energy scope of the carbon atom is 10
~50keV.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, the implantation dosage of the carbon atom is 1013/cm2
~1015/cm2。
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, second particle is arsenic ion；And/or
3rd particle is phosphonium ion.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, second particle has one first dosage, institute
The 3rd particle is stated with one second dosage, the ratio of first dosage and second dosage is 20~50.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, first dosage and second dosage
Ratio is 35.
Preferably, the method for the stress effect of the reduction metal-oxide-semiconductor, wherein, in the step S4, the heat treatment process
With a preset temperature, the preset temperature is 1020 degrees Celsius；And/or
The heat treatment process continues a preset time, and the preset time is 16 seconds.
The advantageous effect of above-mentioned technical proposal is：
Invention increases the ion concentrations in the source region or drain region formed after ion implanting, reduce answering in metal-oxide-semiconductor
Stress effect.
Description of the drawings
Fig. 1 is a kind of method flow schematic diagram for reducing metal-oxide-semiconductor stress effect in the preferred embodiment of the present invention；
Fig. 2 is a kind of method carbon atom injection process for reducing metal-oxide-semiconductor stress effect in the preferred embodiment of the present invention
Schematic diagram；
In the preferred embodiment of Fig. 3 present invention, a kind of method arsenic ion injection process for reducing metal-oxide-semiconductor stress effect is shown
It is intended to；
In the preferred embodiment of Fig. 4 present invention, a kind of method phosphonium ion injection process for reducing metal-oxide-semiconductor stress effect is shown
It is intended to；
In the preferred embodiment of Fig. 5 present invention, the ion solubility that the source-drain electrode after heat treatment prepares the section in area is bent
Line comparison diagram；
In the preferred embodiment of Fig. 6 present invention, the source-drain electrode after heat treatment prepares the arsenic ion and phosphorus of the section in area
The solubility curve comparison diagram of ion；
In figure：1 gate patterns, 2 fleet plough groove isolation structures, 3 substrates.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art obtained on the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
It should be noted that in the case where there is no conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
As shown in Figure 1, the present embodiment is related to a kind of method for the stress effect for reducing metal-oxide-semiconductor,
A substrate 3 is provided, in forming fleet plough groove isolation structure 2 on substrate 3, the fleet plough groove isolation structure 2 separates substrate 3
To form at least one active area, gate patterns 1 are formed in each active area to separate active area and form source-drain electrode and prepare area.
Specifically include following steps：
Step S1, as shown in Fig. 2, preparing area to source-drain electrode with one first particle carries out one first injection technology.
In first injection technology, the first particle is carbon atom, i.e., it is former to carry out carbon in the upper surface that source-drain electrode is prepared in area
Son injection.
First injection technology particle injection direction has a predetermined angle with substrate 3, and carbon atom injects source with predetermined angle
Drain electrode is prepared in area.
The predetermined angle of the injection of carbon atom is 90 degree.
The Implantation Energy scope of carbon atom is 10~50keV.
The implantation dosage of carbon atom is 1013/cm2~1015/cm2。
Step S2, as shown in figure 3, preparing area to source-drain electrode with one second particle carries out one second injection technology.
In second injection technology, the second particle is arsenic ion, that is, carries out arsenic ion injection.Arsenic ion is injected into complete
The source-drain electrode injected into carbon atom prepares the surface in area.
For the dosage of arsenic ion injection for the first dosage, i.e. arsenic ion in the second injection technology is injected into source with the first dosage
Drain electrode prepares area.
Step S3, as shown in figure 4, preparing area to source-drain electrode with one the 3rd particle carries out one the 3rd injection technology.
In 3rd injection technology, the 3rd particle is phosphonium ion, that is, carries out phosphonium ion injection.Phosphonium ion is injected into complete
The source-drain electrode injected into arsenic ion is prepared in area.
The implantation dosage of phosphonium ion is the second dosage, i.e., carries out the 3rd injection technology with the second dosage.
The ratio of first dosage and the second dosage is 20~50.
In the present embodiment, the ratio of the first dosage and the second dosage is 35.
Step S4 prepares area to source-drain electrode and carries out heat treatment process.
Heat treatment process has a preset temperature, and preset temperature is 1020 degrees Celsius.
Optionally, heat treatment process continues a preset time, and preset time is 16 seconds.After Overheating Treatment, source-drain electrode system
Further it is processed into source electrode or the drain electrode of metal-oxide-semiconductor in preparation area.Preset temperature and preset time can meet simultaneously.
As shown in figure 5, showing that source-drain electrode prepares the ion concentration of the longitudinal cross-section in area, a curve is without carbon atom
Injection, another is to be injected by carbon atom, and the ion concentration distribution after carbon atom injects is substantially better than without carbon atom
The ion concentration distribution of injection.After the first injection technology carbon atom injection technology, source-drain electrode prepares the doping that area is formed
The scope bigger of profile.
As shown in fig. 6, in a source-drain electrode prepares area's longitudinal profile, after carbon atom injection technology, prepared by source-drain electrode
Arsenic ion concentration and phosphate ion concentration in area increase.
The power of the stress effect in metal-oxide-semiconductor is indicated with the absolute value of Δ, wherein：
VtSaminThreshold voltage when width S a for source-drain electrode preparation area is minimum value；
VtSa=10Threshold voltage when width S a for source-drain electrode preparation area is 10um.
Δ is -0.326 when being injected without carbon atom, and Δ is -0.262 after carbon atom injects, i.e., by carbon atom
The absolute value of Δ reduces 6.4% after injection.
The method of the reduction metal-oxide-semiconductor stress effect of the present invention, compared with prior art：After ion implanting
Ion concentration in the source region of formation or drain region reduces the stress effect in metal-oxide-semiconductor.
The foregoing is merely preferred embodiments of the present invention, not thereby limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent substitution and obviously change obtained scheme, should all include within the scope of the present invention.
Claims (10)
- A kind of 1. method for reducing metal-oxide-semiconductor stress effect, which is characterized in thatA substrate is provided, in forming fleet plough groove isolation structure on the substrate, the fleet plough groove isolation structure separates the substrate To form at least one active area, gate patterns are formed in each active area to separate the active area and form source-drain electrode Prepare area；It is further comprising the steps of：Step S1 prepares area to the source-drain electrode with one first particle and carries out one first injection technology；Step S2 prepares area to the source-drain electrode with one second particle and carries out one second injection technology；Step S3 prepares area to the source-drain electrode with one the 3rd particle and carries out one the 3rd injection technology；Step S4 prepares area to the source-drain electrode and carries out heat treatment process.
- 2. the method according to claim 1 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatIn the step S1, the particle injection direction of first injection technology has a predetermined angle with the substrate.
- 3. the method according to claim 2 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatThe predetermined angle is 90 degree.
- 4. the method according to claim 1 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatIn the step S1, first particle is carbon atom.
- 5. the method according to claim 4 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatThe Implantation Energy scope of the carbon atom is 10~50keV.
- 6. the method according to claim 4 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatThe implantation dosage of the carbon atom is 1013/cm2~1015/cm2。
- 7. the method according to claim 1 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatSecond particle is arsenic ion；And/or3rd particle is phosphonium ion.
- 8. the method according to claim 1 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatSecond particle have one first dosage, the 3rd particle have one second dosage, first dosage with it is described The ratio of second dosage is 20~50.
- 9. the method according to claim 8 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatThe ratio of first dosage and second dosage is 35.
- 10. the method according to claim 1 for reducing metal-oxide-semiconductor stress effect, which is characterized in thatIn the step S4, the heat treatment process has a preset temperature, and the preset temperature is 1020 degrees Celsius；With/ OrThe heat treatment process continues a preset time, and the preset time is 16 seconds.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
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| JPH07226509A (en) * | 1994-02-14 | 1995-08-22 | Sanyo Electric Co Ltd | Semiconductor integrated circuit and manufacture thereof |
| JPH10303418A (en) * | 1997-04-30 | 1998-11-13 | Fujitsu Ltd | Manufacture of semiconductor device |
| US20030030077A1 (en) * | 2001-08-07 | 2003-02-13 | Jung Woo-Chan | Semiconductor device and method for manufacturing the same |
| CN101752253A (en) * | 2008-12-08 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of metal oxide semiconductor (MOS) transistor |
| CN101834137A (en) * | 2009-03-12 | 2010-09-15 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation method for source/drain electrodes |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0499037A (en) * | 1990-08-06 | 1992-03-31 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH07226509A (en) * | 1994-02-14 | 1995-08-22 | Sanyo Electric Co Ltd | Semiconductor integrated circuit and manufacture thereof |
| JPH10303418A (en) * | 1997-04-30 | 1998-11-13 | Fujitsu Ltd | Manufacture of semiconductor device |
| US20030030077A1 (en) * | 2001-08-07 | 2003-02-13 | Jung Woo-Chan | Semiconductor device and method for manufacturing the same |
| CN101752253A (en) * | 2008-12-08 | 2010-06-23 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of metal oxide semiconductor (MOS) transistor |
| CN101834137A (en) * | 2009-03-12 | 2010-09-15 | 中芯国际集成电路制造(上海)有限公司 | Ion implantation method for source/drain electrodes |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109659236A (en) * | 2018-12-17 | 2019-04-19 | 吉林华微电子股份有限公司 | Reduce the process and its VDMOS semiconductor devices of VDMOS recovery time |
| CN109659236B (en) * | 2018-12-17 | 2022-08-09 | 吉林华微电子股份有限公司 | Process method for reducing VDMOS recovery time and VDMOS semiconductor device thereof |
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