CN102420143A - Method for improving HCI (Hot Carrier Injection) effect of high-K gate dielectric NMOS (N-Mental-Oxide-Semiconductor) by adopting gate-last process - Google Patents
Method for improving HCI (Hot Carrier Injection) effect of high-K gate dielectric NMOS (N-Mental-Oxide-Semiconductor) by adopting gate-last process Download PDFInfo
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- CN102420143A CN102420143A CN2011101603106A CN201110160310A CN102420143A CN 102420143 A CN102420143 A CN 102420143A CN 2011101603106 A CN2011101603106 A CN 2011101603106A CN 201110160310 A CN201110160310 A CN 201110160310A CN 102420143 A CN102420143 A CN 102420143A
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Abstract
The invention generally relates to a method for improving the HCI (Hot Carrier Injection) effect of an NMOS (N-Mental-Oxide-Semiconductor) in the field of semiconductor manufacture, in particular to a method for improving the hot carrier effect of a high-K gate dielectric NMOS by adopting a gate-last process. In the processing procedure of the gate-last process, after a dummy gate is formed, fluorine ions are implanted in an NMOS device region through an ion injection process; and a stable chemical bond is formed at the interface by a heat treatment process, so that the performance of the NMOS resisting the HCI effect is effectively improved.
Description
Technical field
The present invention relates generally to the method for a kind of NMOS of the improvement reliability in the field of semiconductor manufacture, more precisely, the present invention relates to a kind of method of improving the high K gate dielectric of back grid technology NMOS hot carrier's effect.
Background technology
For reducing grid leakage current, improve device performance, at present, high K gate dielectric technology has been applied to 45 nanometers with lower node; Yet because the interface of high K gate dielectric and silicon has a large amount of interfacial states, and these interfacial states can form unsettled hydrogen bond with hydrogen in manufacture of semiconductor, cause in the nmos device course of work, producing a large amount of interfacial states, thereby change the MOS device performance; Promptly make the nmos device of high K gate dielectric have very serious hot carrier (Hot Carrier Injection is called for short HCI) effect.
Hot carrier (Hot Carrier Injection is called for short HCI) effect is promptly on nmos device; When the characteristic size of device is very little,, also can produce very strong electric field even under not really high voltage; Thereby be easy to cause occurring hot carrier, therefore, in small size device and large scale integrated circuit; Hot carrier appears easily, because some influences that hot carrier caused just are called hot carrier's effect.Hot carrier's effect is to cause device and integrated circuit to produce the major reason that lost efficacy, so pay particular attention to and prevent.
Current; Industry is to improve the HCI effect of nmos pass transistor, adopts lightly doped drain to inject the optimization method that (Lightly Doped Drain is called for short LDD) ion injects usually; Utilization reduces the dosage and increase LDD injection energy that the LDD ion injects; Obtain darker LDD knot, reduce transverse electric field intensity, thereby improve the HCI effect.But increase the LDD ion implantation energy, along with the increasing of junction depth, the length of effective channel of device also will reduce, and will increase short-channel effect (Short Channel Effect is called for short SCE) like this, cause the decline of device DC characteristic.Therefore, merely to improve the HCI effect be not enough through changing dosage that the LDD ion injects and energy.
Summary of the invention
In view of the above problems, the invention provides a kind of method of improving the high K gate dielectric of back grid technology NMOS device HCI effect, wherein, may further comprise the steps:
Deposit first dielectric layer and polysilicon layer successively on a substrate, said first dielectric layer of etching and said polysilicon layer form the sample grid of the first kind semiconductor device and the second based semiconductor device respectively;
Inject fluorine ion in said first kind semiconductor device sample gate region; And fluorine ion is got in first dielectric layer in the said first kind semiconductor device sample grid, and form first kind semiconductor device and second based semiconductor device drain-source district separately through heat treatment;
Deposit second dielectric layer covers first, second device and sample grid separately, behind the sample grid of said second dielectric layer of cmp and said first and second based semiconductor device, eat-backs said sample grid and forms the sample grid recess;
Selective etch the first metal layer behind deposition the first metal layer on second dielectric layer; On second dielectric layer on the first kind semiconductor device, to keep the first metal layer at least; And the bottom and the sidewall of first kind semiconductor sample grid recess are coated with the part the first metal layer; Afterwards on second dielectric layer deposition second metal level after selective etch second metal level; On second dielectric layer on the second based semiconductor device, keeping second metal level at least, and the bottom of the second based semiconductor sample grid recess and sidewall are coated with part second metal level;
Deposit the 3rd metal level covers on the first metal layer, second metal; And part the 3rd metal level is filled in the bottom and sidewall is coated with in the first kind semiconductor sample grid recess of the first metal layer; And part the 3rd metal level is filled in the bottom and sidewall is coated with in the second based semiconductor sample grid recess of second metal level, afterwards unnecessary the first metal layer, second metal level, the 3rd metal level is carried out cmp.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement, wherein, said fluorine ion adopts ion implantation technology to carry out the fluorine ion injection.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement wherein, after said polysilicon gate forms, carries out carrying out said fluorine ion injection technology before the drain-source utmost point ion injection Technology for Heating Processing.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement, wherein, the injection energy range of said fluorine ion is 1KeV to 20KeV.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement, wherein, said fluorine ion implantation dosage scope is 1E14/cm
2To 3 E15/cm
2
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement, wherein, said substrate is provided with an isolation channel, and said isolation channel both sides are respectively P substrate and N substrate.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement; Wherein, Said the first metal layer of said selective etch and said second metal; Both kept in said the first metal layer to the said first kind semiconductor sample grid recess, in said second metal level to the said second based semiconductor sample grid recess.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement, wherein, said first kind semiconductor device is the NMOS reliability, the said second based semiconductor device is PMOS.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement, wherein, said first and second dielectric layer is a high dielectric constant material.
The high K gate dielectric of grid technology NMOS HCI method after the above-mentioned improvement, wherein, said injection fluorine ion shelters from the said second based semiconductor device sample gate region when said first kind semiconductor device sample gate region.
The present invention proposes the high K gate dielectric of a kind of improvement back grid technology NMOS HCI method; Through in the grid technology processing procedure of back; After the sample grid form, inject fluorine ion in the nmos device zone, through Technology for Heating Processing through ion implantation technology; Form stable chemical bond at the interface, effectively improving the performance of the anti-HCI effect of nmos device.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after the accompanying drawing, of the present invention these are incited somebody to action obvious with otherwise advantage undoubtedly.
Description of drawings
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.Yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1 a-g is that the present invention improves the high K gate dielectric of back grid technology NMOS HCI method flow sketch map;
Fig. 2 is the sketch map after intermediate ion injection technology of the present invention is injected fluorine ion and Technology for Heating Processing.
Embodiment
Shown in Fig. 1 a-g, the high K gate dielectric of a kind of improvement back grid technology of the present invention NMOS HCI method wherein, may further comprise the steps:
Deposit first dielectric layer 102 and polysilicon layer 103 successively on substrate 1, wherein, substrate 1 is provided with isolation channel 101, and its both sides are respectively P type substrate 11 and N type substrate 12; Adopt photoetching and etching technics, the etch polysilicon layer 102 and first dielectric layer 103 form NMOS semiconductor device sample grid 104 and PMOS semiconductor device sample grid 105, and wherein, NMOS semiconductor device sample grid 104 are by first dielectric layer 102
1With polysilicon layer 103
1Constitute, PMOS semiconductor device sample grid 105 are by first dielectric layer 102
2With polysilicon layer 103
2Constitute; Adopt the drain-source district of ion implantation technology 106 on P type substrate 11 to inject fluorine ion, wherein, the injection energy range of above-mentioned fluorine ion is between 1KeV to 20KeV, and the implantation dosage scope is 1E14/cm
2To 3 E15/cm
2, and then carry out the Technology for Heating Processing of source-drain area, enter into high-K gate first dielectric layer 102 with the fluorine ion that drives above-mentioned injection
1To form stable chemical bond.
Deposit second dielectric layer 107; Cover NMOS semiconductor device sample grid 104 and PMOS semiconductor device sample grid 104; And adopt the mechanochemistry grinding technics, and grind second dielectric layer 107, NMOS semiconductor device sample grid 104 and PMOS semiconductor device sample grid 105, make polysilicon layer 103
1Upper surface, polysilicon layer 103
2The upper surface of upper surface and second dielectric layer 107 on same horizontal plane, wherein, second dielectric layer 107 is interlayer dielectric layer (interlayer dielectric is called for short ILD); Eat-back polysilicon layer 103
1, polysilicon layer 103
2Form NMOS semiconductor device sample grid recess 110 and PMOS semiconductor device sample grid recess 111 respectively; Deposit the first metal layer 108 is on NMOS semiconductor device sample grid recess 110; Shelter from N substrate part simultaneously; Deposit second metal level 109 shelters from P substrate part simultaneously on PMOS semiconductor device sample grid recess 111; The etching the first metal layer 108 and second metal level 109 keep on the first metal layer 108 to the NMOS semiconductor device sample grid recess 110, form groove metal level 108
1, keep on second metal level, 109 to the PMOS semiconductor device sample grid recess 111, form groove second metal level 109
1
Deposit the 3rd metal level etching and carry out chemical mechanical milling tech after; Formation is full of NMOS the 3rd metal level 112 of NMOS semiconductor device sample grid recess 110; And be full of PMOS the 3rd metal level 113 of PMOS semiconductor device sample grid recess 111; Continue the preparation technology of semiconductor device, finally form nmos device 2 and PMOS device 3.
Wherein, first dielectric layer 102 and second dielectric layer 107 are high dielectric constant material.
Further, adopt ion implantation technology 6 to inject fluorine ion in nmos device sample gate region, promptly fluorine ion is injected in the drain-source district on the P type substrate 11, shelters from the drain-source district on the N type substrate 12 simultaneously.
Referring to shown in Figure 2; In back grid technology (gate-last), after sample grid (dummy gate) form, inject fluorine ion through ion implantation technology; Utilize follow-up source-drain area Technology for Heating Processing to make fluorine ion enter into the high-K gate dielectric layer, fluorine ion is at HfO
2With SiO
2Interface, SiO
2With Si all form Hf-F and Si-F key at the interface because Hf-F and Si-F bond energy will be higher than Hf-H and Si-H bond energy, in nmos device work, be not easy to produce interfacial state, thereby improved the hot carrier injection effect of nmos pass transistor.
The present invention proposes the high K gate dielectric of a kind of improvement back grid technology NMOS HCI method; Through in the grid technology processing procedure of back; After polysilicon gate forms, promptly in grid, inject fluorine ion, through Technology for Heating Processing through ion implantation technology; Form stable chemical bond at the interface, effectively improving the performance of the anti-HCI effect of nmos device.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, based on the present invention's spirit, also can do other conversion.Although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as.Any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (10)
1. the high K gate dielectric of grid technology NMOS HCI method after the improvement is characterized in that, may further comprise the steps:
Deposit first dielectric layer and polysilicon layer successively on a substrate, said first dielectric layer of etching and said polysilicon layer form the sample grid of the first kind semiconductor device and the second based semiconductor device respectively;
Inject fluorine ion in said first kind semiconductor device sample gate region; And fluorine ion is got in first dielectric layer in the said first kind semiconductor device sample grid, and form first kind semiconductor device and second based semiconductor device drain-source district separately through heat treatment;
Deposit second dielectric layer covers first, second device and sample grid separately, behind the sample grid of said second dielectric layer of cmp and said first and second based semiconductor device, eat-backs said sample grid and forms the sample grid recess;
Selective etch the first metal layer behind deposition the first metal layer on second dielectric layer; On second dielectric layer on the first kind semiconductor device, to keep the first metal layer at least; And the bottom and the sidewall of first kind semiconductor sample grid recess are coated with the part the first metal layer; Afterwards on second dielectric layer deposition second metal level after selective etch second metal level; On second dielectric layer on the second based semiconductor device, keeping second metal level at least, and the bottom of the second based semiconductor sample grid recess and sidewall are coated with part second metal level;
Deposit the 3rd metal level covers on the first metal layer, second metal; And part the 3rd metal level is filled in the bottom and sidewall is coated with in the first kind semiconductor sample grid recess of the first metal layer; And part the 3rd metal level is filled in the bottom and sidewall is coated with in the second based semiconductor sample grid recess of second metal level, afterwards unnecessary the first metal layer, second metal, the 3rd metal level is carried out cmp.
2. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method is characterized in that said fluorine ion adopts ion implantation technology to carry out the fluorine ion injection.
3. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method is characterized in that, after said polysilicon gate forms, carries out carrying out said fluorine ion injection technology before the drain-source utmost point ion injection Technology for Heating Processing.
4. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method is characterized in that the injection energy range of said fluorine ion is 1KeV to 20KeV.
5. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method is characterized in that said fluorine ion implantation dosage scope is 1E14/cm
2To 3 E15/cm
2
6. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method is characterized in that said substrate is provided with an isolation channel, and said isolation channel both sides are respectively P substrate and N substrate.
7. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method; It is characterized in that; Said the first metal layer of said selective etch and said second metal; Both kept in said the first metal layer to the said first kind semiconductor sample grid recess, in said second metal level to the said second based semiconductor sample grid recess.
8. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method is characterized in that said first kind semiconductor device is the NMOS reliability, and the said second based semiconductor device is PMOS.
9. the high K gate dielectric of improvement back grid technology as claimed in claim 1 NMOS HCI method is characterized in that said first and second dielectric layer is a high dielectric constant material.
10. the high K gate dielectric of improvement as claimed in claim 1 back grid technology NMOS HCI method is characterized in that, said injection fluorine ion shelters from the said second based semiconductor device sample gate region when said first kind semiconductor device sample gate region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011101603106A CN102420143A (en) | 2011-06-15 | 2011-06-15 | Method for improving HCI (Hot Carrier Injection) effect of high-K gate dielectric NMOS (N-Mental-Oxide-Semiconductor) by adopting gate-last process |
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|---|---|---|---|
| CN2011101603106A CN102420143A (en) | 2011-06-15 | 2011-06-15 | Method for improving HCI (Hot Carrier Injection) effect of high-K gate dielectric NMOS (N-Mental-Oxide-Semiconductor) by adopting gate-last process |
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| CN2011101603106A Pending CN102420143A (en) | 2011-06-15 | 2011-06-15 | Method for improving HCI (Hot Carrier Injection) effect of high-K gate dielectric NMOS (N-Mental-Oxide-Semiconductor) by adopting gate-last process |
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Cited By (3)
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| CN103390559A (en) * | 2012-05-09 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN108630521A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN110444472A (en) * | 2019-08-27 | 2019-11-12 | 上海华力集成电路制造有限公司 | Si base Mosfet device and preparation method thereof |
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| US20050136579A1 (en) * | 2003-12-22 | 2005-06-23 | Texas Instruments, Incorporated | Method for manufacturing a metal oxide transistor having reduced 1/f noise |
| CN101677087A (en) * | 2008-09-12 | 2010-03-24 | 台湾积体电路制造股份有限公司 | Method of fabricating a semiconductor device |
| CN101685800A (en) * | 2008-09-26 | 2010-03-31 | 台湾积体电路制造股份有限公司 | Method of fabricating a semiconductor device |
| CN102054700A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing PMOS (P-channel metal oxide semiconductor) transistor |
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| US20050136579A1 (en) * | 2003-12-22 | 2005-06-23 | Texas Instruments, Incorporated | Method for manufacturing a metal oxide transistor having reduced 1/f noise |
| CN101677087A (en) * | 2008-09-12 | 2010-03-24 | 台湾积体电路制造股份有限公司 | Method of fabricating a semiconductor device |
| CN101685800A (en) * | 2008-09-26 | 2010-03-31 | 台湾积体电路制造股份有限公司 | Method of fabricating a semiconductor device |
| CN102054700A (en) * | 2009-11-10 | 2011-05-11 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing PMOS (P-channel metal oxide semiconductor) transistor |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103390559A (en) * | 2012-05-09 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN103390559B (en) * | 2012-05-09 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN108630521A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN108630521B (en) * | 2017-03-17 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN110444472A (en) * | 2019-08-27 | 2019-11-12 | 上海华力集成电路制造有限公司 | Si base Mosfet device and preparation method thereof |
| CN110444472B (en) * | 2019-08-27 | 2021-10-15 | 上海华力集成电路制造有限公司 | Si-based Mosfet device and preparation method thereof |
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Application publication date: 20120418 |