CN103943502B - Fin formula field effect transistor and forming method thereof - Google Patents
Fin formula field effect transistor and forming method thereof Download PDFInfo
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- CN103943502B CN103943502B CN201310024103.7A CN201310024103A CN103943502B CN 103943502 B CN103943502 B CN 103943502B CN 201310024103 A CN201310024103 A CN 201310024103A CN 103943502 B CN103943502 B CN 103943502B
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- 238000002347 injection Methods 0.000 claims description 15
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- 229910052732 germanium Inorganic materials 0.000 claims description 5
- 229910004129 HfSiO Inorganic materials 0.000 claims description 4
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- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of fin formula field effect transistor and forming method thereof, wherein the forming method of the fin formula field effect transistor includes：Semiconductor substrate is provided, the Semiconductor substrate has first area and second area, has raised fin, the grid structure on the fin in the first area and second area；The first side wall is formed in the grid structure both sides of the first area, the part fin of the first side wall covering forms the first negative covering area；The second side wall is formed in the grid structure both sides of the second area, the width of second side wall is less than the width of first side wall, and the part fin of the second side wall covering forms the second negative covering area；Ion implanting is carried out to the fin of the first area and the grid structure both sides of second area, forms source region and drain region.The forming method of the fin formula field effect transistor of the present invention can form the fin formula field effect transistor with different threshold voltages, and technique is simple.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of fin formula field effect transistor and forming method thereof.
Background technology
With the progress of integrated circuit processing technique so that the integrated level more and more higher of chip, scale is also increasing, but
The power consumption of chip also increases therewith.Core logic transistor region and input/output are normally comprised on one single chip（I/O）It is brilliant
Body area under control domain, the threshold voltage of core logic transistor is relatively low to reduce system power dissipation, and the threshold value of input/output transistors is electric
The pressure higher driving force and breakdown voltage higher with guarantee.Therefore, how different threshold voltages are obtained on a single chip
Transistor becomes the emphasis of research.
Fig. 1 is refer to, is the structural representation of the MOS transistor of prior art, including：Semiconductor substrate 100；Positioned at institute
State the gate dielectric layer 102 in Semiconductor substrate 100；Work-function layer 103 on the gate dielectric layer 102；Positioned at the work(
Gate electrode layer 104 on function layer 103；Positioned at 104 liang of the dielectric layer 102, the work-function layer 103 and the gate electrode layer
The side wall 105 of side；Source region and drain region 106 in the Semiconductor substrate 100 of the both sides of gate electrode layer 104.Prior art
MOS transistor in, by selecting the material of appropriate work-function layer 103, such as TiN, TaAl or TiC, change MOS transistor
Work function difference between gate electrode and gate dielectric layer, to adjust the threshold voltage of MOS transistor, obtain on the same chip different
The transistor of threshold voltage, make the threshold voltage of input/output transistors higher, the threshold voltage of core logic transistor compared with
It is low.Because the work-function layer 103 is usually sandwich construction, and applied to nmos pass transistor and the work-function layer of PMOS transistor
Material is different, and formation process is complicated.Especially in fin formula field effect transistor, work-function layer forms and is protruding from Semiconductor substrate
Fin on, further increase technology difficulty, cost is high.
Therefore, the forming method of the fin formula field effect transistor of the multi-Vt of prior art, complex process, cost
It is high.
Other forming methods about multi-Vt transistor can also refer to Publication No. US2011/0248351A1
U.S. Patent application.
The content of the invention
The present invention solves the problems, such as be prior art formed multi-Vt transistor complex process, cost height.
To solve the above problems, the present invention proposes a kind of forming method of fin formula field effect transistor, including：There is provided half
Conductor substrate, the Semiconductor substrate have first area and second area, had in the first area and second area convex
Fin, the grid structure on the fin risen, the top of fin and side wall described in the grid structure covering part；
The grid structure both sides of the first area form the first side wall, and the part fin of the first side wall covering forms the first negative screening
Cover region；The second side wall is formed in the grid structure both sides of the second area, the width of second side wall is less than described first
The width of side wall, the part fin of the second side wall covering form the second negative covering area；To the first area and the secondth area
The fin of the grid structure both sides in domain carries out ion implanting, forms source region and drain region.
Optionally, the described second negative width for covering area is less than the described first negative width for covering area.
Optionally, the described first negative width range for covering area is 300 angstroms~500 angstroms.
Optionally, the described second negative width range for covering area is 10 angstroms~50 angstroms.
Optionally, the fin formula field effect transistor that the first area is formed is as input/output transistors.
Optionally, the doping of the described first negative doping concentration and the input/output transistors channel region for covering area
Concentration is identical.
Optionally, in addition to the first negative area that covers at the drain region end of the input/output transistors ion implanting is carried out,
Form transoid doped region.
Optionally, the doping type of the transoid doped region adulterates with the source region of the input/output transistors and drain region
Type is opposite.
Optionally, the width range of the transoid doped region is 1 angstrom~300 angstroms.
Optionally, the fin formula field effect transistor that the second area is formed is as core logic transistor.
Optionally, the described second negative doping concentration for covering area and the doping of the core logic transistor channel region are dense
Spend identical.
Optionally, the material of first side wall and the second side wall is high dielectric constant material.
Optionally, the high dielectric constant material is HfO2、Al2O3、ZrO2, in HfSiO, HfSiON, HfTaO and HfZrO
One or more.
Optionally, in addition to the fin of the first area and the grid structure both sides of second area carry out pre-amorphous
Ion implanting.
Optionally, the injection ion of the pre-amorphous ion implanting is Si, C, Ge, Xe or Ar.
It is corresponding, the invention also provides a kind of fin formula field effect transistor, including：Semiconductor substrate, the semiconductor
Substrate has first area and second area, has raised fin in the first area and second area；Positioned at the fin
Grid structure in portion, the top of fin and side wall described in the grid structure covering part；Grid positioned at the first area
First side wall of pole structure both sides, the part fin of the first side wall covering form the first negative covering area；Positioned at described second
Second side wall of the grid structure both sides in region, the width of second side wall are more than the width of first side wall, and described the
The part fin of two side walls covering forms the second negative covering area；Positioned at the first area and the grid structure both sides of second area
Fin in source region and drain region.
Optionally, the described second negative width for covering area is less than the described first negative width for covering area.
Optionally, the first area is input/output transistors region, and the second area is core logic transistor
Region.
Optionally, in addition to the transoid in the first negative covering area at the drain region end of the input/output transistors is mixed
Miscellaneous area, the doping type of the transoid doped region is with the source region of the input/output transistors and drain region doping type on the contrary, institute
The width range for stating transoid doped region is 1 angstrom~300 angstroms.
Optionally, the material of first side wall and the second side wall is high dielectric constant material.
Compared with prior art, the present invention has advantages below：
In the forming method of the fin formula field effect transistor of the embodiment of the present invention, the grid structure both sides shape in first area
Into the first side wall, the second side wall is formed in the grid structure both sides of second area, due to first side wall and the second side wall
Width is different, and first under first side wall is negative to cover area and the second negative width for covering area under the second side wall
It is different.In the fin formula field effect transistor with negative covering area, the width in different negative covering areas causes the fin being subsequently formed
Effective channel width of formula field-effect transistor is different, changes channel region Electric Field Distribution, influences fin formula field effect transistor
Threshold voltage.The embodiment of the present invention is exactly the influence for covering sector width to fin formula field effect transistor threshold voltage using bearing,
In the forming process of fin formula field effect transistor, by controlling the width of the side wall formed in first area and second area,
To control the first negative width for covering area and the second negative covering area, the fin field effect crystal with different threshold voltages is obtained
Pipe, technique is simple, and cost is low.
Further, in the forming method of the fin formula field effect transistor of the embodiment of the present invention, the first area is formed
Fin formula field effect transistor as input/output transistors, due to input/output transistors it is generally necessary to higher threshold value electricity
Pressure and breakdown voltage, therefore, ion implanting, shape are carried out to the first negative area that covers at the drain region end of the input/output transistors
Into transoid doped region.The doping type of the transoid doped region and the source region of the input/output transistors and drain region doping class
Type further increases hitting for the input/output transistors on the contrary, form potential barrier between the transoid doped region and drain region
Wear voltage and threshold voltage.
Corresponding, the fin formula field effect transistor of the embodiment of the present invention is adopted to be formed with the aforedescribed process, therefore positioned at the
The fin formula field effect transistor in one region and fin formula field effect transistor positioned at second area have different threshold voltages.
Brief description of the drawings
Fig. 1 is the structural representation of the MOS transistor of prior art；
Fig. 2 to Fig. 6 is the structural representation of the fin formula field effect transistor forming process of the embodiment of the present invention.
Embodiment
From background technology, the technique that prior art forms the fin formula field effect transistor with multi-Vt is answered
Miscellaneous, cost is high.
The present inventor have studied covers area with negative（Underlap）Fin formula field effect transistor formation side
Method, find because the negative area that covers does not carry out lightly doped drain injection（LDD）Injected with halo（Halo Implantation）,
The negative area that covers can increase effective channel region width of fin formula field effect transistor, alleviate short-channel effect.And not
Difference is influenceed on the channel region Electric Field Distribution of fin formula field effect transistor with the negative width for covering area, threshold voltage is influenceed not
Together, therefore the fin field effect crystal with different threshold voltages can be obtained by controlling the width in the negative covering area formed
Pipe.
Studied based on more than, the present inventor proposes a kind of forming method of fin formula field effect transistor, half
Conductor substrate first area and the grid structure both sides of second area form the first side wall and the second side wall with different in width,
Area and the second negative width for covering area under second side wall are covered because first under first side wall is negative
Difference, the threshold value for the fin formula field effect transistor that the fin formula field effect transistor and second area that the first area is formed are formed
Voltage is different.The technology difficulty to form the fin formula field effect transistor with different threshold voltages is reduced, manufacturing cost is low.
Describe specific embodiment in detail below in conjunction with the accompanying drawings, above-mentioned purpose and advantages of the present invention will be apparent from.
Fig. 2 to Fig. 6 is the structural representation of the fin formula field effect transistor forming process of the embodiment of the present invention.
It refer to Fig. 2, there is provided Semiconductor substrate 200, the Semiconductor substrate 200 have first area Ι and second area
II, the first area Ι and second area II are interior to have prominent fin 202, the grid structure on the fin 202
203, the top of fin 202 and side wall described in the covering part of grid structure 203.
The Semiconductor substrate 200 can be silicon or silicon-on-insulator（SOI）, the Semiconductor substrate 200 can also
It is germanium, germanium silicon, GaAs or germanium on insulator.The Semiconductor substrate 200 has first area Ι and second area II, institute
State first area Ι and second area II is for respectively forming the fin formula field effect transistor with different threshold voltages.Described half
The surface of conductor substrate 200 has a raised fin 202, and the connected mode of the fin 202 and the Semiconductor substrate 200 can be with
It is integral, such as the fin 202 is the bulge-structure by being formed after being etched to the Semiconductor substrate 200.The grid
Pole structure 203 is located on the fin 202, the top of fin 202 and side wall described in the covering part of grid structure 203.This
In embodiment, the grid structure 203 includes gate dielectric layer and gate electrode layer（It is not shown）, the material of the gate dielectric layer is oxygen
SiClx, the material of the gate electrode layer is polysilicon.
In another embodiment, the grid structure is dummy grid, and the material of the dummy grid is polysilicon.The pseudo- grid
Pole is in high-dielectric-coefficient grid medium layer and metal gates（HKMG）Rear grid formation process in, for reducing the Gao Jie that is subsequently formed
The heat budget of electric constant gate dielectric layer and metal gate electrode.After the dummy grid is removed in subsequent technique, in the dummy grid
Position sequentially forms high-dielectric-coefficient grid medium layer and metal gates.
In the present embodiment, in addition to it is located at the surface of Semiconductor substrate 200, and the side wall of fin 202 described in covering part
Fleet plough groove isolation structure 201（STI）.The fleet plough groove isolation structure 201 is used for the difference in the Semiconductor substrate 200
Fin is isolated, and the material of the fleet plough groove isolation structure 201 is silica, and the forming method of the fleet plough groove isolation structure can be with
With reference to existing process, will not be repeated here.
Fig. 3 is refer to, Fig. 3 is during forming fin formula field effect transistor on the basis of Fig. 2, along AA1 directions
Cross-sectional view, the first side wall 204, first side wall are formed in the both sides of grid structure 203 of the first area Ι
The part fin 202 of 204 coverings forms the first negative covering area（Do not indicate）.
Specifically, it is initially formed the first photoresist layer（It is not shown）, the first photoresist layer covering second area
II, first photoresist layer is used for the fin 202 and grid structure 203 for protecting the second area II in subsequent technique；
Secondly, using physical vapour deposition (PVD), chemical vapor deposition or atom layer deposition process the first area Ι fin 202
The first spacer material layer of upper formation（It is not shown）, the first spacer material layer covering first area Ι grid structure
203, the first spacer material layer has higher dielectric constant, such as the first spacer material layer is HfO2、Al2O3、
ZrO2, one or more in HfSiO, HfSiON, HfTaO and HfZrO；Then it is etched back to described using dry etch process
The side walling bed of material, because dry etching has preferable directionality, be etched back to it is described with the first spacer material layer after, be only located at
First spacer material layer of the both sides of grid structure 203 of the first area Ι retains to form the first side wall 204, positioned at described
The one region Ι top of grid structure 203 and the first spacer material layer in remaining region are removed；Remove first photoresist
Layer.
After forming first side wall 204, the part fin 202 that first side wall 204 covers forms the first negative covering
Area.Because the first negative area that covers will not carry out lightly doped drain injection and halo injection, the first negative screening in subsequent technique
The doping concentration of cover region and the doping concentration of the channel region of first area Ι fin formula field effect transistor that is subsequently formed and mix
Miscellany type is identical, can increase effective channel width of first area Ι fin formula field effect transistor, alleviates short-channel effect.
And because first side wall 204 has higher dielectric constant, the first negative capacitance for covering area can be improved so that follow-up
Be formed at first area Ι fin formula field effect transistor driving current will not because of first it is negative cover area doping concentration it is relatively low
And driving current is caused to reduce.
In the present embodiment, the fin formula field effect transistor that the first area Ι is formed is as input/output transistors, institute
State input/output transistors and usually require that there is higher threshold voltage.The described first negative width range for covering area is 300 angstroms
~500 angstroms, the described first negative width range for covering area can be controlled by adjusting the width of first side wall 204.
In fin formula field effect transistor with negative covering area, the width in different negative covering areas can cause fin formula field effect transistor
Effective channel width is different, and channel region Electric Field Distribution is different, and the threshold voltage of fin formula field effect transistor is also different, and fin
The threshold voltage of field-effect transistor can increase and increase with the width in negative covering area.In the present embodiment, the first negative screening
The width of cover region is larger, and the threshold voltage of the input/output transistors formed is also higher.
Fig. 4 is refer to, the second side wall 205, second side are formed in the both sides of grid structure 203 of the second area II
The width of wall 205 is less than the width of first side wall 204, and the part fin 202 that second side wall 205 covers forms second
It is negative to cover area（Do not indicate）.
Specifically, it is initially formed the second photoresist layer（It is not shown）, the second photoresist layer covering first area
Ι, second photoresist layer are used for fin 202, the side wall of grid structure 203 and first for protecting first area Ι in subsequent technique
204；Secondly, using physical vapour deposition (PVD), chemical vapor deposition or atom layer deposition process the second area II fin
The second spacer material layer is formed in portion 202（It is not shown）, the grid of the second spacer material layer covering second area II
Structure 203, the second spacer material layer have higher dielectric constant, and the second spacer material layer is HfO2、Al2O3、
ZrO2, one or more in HfSiO, HfSiON, HfTaO and HfZrO, the second spacer material layer can be with the first side wall
204 material is identical or different；The second spacer material layer is etched back to using dry etch process, formed positioned at described the
The second side wall of both sides 205 of grid structure 203 of two region IIs；Remove second photoresist layer.
After forming second side wall 205, the part fin 202 that second side wall 205 covers forms the second negative covering
The channel region of area, the described second negative doping concentration for covering area and the fin formula field effect transistor for being formed at second area II
Doping concentration is identical.In the present embodiment, the fin formula field effect transistor that the second area II is formed is as core logic crystal
Pipe, the threshold voltage of the core logic transistor is relatively low, to reduce the power consumption of core logic transistor.Please continue to refer to Fig. 4,
During being formed positioned at the core logic transistor of the second area II, the width of second side wall 205 is less than institute
The width of the first side wall 204 is stated, the width of second side wall 205 and the width of the first side wall 204 refer to second side
Wall 205 and the bottom of the first side wall 204 and the width of the contact surface of the fin 202, in the present embodiment, the second negative screening
The width range of cover region is 10 angstroms~50 angstroms.Therefore the second negative width for covering area under second side wall 205 is less than
Under first side wall 204 first it is negative cover area width, due to fin formula field effect transistor threshold voltage with
Bear the reduction for covering sector width and reduce, the threshold voltage of the core logic transistor is again smaller than the input/output crystal
Pipe.
It refer to Fig. 5, in the present embodiment, the fin formula field effect transistor that the first area Ι is formed is as input/output
Transistor, in order to further improve the threshold voltage of the input/output transistors and breakdown voltage, also to it is described input/it is defeated
The the first negative area that covers for going out the drain region end to be formed of transistor carries out ion implanting, forms transoid doped region 206.Need what is illustrated
It is that, in order to concise in Fig. 5, illustrate only the cross-sectional view of the input/output transistors positioned at first area Ι.
Specifically, form the 3rd photoresist layer（It is not shown）, the 3rd photoresist layer covering second area II, institute
The 3rd photoresist layer is stated to be used to protect the second area II in follow-up ion implantation process；Then to it is described input/it is defeated
The the first negative area that covers for going out the drain electrode end of transistor carries out ion implanting, forms transoid doped region 206.Need what is illustrated, it is described
Channel direction of the injection direction of ion implantation technology along the input/output transistors, and with the table of Semiconductor substrate 200
Face has angle so that in injection process, only the first negative area that covers at input/output transistors drain region end to be formed is carried out
Ion implanting, forms transoid doped region 206, and due to the blocking effect of the grid structure 203, will not be pointed to input/defeated
The the first negative area that covers for going out transistor source region end to be formed carries out ion implanting.
The doping type of the transoid doped region 206 and the source region of the input/output transistors and the doping class in drain region
Type is opposite.In the present embodiment, the input/output transistors are nmos pass transistor, and source region and drain region are n-type doping, described anti-
The doping type of type doped region 206 is p-type, such as can be boron ion, phosphonium ion or gallium ion doping.In the present embodiment,
The first negative injection ion for covering area's progress ion implanting to the drain region end of the input/output transistors is BF2, it is described anti-
The width range of type doped region 206 is 1 angstrom~300 angstroms.Due to the transoid doped region 206 doping type with it is described input/
Source region and the drain region doping type of output transistor enter one on the contrary, form potential barrier between the transoid doped region 206 and drain region
Step improves the breakdown voltage and threshold voltage of the input/output transistors.
In another embodiment, the input/output transistors are that PMOS transistor, source region and drain region are adulterated for p-type, institute
The doping type for stating transoid doped region is N-type, such as can be phosphonium ion, arsenic ion or antimony ion doping.
Refer to Fig. 6, the first area Ι and the both sides of grid structure 203 of second area II fin 202 is carried out from
Son injection, forms source region 207 and drain region 208.
In the present embodiment, the first area Ι and second area II are used to form nmos pass transistor, to the first area
The fins 202 of the both sides of grid structure 203 of Ι and second area II carries out N-type ion implanting, for example, can be phosphonium ion, arsenic from
Son or antimony ion injection, form source region 207 and drain region 208.It should be noted that the direction of the ion implanting is perpendicular to institute
The channel direction of nmos pass transistor is stated, and there is angle with the surface of Semiconductor substrate 200 so that in ion implantation process
In, ion implanting only is carried out to the fin 202 of the both sides of grid structure 203, and work is blocked due to the grid structure 203
With the second negative area that covers that negative to the first of first area Ι will not cover area and second area II carries out ion implanting, influences the
The one negative doping concentration for covering area and the second negative covering area.
In another embodiment, the first area Ι and second area II are used to form PMOS transistor, to described first
The fin of the grid structure both sides of region Ι and second area II carries out p-type ion implanting, such as can be boron ion, phosphonium ion
Or gallium ion injection, form source region and drain region.
In another embodiment, before source region and drain region is formed, also to the first area Ι and the grid of second area II
Structure both sides fin has carried out pre-amorphous ion implanting（PAI：Pre-Amorphization Implantation）, it is described pre-
The monocrystal material of source region to be formed and the fin portion surface in drain region can be converted into non-crystalline material by amorphizing ion injection.Follow-up
When progress source region and the ion implanting in drain region, because the fin portion surface material is non-crystalline material, lattice arrangement is irregular, to note
Enter the scattering enhancing of ion, the distribution of injection ion is more concentrated, hangover is shorter, is advantageous to improve formed fin field effect
The performance of transistor.The particle of the pre-amorphous injection is Si, C, Ge, Xe or Ar.
It is corresponding, please continue to refer to Fig. 6, the invention also provides a kind of fin formula field effect transistor, including：Semiconductor serves as a contrast
Bottom 200, the surface of Semiconductor substrate 200 have first area Ι and second area II, the first area Ι and second area
There is raised fin 202 in II；Grid structure 203 on the fin 202, the covering part of grid structure 203
The top of the fin 202 and side wall；The first side wall 204 positioned at the both sides of grid structure 203 of the first area Ι, it is described
The part fin 202 of first side wall 204 covering forms the first negative covering area（It is not shown）；Positioned at the grid of the second area II
Second side wall 205 of the both sides of structure 203, the width of second side wall 205 is less than the width of first side wall 204, described
The material of first side wall 204 and the second side wall 205 is high dielectric constant material；The part fin that second side wall 205 covers
202 form the second negative covering area（It is not shown）；Positioned at the both sides of grid structure 203 of the first area Ι and second area II
Source region 207 and drain region 208 in fin 202.
In the present embodiment, the first area Ι is input/output transistors region, and the second area II is patrolled for core
Collect transistor area.The described second negative width for covering area is less than the described first negative width for covering area.In the present embodiment, also wrap
The first negative transoid doped region 206 covered in area positioned at the end of drain region 208 of the input/output transistors has been included, it is described anti-
The source region 207 and the doping type of drain region 208 of the doping type of type doped region 206 and the input/output transistors are on the contrary, described
The width range of transoid doped region 206 is 1 angstrom~300 angstroms.
The fin formula field effect transistor of the present embodiment is formed using the forming method of above-mentioned fin formula field effect transistor,
Therefore, the fin formula field effect transistor positioned at first area Ι and the fin formula field effect transistor positioned at second area II have not
Same threshold voltage.
In summary, compared with prior art, the present invention has advantages below：
In the forming method of the fin formula field effect transistor of the embodiment of the present invention, the grid structure both sides shape in first area
Into the first side wall, the second side wall is formed in the grid structure both sides of second area, due to first side wall and the second side wall
Width is different, and first under first side wall is negative to cover area and the second negative width for covering area under the second side wall
It is different.In the fin formula field effect transistor with negative covering area, the width in different negative covering areas causes the fin being subsequently formed
Effective channel width of formula field-effect transistor is different, changes channel region Electric Field Distribution, influences fin formula field effect transistor
Threshold voltage.The embodiment of the present invention is exactly the influence for covering sector width to fin formula field effect transistor threshold voltage using bearing,
In the forming process of fin formula field effect transistor, by controlling the width of the side wall formed in first area and second area,
To control the first negative width for covering area and the second negative covering area, the fin field effect crystal with different threshold voltages is obtained
Pipe, technique is simple, and cost is low.
Further, in the forming method of the fin formula field effect transistor of the embodiment of the present invention, the first area is used for
Input/output transistors are formed, due to input/output transistors it is generally necessary to higher threshold voltage and breakdown voltage, therefore,
Ion implanting is carried out to the first negative area that covers at the drain region end of the input/output transistors, forms transoid doped region.It is described anti-
Source region and the drain region doping type of the doping type of type doped region and the input/output transistors in the transoid on the contrary, mix
Potential barrier is formed between miscellaneous area and drain region, further increases the breakdown voltage and threshold voltage of the input/output transistors.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques of the disclosure above to skill of the present invention
Art scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, the skill according to the present invention
Any simple modifications, equivalents, and modifications that art is substantially made to above example, belong to the guarantor of technical solution of the present invention
Protect scope.
Claims (19)
- A kind of 1. forming method of fin formula field effect transistor, it is characterised in that including：Semiconductor substrate is provided, the Semiconductor substrate has first area and second area, the first area and the secondth area There is raised fin, the grid structure on the fin, the top of fin described in the grid structure covering part in domain Portion and side wall；Form the first side wall in the grid structure both sides of the first area, the part fin of first side wall covering forms the One negative covering area；The second side wall is formed in the grid structure both sides of the second area, the width of second side wall is less than first side The width of wall, the part fin of the second side wall covering form the second negative covering area；Ion implanting is carried out to the fin of the first area and the grid structure both sides of second area, forms source region and drain region；Wherein, the fin formula field effect transistor that the first area is formed as input/output transistors, first side wall Material is high dielectric constant material, the doping concentration of the channel region in the described first negative fin for covering area and first area and is mixed Miscellany type is identical.
- 2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the second negative covering area Width be less than described first it is negative cover area width.
- 3. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the first negative covering area Width range be 300 angstroms~500 angstroms.
- 4. the forming method of fin formula field effect transistor as claimed in claim 2, it is characterised in that the second negative covering area Width range be 10 angstroms~50 angstroms.
- 5. the forming method of fin formula field effect transistor as claimed in claim 4, it is characterised in that the first negative covering area Doping concentration it is identical with the doping concentration of the input/output transistors channel region.
- 6. the forming method of fin formula field effect transistor as claimed in claim 4, it is characterised in that also include to described defeated Enter/the first negative area that covers at the drain region end of output transistor carries out ion implanting, form transoid doped region.
- 7. the forming method of fin formula field effect transistor as claimed in claim 6, it is characterised in that the transoid doped region Doping type is opposite with the source region and drain region doping type of the input/output transistors.
- 8. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that the transoid doped region Width range is 1 angstrom~300 angstroms.
- 9. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the second area is formed Fin formula field effect transistor as core logic transistor.
- 10. the forming method of fin formula field effect transistor as claimed in claim 9, it is characterised in that the second negative covering The doping concentration in area is identical with the doping concentration of the core logic transistor channel region.
- 11. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that second side wall Material is high dielectric constant material.
- 12. the forming method of the fin formula field effect transistor as described in claim 1 or 11, it is characterised in that the high dielectric Constant material is HfO2、Al2O3、ZrO2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.
- 13. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include to described the The fin of one region and the grid structure both sides of second area carries out pre-amorphous ion implanting.
- 14. the forming method of fin formula field effect transistor as claimed in claim 13, it is characterised in that it is described it is pre-amorphous from The injection ion of son injection is Si, C, Ge, Xe or Ar.
- A kind of 15. fin formula field effect transistor, it is characterised in that including：Semiconductor substrate, the Semiconductor substrate have a first area and second area, in the first area and second area Fin with projection；Grid structure on the fin, the top of fin and side wall described in the grid structure covering part；The first side wall positioned at the grid structure both sides of the first area, the part fin of first side wall covering form the One negative covering area；The second side wall positioned at the grid structure both sides of the second area, the width of second side wall are less than first side The width of wall, the part fin of the second side wall covering form the second negative covering area；Source region and drain region in the fin of the first area and the grid structure both sides of second area；Wherein, the fin formula field effect transistor that the first area is formed as input/output transistors, first side wall Material is high dielectric constant material, the doping concentration of the channel region in the described first negative fin for covering area and first area and is mixed Miscellany type is identical.
- 16. fin formula field effect transistor as claimed in claim 15, it is characterised in that the width in the second negative covering area is small In the described first negative width for covering area.
- 17. fin formula field effect transistor as claimed in claim 15, it is characterised in that the first area is input/output Transistor area, the second area are core logic transistor region.
- 18. fin formula field effect transistor as claimed in claim 17, it is characterised in that also include being located at the input/output The drain region end of transistor first it is negative cover area in transoid doped region, the doping type of the transoid doped region with it is described defeated Enter/source region of output transistor and drain region doping type be on the contrary, the width range of the transoid doped region is 1 angstrom~300 angstroms.
- 19. fin formula field effect transistor as claimed in claim 15, it is characterised in that the material of second side wall is Gao Jie Permittivity material.
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| US7009265B2 (en) * | 2004-06-11 | 2006-03-07 | International Business Machines Corporation | Low capacitance FET for operation at subthreshold voltages |
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