CN104064467B - The forming method of fin formula field effect transistor - Google Patents
The forming method of fin formula field effect transistor Download PDFInfo
- Publication number
- CN104064467B CN104064467B CN201310093720.2A CN201310093720A CN104064467B CN 104064467 B CN104064467 B CN 104064467B CN 201310093720 A CN201310093720 A CN 201310093720A CN 104064467 B CN104064467 B CN 104064467B
- Authority
- CN
- China
- Prior art keywords
- field effect
- effect transistor
- formula field
- fin
- forming method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 80
- 230000005669 field effect Effects 0.000 title claims abstract description 59
- 230000004888 barrier function Effects 0.000 claims abstract description 43
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000001590 oxidative effect Effects 0.000 claims description 29
- 239000000463 material Substances 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 21
- 239000007789 gas Substances 0.000 claims description 20
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 20
- 239000008367 deionised water Substances 0.000 claims description 16
- 229910021641 deionized water Inorganic materials 0.000 claims description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 10
- 239000001257 hydrogen Substances 0.000 claims description 10
- 229910052739 hydrogen Inorganic materials 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000005507 spraying Methods 0.000 claims description 10
- 239000000243 solution Substances 0.000 claims description 9
- 239000011259 mixed solution Substances 0.000 claims description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 5
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 4
- 239000007800 oxidant agent Substances 0.000 claims description 4
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 claims description 4
- 229910001868 water Inorganic materials 0.000 claims description 4
- 229910004129 HfSiO Inorganic materials 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052593 corundum Inorganic materials 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 3
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 3
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 6
- 125000001475 halogen functional group Chemical group 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000001994 activation Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- -1 boron Ion Chemical class 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910001439 antimony ion Inorganic materials 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- CKHJYUSOUQDYEN-UHFFFAOYSA-N gallium(3+) Chemical compound [Ga+3] CKHJYUSOUQDYEN-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of fin formula field effect transistor, including：Semiconductor substrate is provided, the semiconductor substrate surface has raised fin, the grid structure on the fin, the top of fin and side wall described in the grid structure covering part；The part fin of the grid structure both sides is etched, opening is formed；In the bottom of the opening and sidewall surfaces formation barrier oxide layer；Embedded source region and drain region are formed in the opening.The forming method of the fin formula field effect transistor of the present invention prevents the impurity in embedded source region and drain region to diffuse into negative covering area, is conducive to improving transistor performance.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of fin formula field effect transistor.
Background technology
MOS transistor in grid by applying voltage, and regulation produces switching signal by the electric current of channel region.With
The development of semiconductor technology, traditional plane formula MOS transistor dies down to the control ability of channel current, causes serious electric leakage
Stream.Fin formula field effect transistor（Fin FET）It is a kind of emerging multi-gate device, it, which is generally comprised, protrudes from Semiconductor substrate table
The semiconductor fin in face, the grid structure of the top of fin and side wall described in covering part, positioned at the grid structure both sides
Source region and drain region in fin.
But below 20 nanometer nodes, the thickness of fin formula field effect transistor fin is minimum, short-channel effect is obvious, such as threshold
Threshold voltage is to changes in channel length sensitivity, carrier velocity saturation effect, hot carrier's effect and Sub-Threshold Characteristic degeneration etc..For
Solve the above problems, prior art proposes a kind of fin formula field effect transistor (Fin FET with for having and bearing and covering area
underlaps).Fig. 1 is refer to, Fig. 1, which shows that prior art is a kind of, has cuing open for the negative fin formula field effect transistor for covering area
Face structural representation, including：Semiconductor substrate 100；The fin 101 of protrusion in the Semiconductor substrate 100, the fin
Portion 101 is formed by being etched to the Semiconductor substrate 100；The gate dielectric layer 103 on the surface of fin 101 described in covering part；Position
Gate electrode layer 104 on the gate dielectric layer 103；Side positioned at the gate dielectric layer 103 and the both sides of the gate electrode layer 104
Wall 105；Source region and drain region 102 in the fin 101 of the both sides of gate electrode layer 104；Positioned at the lower section of side wall 105
Negative covering area in fin 101（underlap）106, the doping concentration and the fin field effect in the negative covering area 106 are brilliant
Body pipe channel region（It is not shown）Doping concentration it is identical.In the above-mentioned fin formula field effect transistor with negative covering area 106,
Due to not carrying out lightly doped drain injection to the negative covering area 106（LDD）With halo injection（Halo
Implantation）, the doping concentration in the negative covering area 106 and the doping of the fin formula field effect transistor channel region are dense
Degree is identical, increases effective channel region length, alleviates short-channel effect.
But, in the above-mentioned forming process with the negative fin formula field effect transistor for covering area, source region and drain region 102
Doped ions readily diffuse into negative covering area 106 in impurity activation or other Technologies for Heating Processing, change negative covering area 106
Doping concentration, reduces transistor performance.
Other can also refer to Publication No. about the forming method with the negative fin formula field effect transistor for covering area
US2005/0275045A1 U.S. Patent application.
The content of the invention
The problem of present invention is solved is that the impurity with source region and drain region in the negative fin formula field effect transistor for covering area holds
Easily diffuse into negative covering area.
To solve the above problems, the invention provides a kind of forming method of fin formula field effect transistor, including：There is provided half
Conductor substrate, the semiconductor substrate surface has raised fin, the grid structure on the fin, the grid knot
The top of fin described in structure covering part and side wall；The part fin of the grid structure both sides is etched, opening is formed；Described
The bottom of opening and sidewall surfaces formation barrier oxide layer；Embedded source region and drain region are formed in the opening.
Optionally, the barrier oxide layer has monoatomic layer or diatomic Rotating fields.
Optionally, the technique in the bottom of the opening and sidewall surfaces formation barrier oxide layer includes：In the opening
Bottom and sidewall surfaces spraying deionized water；Oxidizing gas is passed through, the oxidizing gas is aoxidized with deionized water formation
Agent, aoxidizes the bottom of the opening and the surface of side wall；The step of repeating above-mentioned spraying deionized water and be passed through oxidizing gas, directly
To forming the barrier oxide layer.
Optionally, the oxidizing gas is O3。
Optionally, the technique in the bottom of the opening and sidewall surfaces formation barrier oxide layer is wet oxidation.
Optionally, the wet process oxidation technology uses NH4OH、H2O2And H2O mixed solution.
Optionally, the grid structure includes gate dielectric layer, the gate electrode layer on the gate dielectric layer and is located at
The side wall of gate dielectric layer and the gate electrode layer both sides.
Optionally, the material of the side wall is high dielectric constant material.
Optionally, the high dielectric constant material is HfO2、Al2O3、ZrO2, in HfSiO, HfSiON, HfTaO and HfZrO
One or more.
Optionally, the part fin of the side wall covering constitutes negative covering area.
Optionally, the doping concentration and the doping concentration phase of the channel region of fin formula field effect transistor in the negative covering area
Together.
Optionally, in addition to, before the bottom of the opening and sidewall surfaces formation barrier oxide layer, remove the opening
Bottom and the natural oxidizing layer of sidewall surfaces.
Optionally, the technique for removing the natural oxidizing layer is wet etching.
Optionally, the wet-etching technology uses HF solution, NH3With HF mixed solution or NF3With HF mixing
Solution.
Optionally, in addition to, formed in the opening before embedded source region and drain region, to the bottom and side of the opening
Wall carries out hydrogen pretreatment.
Optionally, the temperature of the hydrogen pretreatment is less than 800 degrees Celsius.
Optionally, the technique that embedded source region and drain region are formed in the opening is selective epitaxial process.
Optionally, the selective epitaxial process is molecular beam epitaxy or ultra-high vacuum CVD.
Optionally, the material in the embedded source region and drain region is germanium silicon, carborundum or silicon.
Optionally, the embedded source region and drain region are doped with N-type or p type impurity.
Compared with prior art, technical solution of the present invention has advantages below：
In the forming method of the fin formula field effect transistor of the embodiment of the present invention, the portion of the grid structure both sides is being etched
Divide fin, formed after opening, in the bottom of the opening and sidewall surfaces formation barrier oxide layer, then again in the opening
It is interior to form embedded source region and drain region.The barrier oxide layer is under the embedded source/drain regions and the grid structure
Particle trap is introduced between fin, the thermal diffusion of impurity can be stopped.Therefore, the fin field effect of the embodiment of the present invention
In the forming method of transistor, the barrier oxide layer can prevent fin formula field effect transistor as impurity diffusion impervious layer
Embedded source region and drain region the part fin that diffuses under the grid structure of impurity and influence the negative area that covers
Doping concentration, is conducive to improving the performance of transistor.
Further, when the embodiment of the present invention forms the barrier oxide layer, in the bottom of the opening and sidewall surfaces
Deionized water is sprayed, oxidizing gas is then passed to, the oxidizing gas and deionized water formation oxidant are opened described in oxidation
Mouthful bottom and side wall surface, and the step of repeat above-mentioned spraying deionized water and be passed through oxidizing gas, until forming described
Barrier oxide layer.Due to above-mentioned technique spray deionized water and be passed through gas amount it is limited and can accurately control, the oxygen of formation
The amount of agent is also limited and can accurately control, therefore, in the bottom of the opening and the thickness of the barrier oxide layer of side wall formation
Degree can be controlled in relatively thin size, for example, can be the barrier oxide layer of monoatomic layer or diatomic layer.Relatively thin resistance
Gear oxidated layer thickness is conducive to improving the embedded source region of subsequent epitaxial formation and the lattice quality of drain region material, reduces due to crystalline substance
Boundary defect caused by lattice mismatch.
Brief description of the drawings
Fig. 1 is the cross-sectional view with the negative fin formula field effect transistor for covering area of prior art；
Fig. 2 to Fig. 6 is the structural representation of the forming process of the fin formula field effect transistor of the embodiment of the present invention.
Embodiment
From background technology, source region and leakage in the fin formula field effect transistor for covering area are born in having for prior art formation
The impurity in area readily diffuses into negative covering area.
The present inventor is by studying the formation with the negative fin formula field effect transistor for covering area of prior art
Method, finds because the negative area that covers will not carry out lightly doped drain injection and halo injection in formation process, therefore described negative
The doping concentration for covering area is relatively low, suitable with the doping concentration of the channel region of fin formula field effect transistor.Therefore, in source region and
Drain region formed after impurity activation process or other thermal annealing process in, the impurity in source region and drain region readily diffuses into low
The negative covering area of doping concentration, influences the performance of transistor.
Studied based on more than, the present inventor proposes a kind of forming method of fin formula field effect transistor, in etching
The part fin of grid structure both sides, is formed after opening, in the bottom of the opening and sidewall surfaces formation barrier oxide layer,
Then embedded source region and drain region are formed in the opening again.The barrier oxide layer can be prevented as diffusion impervious layer
The embedded source region of fin formula field effect transistor and the impurity in drain region diffuse into negative covering area.
Describe specific embodiment in detail below in conjunction with the accompanying drawings, above-mentioned purpose and advantages of the present invention will be apparent from.
Fig. 2 to Fig. 6 is the structural representation of the forming process of the fin formula field effect transistor of the embodiment of the present invention.
Refer to Fig. 2 and Fig. 3, Fig. 3 be in Fig. 2 along the cross-sectional view in AA1 directions there is provided Semiconductor substrate 200,
The surface of Semiconductor substrate 200 has raised fin 201, the grid structure 202 on the fin 201, the grid
The top of fin 201 and side wall described in the covering part of pole structure 202.
The Semiconductor substrate 200 can be silicon or silicon-on-insulator（SOI）, the Semiconductor substrate 200 can also
It is germanium, germanium silicon, GaAs or germanium on insulator.In the present embodiment, the Semiconductor substrate 200 is silicon substrate.It is described partly to lead
The surface of body substrate 200 has raised fin 201, and the fin 201 and the connected mode of the Semiconductor substrate 200 can be
One, such as described fin 201 is the bulge-structure by being formed after being etched to the Semiconductor substrate 200.
The grid structure 202 includes gate dielectric layer（It is not shown）, gate electrode layer 203 on the gate dielectric layer with
And the side wall 204 positioned at the gate dielectric layer and the both sides of gate electrode layer 203.It refer in Fig. 3, the present embodiment, the side wall 204
The part fin 201 of covering constitutes negative covering area（underlaps）206, will not be to the negative covering area 206 in subsequent technique
Carry out lightly doped drain injection（LDD）With halo injection（Halo）, therefore, the doping concentration in the negative covering area 206 with it is follow-up
The doping concentration of the channel region of the fin formula field effect transistor of formation is identical.The doping concentration in the negative covering area 206 is relatively low,
Effective channel region length of fin formula field effect transistor can be increased, alleviate short-channel effect（SCE）, improve transistor
Energy.
In the present embodiment, the material of the gate dielectric layer is silica, and the material of the gate electrode layer 203 is polysilicon.
In other embodiments, the gate dielectric layer and the gate electrode layer 203 constitute dummy grid, rear grid（gate-last）In technique,
The dummy grid is removed, then high-dielectric-coefficient grid medium layer and metal gates are formed in former dummy grid position, high-K metal gate is formed
Structure（HKMG）Structure, is conducive to improving the breakdown voltage of transistor, reduces leakage current, improve transistor performance.
Such as in the present embodiment, the material of the side wall 204 is high dielectric constant material, and the material of described side wall 204 is
HfO2、Al2O3、ZrO2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.In the fin with negative covering area
In effect transistor, due to the negative presence for covering area 206, the doping concentration for bearing covering area 206 is relatively low, and channel resistance increase is led
The driving current of fin formula field effect transistor is caused to decline.Therefore, in the present embodiment, the side wall 204 is with high-k
Dielectric material, the negative capacitance for covering area 206 can be improved, the negative resistance for covering area 206 of reduction is conducive to lifting fin
The driving current of effect transistor.
In the present embodiment, in addition to positioned at the surface of Semiconductor substrate 200, and the side wall of fin 201 described in covering part
Isolation structure 205, the isolation structure 205 is used for the different fins isolated in the Semiconductor substrate 200, the grid knot
The surface of isolation structure 205 described in the covering part of structure 202.In the present embodiment, the isolation structure 205 is fleet plough groove isolation structure
（STI）, the material of the fleet plough groove isolation structure is silica, and the forming method of the fleet plough groove isolation structure may be referred to now
There is technique, will not be repeated here.
Fig. 4 is refer to, the part fin 201 of the both sides of grid structure 202 is etched, opening 207 is formed.
Specifically, being initially formed the mask layer for covering the grid structure 202 and the part fin 201（It is not shown）,
The mask layer exposes the part fin 201 of the both sides of grid structure 202；Again using the mask layer as mask, using each
Anisotropy dry etch process etches the fin 201, forms opening 207；Remove the mask layer.It is described in the present embodiment
Anisotropic dry etch process be reactive ion etching, the opening 207 be used for embedded source is formed in subsequent technique
Area and drain region, the embedded source region and drain region can introduce stress in the channel region of fin formula field effect transistor, improve brilliant
Body pipe performance.
Fig. 5 is refer to, in the bottom of the opening 207 and sidewall surfaces formation barrier oxide layer 208.
In the present embodiment, before the bottom of the opening 207 and sidewall surfaces formation barrier oxide layer 208, to described
The bottom of opening 207 and sidewall surfaces are etched, to remove removing natural oxidizing layer（native oxide）.Described natural oxygen
Change during layer is semiconductor fabrication process, in such as reactive ion etching process or cleaning process, in semi-conducting material table
The oxide layer that face is formed.The thickness of described natural oxidizing layer has uncertainty with quality, it is therefore desirable to remove.Remove institute
The technique for stating natural oxidizing layer is wet etching, and the wet-etching technology uses HF solution, NH3With HF mixed solution or
Person NF3With HF mixed solution.During wet etching using above-mentioned solution, etchant solution only reacts with oxide layer, no
Damage can be caused to Semiconductor substrate 200 and other semiconductor structures.Remove after the natural oxidizing layer, the opening 207 is sudden and violent
Expose the semiconductor surface state of cleaning, be conducive to follow-up processing step.
In the present embodiment, the technique in the bottom of the opening 207 and sidewall surfaces formation barrier oxide layer 208 includes：
In the bottom of the opening 207 and sidewall surfaces spraying deionized water；Then pass to oxidizing gas, the oxidizing gas with it is described
Deionized water formation oxidant, aoxidizes the bottom of the opening 207 and the surface of side wall；Repeat above-mentioned spraying deionized water and logical
The step of entering oxidizing gas, until forming barrier oxide layer 208.Due to above-mentioned spraying deionized water and the amount for being passed through oxidizing gas
Limited and can accurately control, the amount of the oxidant formed is limited, aoxidizes the bottom of the opening 207 and the semiconductor of side wall
The number of times for the step of thickness of material formation oxide just can be by repeating above-mentioned spraying deionized water and being passed through oxidizing gas
To control, reach that accurate control forms the purpose of the thickness of barrier oxide layer 208.In the present embodiment, the oxidizing gas being passed through is
O3, barrier oxide layer 208 is formed for elementary layer or diatomic Rotating fields.
The barrier oxide layer 208 is located at the embedded source region being subsequently formed or drain region and the fin under the grid structure
Between, form particle trap（dopant trap）, can stop that impurity spreads.Therefore, the conduct of barrier oxide layer 208
Impurity diffusion impervious layer, it is therefore prevented that the embedded source region of fin formula field effect transistor and the impurity in drain region diffuse into described
The negative doping concentration for covering area 206 of part fin, influence under grid structure, is conducive to improving the performance of transistor.And this reality
The barrier oxide layer 208 applied in example is formed using above-mentioned spraying deionized water with the technique for being passed through oxidizing gas, the stop oxygen
Changing the thickness of layer 208 can accurately control, for example, can form the barrier oxide layer 208 of elementary layer or diatomic layer.It is relatively thin
The thickness of barrier oxide layer 208 be conducive to improve subsequent epitaxial formation embedded source region and drain region material lattice quality, subtract
It is small due to boundary defect caused by lattice mismatch, be conducive to improve transistor performance.
In another embodiment, the technique in the bottom of the opening and sidewall surfaces formation barrier oxide layer is wet method oxygen
Change.The wet process oxidation technology uses NH4OH、H2O2And H2O mixed solution, NH4OH、H2O2And H2O volume ratio is 1：1：5
~1：2：7.Using above-mentioned wet process oxidation technology, relatively thin stop oxygen can also be formed in the bottom of the opening and sidewall surfaces
Change layer.
Fig. 6 is refer to, in the opening 207（With reference to Fig. 5）It is interior to form embedded source region and drain region 209.
The technique that embedded source region and drain region 209 are formed in the opening 207 is selective epitaxial process.The present embodiment
In, before forming embedded source region and drain region 209 in the opening 207, hydrogen is carried out to the bottom and side wall of the opening 207
Gas is pre-processed（hydrogen pretreatment）.Due in epitaxy technique, in order to obtain higher epitaxial quality, it is necessary to
Ensure the cleanliness factor of epi-layer surface.Hydrogen pretreatment process is toasted to sample, removal sample surfaces that can be in situ
Impurity and defect, are that follow-up epitaxial deposition prepares the semiconductor surface state of cleaning.Further, since in hydrogen pretreatment mistake
Cheng Zhong, hydrogen not only reacts with the impurity of sample surfaces, it is also possible to reacted with barrier oxide layer 208, will aoxidize Si reduction shape
Into silicon and steam, the isolation effect of the barrier oxide layer 208 is influenceed.Therefore, in the present embodiment, the hydrogen pretreatment technique
Temperature be less than 800 degrees Celsius, removing sample surfaces impurity and defect, improving epitaxial layer lattice quality simultaneously, reducing to resistance
Keep off the damage of oxide layer 208.
The technique that embedded source region and drain region 209 are formed in the opening 207 is selective epitaxial process.Described choosing
Selecting property epitaxy technique can be molecular beam epitaxy（MBE）Or ultra-high vacuum CVD（UHVCVD）.The selectivity
Epitaxy technique utilizes deposition materials adsorbing more than oxide or nitride and realize in silicon face by adjusting deposition parameter
The selectivity of epitaxial growth, one layer of growth has same or like lattice arrangement on the bottom of the opening 207 and sidewall surfaces
Monocrystal material.It should be noted that in the present embodiment, the barrier oxide layer 208 is monoatomic layer（mono atomic
layer）Or diatomic layer（double atomic layer）Structure, can be used as the miscellaneous of embedded source region and drain region 209
While matter diffusion impervious layer, the influence of the extension lattice quality to embedded source region and drain region 209 is reduced.
In the present embodiment, fin formula field effect transistor to be formed is PMOS transistor, the embedded source region and drain region
209 material is silicon or germanium silicon.The silicon materials or germanium silicon material are doped with p type impurity, and the p type impurity can be boron
Ion, indium ion or gallium ion.When the material in the embedded source region and drain region 209 is silicon, the source raised can be formed
Area and drain region, make the embedded source region and the volume in drain region 209 be more than the volume for the fin 201 that is etched, are conducive to subsequent source
The formation of conductive plunger in area and drain region, prevents from causing because the volume of fin 201 is too small conductive plunger and source region and drain region
Loose contact.When the material in the embedded source region and drain region 209 is germanium silicon, the embedded source region of formation and drain region 209 are not
Only be conducive to the formation of conductive plunger on subsequent source area and drain region, due also to the lattice constant of germanium silicon material is more than the crystalline substance of silicon materials
Lattice constant, can introduce compression stress in the channel region of PMOS fin formula field effect transistors, improve hole mobility.
In another embodiment, fin formula field effect transistor to be formed is nmos pass transistor, the embedded source region and leakage
The material in area 209 is silicon or carborundum.The silicon materials or carbofrax material are doped with N-type impurity, and the N-type impurity can
Think phosphonium ion, arsenic ion or antimony ion.When the material in the embedded source region and drain region 209 is silicon, with PMOS crystal
Tubing seemingly, can also form the source region raised and drain region, the embedded source region and the volume in drain region 209 is more than the fin that is etched
The volume in portion 201, is conducive to the formation of conductive plunger on follow-up source region and drain region, prevents from leading because the volume of fin 201 is too small
Cause conductive plunger and the loose contact in source region and drain region.When the material in the embedded source region and drain region is carborundum, formed
Embedded source region and drain region 209 not only contribute to the formation of conductive plunger on follow-up source region and drain region, due also to carborundum
Lattice constant is less than the lattice constant of silicon materials, and can introduce stretching in the channel region of NMOS fin formula field effect transistors should
Power, improves electron mobility.
In the present embodiment, due to before embedded source region and drain region 209 are formed, in the bottom and side of the opening 207
Wall surface is formed with barrier oxide layer 208.The barrier oxide layer 208 covers area 206 in embedded source region and drain region 209 with negative
Between introduce particle trap, in follow-up impurity activation or thermal anneal process, the barrier oxide layer 208 can be as miscellaneous
Matter diffusion impervious layer, prevents the embedded source region of fin formula field effect transistor and the impurity in drain region 209 from diffusing into described
It is negative to cover area 206, the negative doping concentration for covering area 206 of influence, be conducive to improving the performance of transistor.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and techniques of the disclosure above to skill of the present invention
Art scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, the skill according to the present invention
Any simple modifications, equivalents, and modifications that art is substantially made to above example, belong to the guarantor of technical solution of the present invention
Protect scope.
Claims (20)
1. a kind of forming method of fin formula field effect transistor, it is characterised in that including：
Semiconductor substrate is provided, the semiconductor substrate surface is with raised fin, the grid structure on the fin,
The top of fin and side wall described in the grid structure covering part；
The part fin of the grid structure both sides is etched, opening is formed；
The top surface and fin of barrier oxide layer on the bottom of the opening and sidewall surfaces formation barrier oxide layer, side wall
The top surface in portion is flushed；
After barrier oxide layer is formed, embedded source region and drain region, embedded source region and drain region covering are formed in the opening
The barrier oxide layer.
2. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the barrier oxide layer tool
There are monoatomic layer or diatomic Rotating fields.
3. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that in the bottom of the opening
Include with the technique of sidewall surfaces formation barrier oxide layer：
In the bottom of the opening and sidewall surfaces spraying deionized water；
Oxidizing gas, the oxidizing gas and deionized water formation oxidant are passed through, the bottom and side of the opening is aoxidized
The surface of wall；
The step of repeating above-mentioned spraying deionized water and be passed through oxidizing gas, until forming the barrier oxide layer.
4. the forming method of fin formula field effect transistor as claimed in claim 3, it is characterised in that the oxidizing gas is O3。
5. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that in the bottom of the opening
Technique with sidewall surfaces formation barrier oxide layer is wet oxidation.
6. the forming method of fin formula field effect transistor as claimed in claim 5, it is characterised in that the wet process oxidation technology
Using NH4OH、H2O2And H2O mixed solution.
7. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the grid structure includes
Gate dielectric layer, the gate electrode layer on the gate dielectric layer and the side positioned at the gate dielectric layer and gate electrode layer both sides
Wall.
8. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that the material of the side wall is
High dielectric constant material.
9. the forming method of fin formula field effect transistor as claimed in claim 8, it is characterised in that the high-k material
Expect for HfO2、Al2O3、ZrO2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.
10. the forming method of fin formula field effect transistor as claimed in claim 7, it is characterised in that the side wall covering
Part fin constitutes negative covering area.
11. the forming method of fin formula field effect transistor as claimed in claim 10, it is characterised in that the negative covering area
Doping concentration is identical with the doping concentration of the channel region of fin formula field effect transistor.
12. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include, is opened described
Before the bottom of mouth and sidewall surfaces formation barrier oxide layer, the natural oxidizing layer of the open bottom and sidewall surfaces is removed.
13. the forming method of fin formula field effect transistor as claimed in claim 12, it is characterised in that remove the natural oxygen
The technique for changing layer is wet etching.
14. the forming method of fin formula field effect transistor as claimed in claim 13, it is characterised in that the wet etching work
Skill uses HF solution, NH3With HF mixed solution or NF3With HF mixed solution.
15. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that also include, is opened described
Intraoral to be formed before embedded source region and drain region, bottom and side wall to the opening carry out hydrogen pretreatment.
16. the forming method of fin formula field effect transistor as claimed in claim 15, it is characterised in that the hydrogen pretreatment
Temperature be less than 800 degrees Celsius.
17. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the shape in the opening
It is selective epitaxial process into embedded source region and the technique in drain region.
18. the forming method of fin formula field effect transistor as claimed in claim 17, it is characterised in that the selective epitaxial
Technique is molecular beam epitaxy or ultra-high vacuum CVD.
19. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the embedded source region
Material with drain region is germanium silicon, carborundum or silicon.
20. the forming method of fin formula field effect transistor as claimed in claim 1, it is characterised in that the embedded source region
With drain region doped with N-type or p type impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310093720.2A CN104064467B (en) | 2013-03-21 | 2013-03-21 | The forming method of fin formula field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310093720.2A CN104064467B (en) | 2013-03-21 | 2013-03-21 | The forming method of fin formula field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104064467A CN104064467A (en) | 2014-09-24 |
| CN104064467B true CN104064467B (en) | 2017-08-25 |
Family
ID=51552127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310093720.2A Active CN104064467B (en) | 2013-03-21 | 2013-03-21 | The forming method of fin formula field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104064467B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9911849B2 (en) | 2015-12-03 | 2018-03-06 | International Business Machines Corporation | Transistor and method of forming same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479801A (en) * | 2010-11-22 | 2012-05-30 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| CN102543736A (en) * | 2010-12-15 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and method for manufacturing same |
| CN102903636A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of MOS (metal oxide semiconductor) transistor |
-
2013
- 2013-03-21 CN CN201310093720.2A patent/CN104064467B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102479801A (en) * | 2010-11-22 | 2012-05-30 | 中国科学院微电子研究所 | Semiconductor device and forming method thereof |
| CN102543736A (en) * | 2010-12-15 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and method for manufacturing same |
| CN102903636A (en) * | 2011-07-25 | 2013-01-30 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of MOS (metal oxide semiconductor) transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104064467A (en) | 2014-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9502530B2 (en) | Method of manufacturing semiconductor devices | |
| US8980719B2 (en) | Methods for doping fin field-effect transistors | |
| US8187928B2 (en) | Methods of forming integrated circuits | |
| US8652891B1 (en) | Semiconductor device and method of manufacturing the same | |
| US10312155B2 (en) | FinFET device and fabrication method thereof | |
| CN103928327B (en) | Fin formula field effect transistor and forming method thereof | |
| CN104701171B (en) | Fin formula field effect transistor and forming method thereof | |
| CN103632973B (en) | Semiconductor device and manufacture method thereof | |
| CN103855096B (en) | The forming method of CMOS transistor | |
| WO2015070555A1 (en) | Three-face source tunnel field-effect transistor and manufacturing method therefor | |
| US20150270399A1 (en) | Semiconductor structure and method for manufacturing the same | |
| CN110957220B (en) | Semiconductor structure and forming method thereof | |
| CN103943502B (en) | Fin formula field effect transistor and forming method thereof | |
| CN103325787B (en) | Cmos device and manufacturing method thereof | |
| CN106935505B (en) | The forming method of fin formula field effect transistor | |
| CN109087887B (en) | Semiconductor structure and forming method thereof | |
| CN108807179B (en) | Semiconductor structure and forming method thereof | |
| US8765540B2 (en) | Semiconductor structure and method for manufacturing the same | |
| CN104064467B (en) | The forming method of fin formula field effect transistor | |
| CN103928328B (en) | The forming method of fin formula field effect transistor | |
| CN104282562A (en) | Fin field effect transistor and forming method thereof | |
| CN105244375B (en) | PNIN/NPIP type SSOI TFET and preparation method with mutation tunnel junctions | |
| CN111162074B (en) | Semiconductor structure and forming method thereof | |
| CN111463275A (en) | Semiconductor structure and forming method thereof | |
| CN109037070A (en) | A kind of manufacturing method and semiconductor devices of semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |