CN111162074A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN111162074A
CN111162074A CN201811321624.8A CN201811321624A CN111162074A CN 111162074 A CN111162074 A CN 111162074A CN 201811321624 A CN201811321624 A CN 201811321624A CN 111162074 A CN111162074 A CN 111162074A
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semiconductor
region
semiconductor pillar
pmos
pillar
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CN111162074B (en
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming a base, wherein the base comprises a PMOS (P-channel metal oxide semiconductor) region, the base comprises a substrate and a semiconductor column protruding out of the substrate, the semiconductor column of the PMOS region comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the molar volume percentage of Ge in the second semiconductor column is greater than that of Ge in the first semiconductor column; forming a PMOS drain region in the bottom of the first semiconductor pillar in the PMOS region; forming a grid structure surrounding the semiconductor column after forming the PMOS drain region, wherein the grid structure of the PMOS region covers the junction of the first semiconductor column and the second semiconductor column and exposes the top of the second semiconductor column, and the semiconductor column covered by the grid structure is used as a channel layer; after the gate structure is formed, a PMOS source region is formed in the top of the second semiconductor pillar. The embodiment of the invention is beneficial to improving the stability problems of the PMOS transistor, such as hot carrier effect, self-heating effect and the like.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the channel length of transistors has to be shortened in order to accommodate the reduction of process nodes.
The shortening of the channel length of the transistor has the advantages of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is also shortened, and the controllability of the gate to the channel is deteriorated, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (short-channel leakage) is more likely to occur, and the channel leakage current of the transistor is increased.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to more power efficient three-dimensional transistors, such as Gate-all-around (GAA) transistors. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel, and can better inhibit a short-channel effect. The fully-wrapped Gate transistor includes a transverse Gate-all-around (LGAA) transistor and a Vertical Gate-all-around (VGAA) transistor, in which a channel of the VGAA extends in a direction perpendicular to a surface of a substrate, which is advantageous for improving an area utilization efficiency of a semiconductor structure, and thus is advantageous for realizing a further reduction in feature size.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize the performance of a semiconductor device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a base including a PMOS region, wherein the base includes a substrate and a semiconductor pillar protruding from the substrate, the semiconductor pillar of the PMOS region includes a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, and the molar volume percentage of Ge in the second semiconductor pillar is greater than that of Ge in the first semiconductor pillar; forming a PMOS drain region in the bottom of the first semiconductor pillar in the PMOS region; after the PMOS drain region is formed, a grid structure surrounding the semiconductor column is formed, the grid structure of the PMOS region covers the junction of the first semiconductor column and the second semiconductor column and exposes the top of the second semiconductor column, and the semiconductor column covered by the grid structure is used as a channel layer; and forming a PMOS source region in the top of the second semiconductor column after the gate structure is formed.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the semiconductor pillar of the PMOS region comprises a first semiconductor pillar and a second semiconductor pillar positioned on the first semiconductor pillar, and the molar volume percentage of Ge in the second semiconductor pillar is greater than that of Ge in the first semiconductor pillar; a PMOS drain region located within a bottom of the PMOS region first semiconductor pillar; a gate structure surrounding the semiconductor pillar, the gate structure covering a boundary between the first semiconductor pillar and the second semiconductor pillar and exposing a top of the second semiconductor pillar, the semiconductor pillar covered by the gate structure serving as a channel layer; a PMOS source region located within a top portion of the second semiconductor pillar.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the present invention, the semiconductor pillar in the PMOS region includes a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, a mol volume percentage of Ge in the second semiconductor pillar is greater than a mol volume percentage of Ge in the first semiconductor pillar, a channel layer is subsequently formed in the semiconductor pillar, a PMOS drain region is formed in a bottom of the first semiconductor pillar in the PMOS region, and a PMOS source region is formed in a top of the second semiconductor pillar, a mol volume percentage of Ge in the channel layer in the PMOS region near the source region is greater than a mol volume percentage of Ge in the channel layer near the drain region, in a semiconductor field, a voltage of the PMOS drain region is generally higher than that of the source region, so that an electric field in the channel layer near the drain region is stronger, and by making a mol volume percentage of Ge in the channel layer in the PMOS region near the source region higher, it is beneficial to improve mobility of carriers of the PMOS transistor near the source, thereby improving the electrical performance of the PMOS transistor; the mole volume percentage of Ge in the channel layer of the PMOS area close to the drain area is low, so that the mobility of the current Carrier of the channel layer of the PMOS area close to the drain area is low, the stability problems of Hot Carrier Effect (HCI), Self-Heating Effect (SHE) and the like of the channel layer of the PMOS transistor close to the drain area are improved, and the electrical performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic diagram of another semiconductor structure;
fig. 3 to 9 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The semiconductor device still has a problem of poor performance. The two semiconductor structures are combined to analyze the reason of poor performance of the device.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.
The semiconductor structure includes: the substrate comprises a PMOS region I, the substrate comprises a substrate 10 and a semiconductor column 15 protruding out of the substrate 10, and the PMOS region I semiconductor column 15 is made of Si; a drain region 11 located in a bottom of the semiconductor pillar 15; a gate structure 16 surrounding the semiconductor pillar 15, the gate structure 16 covering the semiconductor pillar 15 and exposing the top of the semiconductor pillar 15, the semiconductor pillar 15 covered by the gate structure 16 being a channel layer 12; a source region 13 located within the top of the semiconductor pillar 15.
The PMOS region I semiconductor pillar 15 is made of Si, and the PMOS region I channel layer 12 is made of Si, so that the carrier mobility of the PMOS transistor channel layer 12 is low, and accordingly, the probability of the PMOS transistor generating stability problems such as hot carrier effect and spontaneous heat effect is low, but the carrier mobility of the PMOS transistor channel layer 12 is low, which easily results in poor performance of the PMOS transistor.
Referring to fig. 2, a schematic diagram of another semiconductor structure is shown.
The semiconductor structure is the same as the semiconductor structure in fig. 1 and will not be described herein again. The semiconductor structure differs from the semiconductor structure in fig. 1 in that: the PMOS region I semiconductor pillar 25 is SiGe.
Correspondingly, the material of the PMOS region I channel layer 22 is also SiGe, and the SiGe material can provide tensile stress to the channel layer 22 of the PMOS transistor, so that the carrier mobility of the channel layer 22 of the PMOS transistor is high. In the semiconductor field, the voltage of the PMOS drain region 23 is usually higher than that of the source region 21, so the electric field in the channel layer 22 near the drain region 23 is stronger, and the carrier mobility in the channel layer 22 near the drain region 23 of the PMOS transistor is higher, which easily causes stability problems such as hot carrier effect and self-heating effect in the channel layer 22 near the drain region 23 of the PMOS transistor, thereby reducing the electrical performance of the semiconductor structure.
In order to solve the technical problem, in an embodiment of the present invention, the semiconductor pillar of the PMOS region includes a first semiconductor pillar and a second semiconductor pillar located on the first semiconductor pillar, a molar volume percentage of Ge in the second semiconductor pillar is greater than a molar volume percentage of Ge in the first semiconductor pillar, a channel layer is subsequently formed in the semiconductor pillar, a PMOS drain region is formed in a bottom of the first semiconductor pillar of the PMOS region, and a PMOS source region is formed in a top of the second semiconductor pillar, a molar volume percentage of Ge in the channel layer of the PMOS region near the source region is greater than a molar volume percentage of Ge in a bottom of the channel layer near the drain region, in a semiconductor field, a voltage of the PMOS drain region is generally higher than that of the source region, so that an electric field in the channel layer near the drain region is stronger, and by making the molar volume percentage of Ge in the channel layer of the PMOS region near the source region, it is beneficial to improve a mobility ratio of carriers of the channel layer, thereby improving the electrical performance of the PMOS transistor; the mole volume percentage of Ge in the channel layer of the PMOS region close to the drain region is low, so that the mobility of the current carrier of the channel layer of the PMOS region close to the drain region is low, the stability problems of hot carrier effect, spontaneous heat effect and the like of the channel layer of the PMOS transistor close to the drain region are improved, and the electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 3 to 9 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 3 to 5, a base is formed, which includes a PMOS region I, the base includes a substrate 112 (shown in fig. 5) and a semiconductor pillar 120 (shown in fig. 5) protruding from the substrate 112, the semiconductor pillar 120a of the PMOS region I includes a first semiconductor pillar 113 (shown in fig. 5) and a second semiconductor pillar 114 (shown in fig. 5) located on the first semiconductor pillar 113, and a molar volume percentage of Ge in the second semiconductor pillar 114 is greater than a molar volume percentage of Ge in the first semiconductor pillar 113.
After a channel layer is formed in the semiconductor pillar 120, a PMOS drain region is formed in the bottom of the PMOS region I first semiconductor pillar 113, and a PMOS source region is formed in the top of the second semiconductor pillar 114, the molar volume percentage of Ge in the channel layer of the PMOS region I near the source region is greater than the molar volume percentage of Ge in the channel layer near the drain region, in the semiconductor field, the voltage of the PMOS drain region is generally higher than that of the source region, so the electric field in the channel layer near the drain region is stronger, and by making the molar volume percentage of Ge in the channel layer of the PMOS region I near the source region higher, it is beneficial to improve the mobility of carriers of the PMOS transistor near the source region; the mole volume percentage of Ge in the channel layer of the PMOS region I close to the drain region is lower, so that the mobility of the current carrier of the channel layer of the PMOS region I close to the drain region is lower, and the stability problems of hot carrier effect, spontaneous heat effect and the like of the channel layer of the PMOS transistor close to the drain region are improved.
The substrate of the PMOS region I is used for forming a PMOS transistor.
It should be noted that, in this embodiment, the substrate further includes an NMOS area II, and the substrate of the NMOS area II is used to form an NMOS transistor.
The substrate 112 provides a process platform for subsequently forming semiconductor structures.
In this embodiment, the substrate 112 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The semiconductor pillars 120 are used to form a drain region, a source region, and a channel layer.
The first semiconductor pillars 113 are used to form drain regions and channel layers of PMOS and NMOS.
In this embodiment, the first semiconductor pillar 113 and the substrate 112 are obtained by etching the same semiconductor material layer, the first semiconductor pillar 113 and the substrate 112 are integrated into a single structure, and the substrate 112 is made of Si. In other embodiments, the material of the first semiconductor pillar and the substrate may also be different according to actual process requirements, and in order to further improve the carrier mobility of the PMOS transistor, the material of the first semiconductor pillar may be SiGe.
In this embodiment, the first semiconductor pillar 113 has a single-layer structure. That is, the first semiconductor pillar 113 includes only a single semiconductor layer, which can simplify the process flow and reduce the difficulty of the process operation.
In other embodiments, the first semiconductor pillar may further include a plurality of semiconductor layers sequentially disposed on the substrate, and in the first semiconductor pillar, the mol volume percentage of Ge in the semiconductor layers is gradually increased from a direction away from the second semiconductor pillar to a direction close to the second semiconductor pillar, so that the mol volume percentage of Ge in the first semiconductor pillar is sequentially decreased from top to bottom, which is beneficial to further improving stability problems of a hot carrier effect, a spontaneous heat effect, and the like of a channel layer of the PMOS transistor close to the drain region.
The second semiconductor pillars 114 are used to form PMOS source regions and channel layers.
The second semiconductor pillar 114 is made of SiGe, and the SiGe material can provide a compressive stress effect to the channel layer of the PMOS transistor, thereby facilitating to improve the carrier mobility of the PMOS transistor.
It should be noted that, in this embodiment, the second semiconductor pillar 114 includes a plurality of semiconductor layers (not shown) sequentially located on the first semiconductor pillar 113, and in the second semiconductor pillar 114, from a direction close to the first semiconductor pillar 113 to a direction away from the first semiconductor pillar 113, a mol volume percentage of Ge in the semiconductor layers gradually increases, so that a mol volume percentage of Ge in the second semiconductor pillar 114 sequentially decreases from top to bottom, which is beneficial to further improving mobility of channel layer carriers of the PMOS transistor close to the source region and improving stability problems such as channel layer hot carrier effect and spontaneous heat effect of the PMOS transistor close to the drain region. In other embodiments, the second semiconductor pillar may also include only a single semiconductor layer, which is advantageous for simplifying the process flow.
In this embodiment, the semiconductor pillar 120b of the NMOS region I includes a first semiconductor pillar 113 and a third semiconductor pillar 115 located on the first semiconductor pillar 113.
In this embodiment, the third semiconductor pillar 115 and the first semiconductor pillar 113 are made of the same material, and the third semiconductor pillar 115 is made of Si, so that the semiconductor pillar 120b in the NMOS region II is made of Si, which is not only beneficial to improving process compatibility, but also beneficial to improving carrier mobility of the channel layer in the NMOS region II.
Specifically, the step of forming the PMOS region I substrate includes:
referring to fig. 3, a first semiconductor material layer 100 is provided, and a second semiconductor material layer 110 is formed on the first semiconductor material layer 100, wherein a molar volume percentage of Ge in the second semiconductor material layer 110 is greater than a molar volume percentage of Ge in the first semiconductor material layer 100.
The first semiconductor material layer 100 is used for the subsequent formation of a substrate 112 and a first semiconductor pillar 113.
The second semiconductor material layer 110 is used for the subsequent formation of second semiconductor pillars 114.
In this embodiment, the step of forming the second semiconductor material layer 110 on the first semiconductor material layer 100 includes: a plurality of semiconductor material films (not shown) are sequentially grown on the first semiconductor material layer 100 using an epitaxial growth process, and the plurality of semiconductor material films serve as the second semiconductor material layer 110.
The film obtained by the epitaxial growth process has high purity and few defects, and is favorable for obtaining a single crystal film and improving the formation quality of the second semiconductor material layer 110.
In this embodiment, the second semiconductor material layer 110 is SiGe, and therefore, the gas used in the epitaxial growth process is SiH4、Si2H6、GeH4And Ge2H6A gas. By controlling the SiH4、Si2H6Gas and said GeH4、Ge2H6The proportion of gases, thereby enabling variation of the molar volume percentage of Ge in the different films of semiconductor material during said epitaxial growth. In this embodiment, with reference to fig. 4 in combination, after the forming of the second semiconductor material layer 110, the forming method further includes: removing the second semiconductor material layer 110 on the NMOS region II; and forming a third semiconductor material layer 111 on the first semiconductor material layer 100 of the NMOS region II, wherein the third semiconductor material layer 111 and the first semiconductor material layer 100 are made of the same material.
The first semiconductor material layer 100 and the third semiconductor material layer 111 of the NMOS area II are used to form the substrate 112 and the semiconductor pillar 120b of the NMOS area II.
In this embodiment, the material of the first semiconductor material layer 100 is Si, and the material of the third semiconductor material layer 111 is also Si correspondingly, so that after the semiconductor pillar 120b of the NMOS region II is formed subsequently, the carrier mobility of the NMOS transistor is improved.
In this embodiment, a wet etching process is adopted to remove the second semiconductor material layer 110 on the NMOS region II.
The wet etching process has a high etching rate, and the wet etching process has a high etching selectivity for SiGe material and Si, so that it is beneficial to completely remove the second semiconductor material layer 110 of the NMOS region II, and can reduce damage to the first semiconductor material layer 100 during the process of removing the second semiconductor material layer 110 of the NMOS region II.
In order to improve the film quality of the third semiconductor material layer 111 and obtain a single crystal film, in this example, an epitaxial growth process is used to form the third semiconductor material layer 111 on the first semiconductor material layer 100.
Referring to fig. 5, after the second semiconductor material layer 110 and the third semiconductor material layer 111 are formed, the second semiconductor material layer 110 and the first semiconductor material layer 100 are sequentially etched, and a substrate 112 and a semiconductor pillar 120a protruding from the substrate 112 are formed on the PMOS region I.
In this embodiment, the base further includes an NMOS area II, and therefore, in the step of etching the second semiconductor material layer 110 and the first semiconductor material layer 100, the third semiconductor material layer 111 and the first semiconductor material layer 100 in the NMOS area II are also sequentially etched, a substrate 112 and a semiconductor pillar 120b protruding from the substrate 112 are formed on the NMOS area II, and the semiconductor pillar 120b in the NMOS area II includes a first semiconductor pillar 113 and a third semiconductor pillar 115 located on the first semiconductor pillar 113.
The substrate 112 of the PMOS region I and the NMOS region II and the semiconductor pillar 120 protruding from the substrate 112 are formed in the same step, which is beneficial to improving process compatibility and process manufacturing efficiency.
In this embodiment, a dry etching process is adopted to sequentially etch the second semiconductor material layer 110 and the first semiconductor material layer 100 in the PMOS region I, and the third semiconductor material layer 111 and the first semiconductor material layer 100 in the NMOS region II, so as to form a substrate 112 and a semiconductor pillar 120 protruding from the substrate 112.
The dry etching process has better controllability of the etching profile, and is beneficial to enabling the appearances of the semiconductor pillars 120 and the substrate 112 to meet the process requirements. In other embodiments, according to actual process requirements, a wet etching process or a process combining a dry method and a wet method may also be used to etch the second semiconductor material layer and the first semiconductor material layer in the PMOS region, and the third semiconductor material layer and the first semiconductor material layer in the NMOS region.
In this embodiment, a buffer layer 121 (shown in fig. 5) and a hard mask layer 122 (shown in fig. 5) on the buffer layer 121 are further formed on the second semiconductor pillar 114 and the third semiconductor pillar 115.
The hard mask layer 122 is used as an etching mask for etching the second semiconductor material layer 110, the third semiconductor material layer 111, and the first semiconductor material layer 111 to form the substrate 112 and the semiconductor pillar 120, and the hard mask layer 122 can also protect the top of the semiconductor pillar 120 in a subsequent process. In this embodiment, the hard mask layer 122 is made of silicon nitride.
Since the silicon nitride material has a large stress when heated, the buffer layer 121 plays a role of stress buffering by forming the buffer layer 121 between the hard mask layer 122 and the second semiconductor pillar 114 and between the hard mask layer 122 and the third semiconductor pillar 115, thereby improving the adhesion between the hard mask layer 122 and the second semiconductor pillar 114, between the hard mask layer 122 and the third semiconductor pillar 115. In this embodiment, the buffer layer 121 is made of silicon oxide.
Referring to fig. 6, a PMOS drain region 125a is formed in the bottom of the PMOS region I first semiconductor pillar 113.
In this embodiment, the molar volume percentage of Ge in the second semiconductor pillar 114 is greater than the molar volume percentage of Ge in the first semiconductor pillar 113, so that after a channel layer is subsequently formed in the semiconductor pillar 120a of the PMOS region I, the molar volume percentage of Ge in the channel layer of the PMOS region I close to the drain region 125a is smaller, and in the semiconductor field, the voltage of the PMOS drain region is higher and the electric field is stronger, so that the carrier mobility of the channel layer of the PMOS transistor close to the drain region 125a is favorably reduced, and the probability of the PMOS transistor generating stability problems such as hot carrier effect, spontaneous heat effect and the like in the drain region 125a can be reduced.
Specifically, a PMOS region drain region 125a is formed in the bottom of the PMOS region I first semiconductor pillar 113 by an ion implantation process.
In this embodiment, the substrate further includes an NMOS region II, and therefore, the step of forming a PMOS drain region 125a in the bottom of the first semiconductor pillar 113 of the PMOS region I includes: forming a protective layer (not shown) on the substrate of the NMOS region II, and only exposing the substrate of the PMOS region I; performing first ion doping treatment on the bottom of the first semiconductor pillar 113 of the PMOS region I to form a PMOS region drain region 125 a; after forming the PMOS region I drain region 125a, the protection layer on the NMOS region II substrate is removed.
In this embodiment, after forming the PMOS drain region 125a, the forming method further includes: an NMOS drain region 125b is formed in the bottom of the NMOS region II first semiconductor pillar 113.
Specifically, the step of forming the NMOS drain region 125b includes: forming a protective layer on the substrate of the PMOS area I, and only exposing the substrate of the NMOS area II; performing second ion doping treatment on the bottom of the first semiconductor pillar 113 of the NMOS region II to form an NMOS drain region 125 b; after the NMOS drain region 125b is formed, the protection layer on the PMOS region I substrate is removed. In other embodiments, the PMOS drain region may also be formed after the NMOS drain region is formed.
The first ion doping process is used to form the PMOS drain region 125a, so the doping ions of the first ion doping process are P-type ions, wherein the P-type ions are B ions, Ga ions, or In ions; the second ion doping process is used to form the NMOS drain region 125b, so the doping ions of the second ion doping process are N-type ions, where the N-type ions are P ions, As ions, or Sb ions.
It should be noted that, during the process of forming the PMOS drain region 125a in the bottom of the PMOS region I first semiconductor pillar 113 and forming the NMOS drain region 125b in the bottom of the NMOS region II first semiconductor pillar 113, the substrate 112 is also exposed to the process environment, so that the ions are also doped into a portion of the substrate 112, so that the PMOS drain region 125a and the NMOS drain region 125b are also formed in a portion of the substrate 112. Moreover, the PMOS drain region 125a and the NMOS drain region 125b are also formed in a portion of the substrate 112, which is beneficial to reducing the difficulty of the subsequent process of forming a drain contact hole plug electrically connected to the PMOS drain region 125a and the NMOS drain region 125b, and improving the process compatibility.
Referring to fig. 7, in this embodiment, after the PMOS drain region 125a is formed, the forming method further includes: a first isolation layer 130 is formed on the substrate 112 exposed by the semiconductor pillar 120, and the first isolation layer 130 surrounds a portion of the PMOS drain region 125 a.
The first isolation layer 130 is used to isolate adjacent devices, and after a gate structure surrounding the semiconductor pillar 120 is formed subsequently, the first isolation layer 130 is also used to isolate the substrate 112 from the gate structure.
In this embodiment, the material of the first isolation layer 130 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the first isolation layer 130; in addition, the smaller dielectric constant of silicon oxide is also beneficial to improve the function of the first isolation layer 130 for isolating adjacent devices and isolating the substrate 112 and the gate structure. In other embodiments, the material of the first isolation layer may also be other insulating materials such as silicon nitride, silicon oxynitride, and the like.
In this embodiment, the substrate further includes an NMOS region II, and therefore, in the step of forming the first isolation layer 130, the first isolation layer 130 further surrounds a portion of the NMOS drain region 125 b.
Specifically, the step of forming the first isolation layer 130 includes: forming a first isolation film (not shown) on the substrate 112 exposed by the semiconductor pillar 120, the first isolation film surrounding the semiconductor pillar 120; the first isolation film is etched back, and the remaining first isolation film serves as the first isolation layer 130.
In this embodiment, the first isolation layer 130 surrounds a portion of the PMOS drain region 125a, and exposes a portion of the first semiconductor pillar 113, so that a gate structure of the subsequent PMOS region I can cover a boundary between the first semiconductor pillar 113 and the second semiconductor pillar 114, and a channel layer of the PMOS region I can cross over the second semiconductor pillar 114 and the first semiconductor pillar 113, so that a molar volume percentage of Ge in the channel layer of the PMOS region I near the drain region 125a is relatively low.
Referring to fig. 8, after the PMOS drain region 125a is formed, a gate structure 140 surrounding the semiconductor pillar 120 is formed, the gate structure 140 in the PMOS region I covers the boundary between the first semiconductor pillar 113 and the second semiconductor pillar 114 and exposes the top of the second semiconductor pillar 114, and the semiconductor pillar 120 covered by the gate structure 140 serves as a channel layer (not shown). Specifically, the gate structure 140 is formed on the first isolation layer 130.
In this embodiment, the gate structure 140 is a fully surrounding gate structure and covers the junction between the first semiconductor pillar 113 and the second semiconductor pillar 114, so that the channel layer of the PMOS region I can span the second semiconductor pillar 114 and the first semiconductor pillar 113, and the molar volume percentage of Ge in the channel layer of the PMOS region I close to the drain region 125a is lower, thereby being beneficial to improving the stability problems of the hot carrier effect, the spontaneous heat effect, and the like near the drain region 125a of the PMOS transistor; after a PMOS source region is formed in the top of the second semiconductor pillar 114, the molar volume percentage of Ge in the channel layer of the PMOS region I close to the source region is higher, which is beneficial to improving the carrier mobility of the PMOS transistor.
It should be noted that, in the present embodiment, the gate structure 140 of the NMOS region II also covers the boundary between the first semiconductor pillar 113 and the third semiconductor pillar 115 and exposes the top of the third semiconductor pillar 115.
The gate structure 140 exposes the tops of the second and third semiconductor pillars 114, 115, thereby enabling the subsequent formation of PMOS source regions in the tops of the second semiconductor pillars 114 and NMOS source regions in the tops of the third semiconductor pillars 115.
In this embodiment, the gate structure 140 is a metal gate structure, and the gate structure 140 includes a gate oxide layer 131 surrounding the semiconductor pillar 120, a gate dielectric layer 132 surrounding the gate oxide layer 131, and a gate electrode layer 133 surrounding the gate dielectric layer 132.
In this embodiment, the gate oxide layer 131 covers the exposed surface of the semiconductor pillar 120 of the first isolation layer 130.
In this embodiment, the gate oxide layer 131 is made of silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.
In this embodiment, the gate dielectric layer 132 is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the gate dielectric layer 132 is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
It should be noted that, in this embodiment, the gate dielectric layer 132 is further located between the first isolation layer 130 and the gate structure 140, because the gate dielectric layer 132 and the first isolation layer 130 are both made of insulating materials, the performance of the transistor is not affected, and the process flow is facilitated to be simplified. In other embodiments, the gate dielectric layer between the first isolation layer and the gate structure may be removed.
The gate electrode layer 133 is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the gate electrode layer 133 is made of W.
In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure comprises a gate oxide layer and a gate layer surrounding the gate oxide layer.
It should be noted that, in this embodiment, a hard mask layer 122 (shown in fig. 7) and a buffer layer 121 (shown in fig. 7) are further formed on the top of the semiconductor pillar 120, so that, after the first isolation layer 130 is formed and before the gate structure 140 is formed, the forming method further includes: the hard mask layer 122 and the buffer layer 121 are removed, and the surface of the semiconductor pillar 120 is exposed.
With continued reference to fig. 8, after the gate structure 140 is formed, a PMOS source region 145a is formed within the top of the second semiconductor pillar 114.
In this embodiment, the molar volume percentage of Ge in the channel layer of the PMOS region I close to the source region 145a is greater than the molar volume percentage of Ge in the channel layer close to the drain region 125a, so that the carrier mobility of the channel layer of the PMOS region I close to the source region 145a is higher, thereby improving the electrical performance of the PMOS transistor.
Specifically, a PMOS source region 145a is formed in the top of the second semiconductor pillar 114 using an ion implantation process.
In this embodiment, the substrate further includes an NMOS region II, so the step of forming a PMOS source region 145a in the top of the second semiconductor pillar 114 includes: forming a protection layer (not shown) covering the gate structure 140 of the NMOS region II and the top of the third semiconductor pillar 115, exposing only the top of the PMOS region I of the second semiconductor pillar 114; performing third ion doping treatment on the top of the second semiconductor column 114 in the PMOS region I to form a PMOS source region 145 a; after the PMOS region source region 145a is formed, the protection layer of the NMOS region II is removed.
In this embodiment, after forming the PMOS source region 145a, the forming method further includes: an NMOS source region 145b is formed within the top of the third semiconductor pillar 115.
Specifically, the step of forming the NMOS source region 145b includes: forming a protection layer (not shown) covering the top of the PMOS region I gate structure 140 and the second semiconductor pillar 114, exposing only the top of the third semiconductor pillar 115 of the NMOS region II; performing fourth ion doping treatment on the top of the third semiconductor column 115 in the NMOS region II to form an NMOS source region 145 b; after the NMOS source region 145b is formed, the protection layer of the PMOS region I is removed. In other embodiments, the source regions of the PMOS region may also be formed after the source regions of the NMOS region are formed.
The third ion doping treatment is the same as the doping ions of the first ion doping treatment, so the doping ions of the third ion doping treatment are also P-type ions, wherein the P-type ions are B ions, Ga ions or In ions; the fourth ion doping treatment is the same As the second ion doping treatment, and therefore the fourth ion doping treatment is an N-type ion, wherein the N-type ion is a P ion, an As ion or an Sb ion.
With reference to fig. 9, it should be noted that after the PMOS source region 145a is formed, the forming method further includes: forming a second isolation layer 150 surrounding the PMOS source region 145a, the second isolation layer 150 being located on the gate structure 140 and covering the top of the semiconductor pillar 120.
The second isolation layer 150 is used to provide a process platform for the subsequent formation of contact holes and contact hole plugs electrically connected to the PMOS source regions 145a, and the second isolation layer 150 is also used to isolate adjacent devices.
In this embodiment, the substrate further includes an NMOS region II, and therefore, in the step of forming the second isolation layer 150, the second isolation layer 150 further surrounds the NMOS source region 145 b.
In this embodiment, in order to improve process compatibility, the material of the second isolation layer 150 is the same as that of the first isolation layer 130, and the material of the second isolation layer 150 is correspondingly silicon oxide. In other embodiments, the material of the second isolation layer may also be other insulating materials such as silicon nitride, silicon oxynitride, and the like.
It should be noted that, referring to fig. 8 in combination, the gate oxide layer 131 covers the surface of the semiconductor pillar 120 exposed by the first isolation layer 130, so that, in the process of performing the third ion doping process on the top of the second semiconductor pillar 114 to form the PMOS region source region 145a and performing the fourth ion doping process on the top of the third semiconductor pillar 115 to form the NMOS source region 145b, the ions are also doped into the gate oxide layer 131 exposed by the gate structure 140. In order to reduce the influence on the electrical performance of the semiconductor structure, and to form a contact hole plug electrically connected to the PMOS source region 145a subsequently, in this embodiment, after forming the source PMOS source region 145a and before forming the second isolation layer 150, the forming method further includes: the gate oxide layer 131 exposed by the gate electrode layer 133 is removed.
In this embodiment, a dry etching process is adopted to remove the gate oxide layer 131 exposed from the gate electrode layer 133.
When the dry etching process is adopted, the bias voltage can be adjusted to adjust the amount of lateral etching, so that the gate oxide layer 131 on the top of the semiconductor column 120 can be removed, and the gate oxide layer 131 on the side wall of the semiconductor column 120 exposed by the gate electrode layer 133 can also be removed.
With continued reference to fig. 9, after forming the second isolation layer 150, etching the second isolation layer 150 on top of the PMOS source region 145a, and forming a contact hole (not shown) in the second isolation layer 150, the contact hole exposing the top of the PMOS source region 145 a; contact hole plugs 160 are formed within the contact holes.
The contact holes are used to provide spatial locations for forming the contact hole plugs 160.
In this embodiment, the substrate further includes an NMOS region II, and therefore, in the step of etching the second isolation layer 150 on the top of the PMOS source region 145a, the second isolation layer 150 on the top of the NMOS source region 145b is also etched, that is, the contact hole is also located in the second isolation layer 150 in the NMOS region II.
The contact hole plugs 160 are used to electrically connect with the PMOS source regions 145 a. In this embodiment, the contact hole plug 160 is further formed in the contact hole of the NMOS region II, and the contact hole plug 160 is further electrically connected to the NMOS source region 145 b.
In this embodiment, the contact hole plug 160 is made of tungsten. In other embodiments, the material of the contact hole plug may also be one or more of metal nitride, titanium nitride and thallium nitride.
After the contact hole is formed, before the contact hole plug 160 is formed in the contact hole, the forming method further includes: silicide layers 155 are formed on the surfaces of PMOS source regions 145a and NMOS source regions 145b exposed by the contact holes.
The silicide layer 155 is located on the surfaces of the PMOS source region 145a and the NMOS source region 145b exposed by the contact hole, and is beneficial to reducing the contact resistance between the PMOS source region 145a and the contact hole plug 160, and between the NMOS source region 145b and the contact hole plug 160 when the contact hole plug 160 electrically connected with the PMOS source region 145a and the NMOS source region 145b is formed.
In this embodiment, the material of the silicide layer 155 may be TiSi, NiSi, CoSi, or the like.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 9, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a base including a PMOS region I, the base including a substrate 112 and a semiconductor pillar 120 protruding from the substrate 112, the semiconductor pillar 120a of the PMOS region I including a first semiconductor pillar 113 and a second semiconductor pillar 114 located on the first semiconductor pillar 113, a molar volume percentage of Ge in the second semiconductor pillar 114 being greater than a molar volume percentage of Ge in the first semiconductor pillar 113; a PMOS drain region 125a located within a bottom portion of the PMOS region I first semiconductor pillar 113; a gate structure 140 surrounding the semiconductor pillar 120, wherein the gate structure 140 covers the boundary between the first semiconductor pillar 113 and the second semiconductor pillar 114 and exposes the top of the second semiconductor pillar 114, and the semiconductor pillar 120 covered by the gate structure 140 serves as a channel layer (not shown); a PMOS source region 145a located within a top portion of the second semiconductor pillar 114.
In the semiconductor field, the voltage of the PMOS drain region 145a is generally higher than that of the source region 125a, the electric field near the drain region 145a is stronger, the molar volume percentage of Ge in the channel layer of the PMOS region I near the source region 145a is larger than that of Ge in the channel layer near the drain region 125a by making the molar volume percentage of Ge in the second semiconductor pillar 114 larger than that of Ge in the first semiconductor pillar 113, and the molar volume percentage of Ge in the channel layer of the PMOS region I near the source region 145a is higher, which is beneficial to improving the mobility of carriers in the channel layer of the PMOS transistor near the source region 145a, thereby improving the electrical performance of the PMOS transistor; the mole volume percentage of Ge in the channel layer of the PMOS region I close to the drain region 125a is low, which is beneficial to making the mobility of the channel layer current carrier of the PMOS region I close to the drain region 125a low, thereby being beneficial to improving the stability problems of hot carrier effect, spontaneous heat effect and the like near the drain region 125a of the PMOS transistor, and further improving the electrical property of the semiconductor structure.
The substrate of the PMOS region I is used for forming a PMOS transistor. It should be noted that, in this embodiment, the substrate further includes an NMOS region II, and the substrate of the NMOS region II is used to form an NMOS transistor.
In this embodiment, the semiconductor pillar 120b of the NMOS region II includes a first semiconductor pillar 113 and a third semiconductor pillar 115 located on the first semiconductor pillar 113.
The semiconductor structure further includes: an NMOS drain region 125b located within the bottom of the NMOS region II first semiconductor pillar 113; an NMOS source region 145b located within a top portion of the third semiconductor pillar 115.
The substrate 112 provides a process platform for the formation of semiconductor structures.
In this embodiment, the substrate 112 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.
The PMOS region I-semiconductor pillar 120a is used to form the PMOS drain region 125a, the source region 145a, and the channel layer.
In this embodiment, the semiconductor pillar 120a of the PMOS region I includes a first semiconductor pillar 113 and a second semiconductor pillar 114 located on the first semiconductor pillar 113, and a molar volume percentage of Ge in the second semiconductor pillar 114 is greater than a molar volume percentage of Ge in the first semiconductor pillar 113.
The first semiconductor pillar 113 of the PMOS region I is used to form a PMOS drain region 125a and a channel layer, and the first semiconductor pillar 113 of the NMOS region II is used to form an NMOS drain region 125b and a channel layer.
In this embodiment, the first semiconductor pillar 113 and the substrate 112 are obtained by etching the same semiconductor material layer, the first semiconductor pillar 113 and the substrate 112 are integrated into a single structure, and the substrate 112 is also made of Si.
In this embodiment, the first semiconductor pillar 113 has a single-layer structure, that is, the first semiconductor pillar 113 only includes a single semiconductor layer (not shown), so that the process flow can be simplified and the difficulty of the process operation can be reduced. In other embodiments, the first semiconductor pillar may further include a plurality of semiconductor layers sequentially located on the substrate, and in the first semiconductor pillar, a molar volume percentage of Ge in the semiconductor layers is gradually increased from a direction away from the second semiconductor pillar to a direction close to the second semiconductor pillar, so that the molar volume percentage of Ge in the first semiconductor pillar is sequentially decreased from top to bottom, which is beneficial to further improving stability problems such as a hot carrier effect and a spontaneous heat effect of the PMOS transistor close to the channel layer of the drain region.
The second semiconductor pillar 114 is used to form a PMOS source region 145a and a channel layer.
The second semiconductor pillar 114 is made of SiGe, and the SiGe material can provide a compressive stress effect to the channel layer of the PMOS transistor, thereby facilitating to improve the carrier mobility of the PMOS transistor.
It should be noted that, in this embodiment, the second semiconductor pillar 114 includes a plurality of semiconductor layers sequentially located on the first semiconductor pillar 113, and in the second semiconductor pillar 114, the mol volume percentage of Ge in the semiconductor layers gradually increases from the direction close to the first semiconductor pillar 113 to the direction away from the first semiconductor pillar 113, so that the mol volume percentage of Ge in the second semiconductor pillar 114 sequentially decreases from top to bottom, which is beneficial to further improve the mobility of channel layer carriers of the PMOS transistor close to the source region 145a and to improve stability problems such as channel layer hot carrier effect and spontaneous heat effect of the PMOS transistor close to the drain region 125 a. In other embodiments, the second semiconductor pillar may also include only a single semiconductor layer, which is advantageous for simplifying the process flow.
In this embodiment, the third semiconductor pillar 115 and the first semiconductor pillar 113 are made of the same material, and the third semiconductor pillar 115 is made of Si, so that the semiconductor pillar 120b in the NMOS region II is made of Si, which is beneficial to improving process compatibility and carrier mobility of an NMOS transistor channel layer.
P-type ions are doped In the PMOS drain region 125a, wherein the P-type ions are B ions, Ga ions or In ions; the NMOS drain region 125b is doped with N-type ions, wherein the N-type ions are P ions, As ions, or Sb ions.
It should be noted that the PMOS drain region 125a and the NMOS drain region 125b are formed by ion doping the bottom of the first semiconductor pillar 113, and during the ion doping process, the substrate 112 is also exposed to the process environment, so that the ions are also doped into a portion of the substrate 112, so that the PMOS drain region 125a and the NMOS drain region 125b are also located in a portion of the substrate 112. Moreover, the PMOS drain region 125a and the NMOS drain region 125b are also located in a portion of the substrate 112, which is beneficial to reducing the process difficulty of forming a drain contact hole plug electrically connected to the PMOS drain region 125a and the NMOS drain region 125b, and improving process compatibility.
It should be further noted that, in this embodiment, the semiconductor structure further includes: a first isolation layer 130 disposed between the substrate 112 and the gate structure 140 and surrounding a portion of the PMOS drain region 125 a.
The first isolation layer 130 is used to isolate adjacent devices, and the first isolation layer 130 is also used to isolate the substrate 112 from the gate structure 140.
In this embodiment, the material of the first isolation layer 130 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the forming difficulty and the process cost of the first isolation layer 130; in addition, the smaller dielectric constant of silicon oxide is also beneficial to improve the function of the first isolation layer 130 for isolating adjacent devices, the isolation substrate 112 and the gate structure 140. In other embodiments, the material of the first isolation layer may also be other insulating materials such as silicon nitride, silicon oxynitride, and the like.
In this embodiment, the substrate further includes an NMOS region II, and therefore, the first isolation layer 130 correspondingly further surrounds a portion of the NMOS drain region 125 b.
In this embodiment, the first isolation layer 130 surrounds a portion of the PMOS drain region 125a, exposing a portion of the first semiconductor pillar 113, so that the gate structure of the PMOS region I can cover the boundary between the first semiconductor pillar 113 and the second semiconductor pillar 114, and therefore the channel layer of the PMOS region I can span the second semiconductor pillar 114 and the first semiconductor pillar 113 to make the PMOS region I have a lower Ge molar volume percentage near the drain region 125 a.
In this embodiment, the gate structure 140 is a fully-surrounding gate structure, and covers the junction between the first semiconductor pillar 113 and the second semiconductor pillar 114, so that the channel layer of the PMOS region I can cross over the second semiconductor pillar 114 and the first semiconductor pillar 113, and the molar volume percentage of Ge in the channel layer of the PMOS region I close to the drain region 125a is lower, thereby being beneficial to improving the stability problems of the hot carrier effect, the spontaneous heat effect, and the like near the drain region 125a of the PMOS transistor; the molar volume percentage of Ge in the channel layer of the PMOS region I close to the source region 145a is high, which is beneficial to improving the carrier mobility of the PMOS transistor.
It should be noted that in the present embodiment, the gate structure 140 of the NMOS region II also covers the boundary between the first semiconductor pillar 113 and the third semiconductor pillar 115, and exposes the top of the third semiconductor pillar 115.
The gate structure 140 exposes the tops of the second semiconductor pillar 114 and the third semiconductor pillar 115, thereby enabling the PMOS source region 145a to be formed in the top of the second semiconductor pillar 114 and the NMOS source region 145b to be formed in the top of the third semiconductor pillar 115.
In this embodiment, the gate structure 140 is a metal gate structure, and the gate structure 140 includes a gate oxide layer 131 surrounding the semiconductor pillar 120, a gate dielectric layer 132 surrounding the gate oxide layer 131, and a gate electrode layer 133 surrounding the gate dielectric layer 132.
In this embodiment, the gate oxide layer 131 is made of silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.
In this embodiment, the gate dielectric layer 132 is made of a high-k dielectric material; wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. Specifically, the gate dielectric layer 132 is made of HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from ZrO2HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3And the like.
In this embodiment, the gate dielectric layer 132 is further located between the first isolation layer 130 and the gate structure 140, because the gate dielectric layer 132 and the first isolation layer 130 are both made of insulating materials, the performance of the transistor is not affected, and the process flow is facilitated to be simplified. In other embodiments, the gate dielectric layer may also be located only between the gate oxide layer and the gate electrode layer.
The gate electrode layer 133 is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the gate electrode layer 133 is made of W.
In other embodiments, the gate structure may also be a polysilicon gate structure. Correspondingly, the gate structure comprises a gate oxide layer and a gate layer surrounding the gate oxide layer.
In this embodiment, the PMOS source region 145a is located in the top of the second semiconductor pillar 114, and the NMOS source region 145b is located in the top of the third semiconductor pillar 115.
The doping ions in the PMOS source region 145a and the drain region 125a are the same, the doping ions in the PMOS source region 145b and the drain region 125b are the same, and the doping ions in the PMOS source region 145a and the NMOS source region 145b may specifically refer to the description of the doping ions in the PMOS drain region 125a and the NMOS drain region 125b, which is not repeated herein.
It should be further noted that the semiconductor structure further includes: a second isolation layer 150 surrounding the PMOS source region 145a, the second isolation layer 150 being located on the gate structure 140 and the top of the second isolation layer 150 being higher than the top of the semiconductor pillar 120; and a contact hole plug 160 located in the second isolation layer 150 and electrically connected to the PMOS source region 145 a.
The second isolation layer 150 is used to provide a process platform for the formation of the contact hole plug 160, and the second isolation layer 150 is also used to isolate adjacent devices.
In this embodiment, the substrate further includes an NMOS region II, and thus, the second isolation layer 150 further surrounds the NMOS source region 145 b.
In this embodiment, in order to improve process compatibility, the material of the second isolation layer 150 is the same as that of the first isolation layer 130, and the material of the second isolation layer 150 is correspondingly silicon oxide. In other embodiments, the material of the second isolation layer may also be other insulating materials such as silicon nitride, silicon oxynitride, and the like.
The contact hole plugs 160 are electrically connected to the PMOS source regions 145 a. Accordingly, the contact hole plug 160 is also located in the second isolation layer 150 of the NMOS region II, and the contact hole plug 160 is also electrically connected to the NMOS source region 145 b.
In this embodiment, the contact hole plug 160 is made of tungsten. In other embodiments, the material of the contact hole plug may also be one or more of metal nitride, titanium nitride and thallium nitride.
In addition, in this embodiment, the semiconductor structure further includes: and a silicide layer 155 between the PMOS source region 145a and the contact hole plug 160, and the NMOS source region 145b and the contact hole plug 160.
The silicide layer 155 serves to reduce contact resistance of the PMOS source region 145a and the contact hole plug 160, and the NMOS source region 145b and the contact hole plug 160.
In this embodiment, the material of the silicide layer 155 may be TiSi, NiSi, CoSi, or the like.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
forming a base, wherein the base comprises a PMOS (P-channel metal oxide semiconductor) region, the base comprises a substrate and a semiconductor column protruding out of the substrate, the semiconductor column of the PMOS region comprises a first semiconductor column and a second semiconductor column positioned on the first semiconductor column, and the molar volume percentage of Ge in the second semiconductor column is greater than that in the first semiconductor column;
forming a PMOS drain region in the bottom of the first semiconductor pillar in the PMOS region;
after the PMOS drain region is formed, a grid structure surrounding the semiconductor column is formed, the grid structure of the PMOS region covers the junction of the first semiconductor column and the second semiconductor column and exposes the top of the second semiconductor column, and the semiconductor column covered by the grid structure is used as a channel layer;
and forming a PMOS source region in the top of the second semiconductor column after the gate structure is formed.
2. The method of forming a semiconductor structure according to claim 1, wherein the second semiconductor pillar includes a plurality of semiconductor layers sequentially located on the first semiconductor pillar, and wherein, in the second semiconductor pillar, a molar volume percentage of Ge in a semiconductor layer gradually increases from a direction close to the first semiconductor pillar to a direction away from the first semiconductor pillar.
3. The method of claim 1 or 2, wherein the first semiconductor pillar comprises a plurality of semiconductor layers sequentially located on the substrate, and wherein a molar volume percentage of Ge in a semiconductor layer gradually increases in the first semiconductor pillar from a direction away from the second semiconductor pillar to a direction closer to the second semiconductor pillar.
4. The method of forming a semiconductor structure of claim 1, wherein a material of the first semiconductor pillar is Si or SiGe.
5. The method of forming a semiconductor structure according to claim 1, wherein a material of the second semiconductor pillar is SiGe.
6. The method of forming a semiconductor structure of claim 1, wherein forming the PMOS region base comprises: providing a first semiconductor material layer, and forming a second semiconductor material layer on the first semiconductor material layer, wherein the molar volume percentage of Ge in the second semiconductor material layer is larger than that of Ge in the first semiconductor material layer;
and sequentially etching the second semiconductor material layer and the first semiconductor material layer, and forming a substrate and a semiconductor column protruding out of the substrate on the PMOS region.
7. The method for forming a semiconductor structure according to claim 6, wherein the second semiconductor material layer and the first semiconductor material layer are sequentially etched by a dry etching process.
8. The method of claim 6, wherein the process of forming the second layer of semiconductor material on the first layer of semiconductor material is an epitaxial growth process.
9. The method of claim 8, wherein the second semiconductor material layer is SiGe, and the epitaxial growth process uses SiH as a gas4、Si2H6、GeH4And Ge2H6A gas.
10. The method of forming a semiconductor structure of claim 6, wherein the substrate further comprises an NMOS region;
the step of forming the NMOS region substrate comprises the following steps: after the second semiconductor material layer is formed, removing the second semiconductor material layer on the NMOS area; forming a third semiconductor material layer on the first semiconductor material layer of the NMOS region, wherein the third semiconductor material layer and the first semiconductor material layer are made of the same material;
in the process of etching the second semiconductor material layer and the first semiconductor material layer of the PMOS region, sequentially etching the third semiconductor material layer and the first semiconductor material layer of the NMOS region, and forming the substrate and a semiconductor column protruding out of the substrate on the NMOS region, wherein the semiconductor column of the NMOS region comprises a first semiconductor column and a third semiconductor column positioned on the first semiconductor column;
forming an NMOS drain region in the bottom of the first semiconductor pillar of the NMOS region;
in the step of forming the gate structure, the gate structure also covers the boundary of the first semiconductor pillar and the third semiconductor pillar and exposes the top of the third semiconductor pillar;
after the gate structure is formed, the forming method further comprises: and forming an NMOS source region in the top of the third semiconductor pillar.
11. The method of forming a semiconductor structure of claim 1, wherein after forming the PMOS drain region and before forming the gate structure, the method further comprises: forming a first isolation layer on the substrate exposed out of the semiconductor pillar, wherein the first isolation layer surrounds part of the PMOS drain region;
in the step of forming a gate structure surrounding the semiconductor pillar, the gate structure is formed on the first isolation layer.
12. The method of forming a semiconductor structure of claim 1, wherein the method of forming further comprises, after forming the PMOS source region: forming a second isolation layer surrounding the PMOS source region, wherein the second isolation layer is positioned on the grid structure and covers the top of the semiconductor pillar;
etching the second isolation layer on the top of the PMOS source region, and forming a contact hole in the second isolation layer, wherein the contact hole exposes the top of the PMOS source region;
and forming a contact hole plug in the contact hole.
13. A semiconductor structure, comprising:
the semiconductor pillar of the PMOS region comprises a first semiconductor pillar and a second semiconductor pillar positioned on the first semiconductor pillar, and the molar volume percentage of Ge in the second semiconductor pillar is greater than that of Ge in the first semiconductor pillar;
a PMOS drain region located within a bottom of the PMOS region first semiconductor pillar;
a gate structure surrounding the semiconductor pillar, the gate structure covering a boundary between the first semiconductor pillar and the second semiconductor pillar and exposing a top of the second semiconductor pillar, the semiconductor pillar covered by the gate structure serving as a channel layer;
a PMOS source region located within a top portion of the second semiconductor pillar.
14. The semiconductor structure of claim 13, wherein the second semiconductor pillar comprises a plurality of semiconductor layers sequentially located on the first semiconductor pillar, and wherein a molar volume percentage of Ge in a semiconductor layer gradually increases in the second semiconductor pillar from near the first semiconductor pillar to far away from the first semiconductor pillar.
15. The semiconductor structure of claim 13 or 14, wherein the first semiconductor pillar comprises a plurality of semiconductor layers sequentially located on the substrate, and wherein, in the first semiconductor pillar, a molar volume percentage of Ge in a semiconductor layer gradually increases from a direction away from the second semiconductor pillar to a direction close to the second semiconductor pillar.
16. The semiconductor structure of claim 13, wherein the material of the first semiconductor pillar is Si or SiGe.
17. The semiconductor structure of claim 13, wherein the material of the second semiconductor pillar is SiGe.
18. The semiconductor structure of claim 13, wherein the substrate further comprises an NMOS region;
the semiconductor pillar of the NMOS region comprises a first semiconductor pillar and a third semiconductor pillar positioned on the first semiconductor pillar, and the third semiconductor pillar and the first semiconductor pillar are made of the same material;
the gate structure also covers the intersection of the first semiconductor pillar and a third semiconductor pillar and exposes the top of the third semiconductor pillar;
the semiconductor structure further includes: an NMOS drain region located within a bottom of the NMOS region first semiconductor pillar; an NMOS source region located within a top portion of the third semiconductor pillar.
19. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: and the first isolation layer is positioned between the substrate and the gate structure and surrounds part of the PMOS drain region.
20. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: the second isolation layer surrounds the PMOS source region, is positioned on the grid structure and has the top higher than the top of the semiconductor column;
and the contact hole plug is positioned in the second isolation layer and is electrically connected with the PMOS source region.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001171A1 (en) * 2006-06-30 2008-01-03 Tsutomu Tezuka Field effect transistor, integrated circuit element, and method for manufacturing the same
US20140175543A1 (en) * 2012-12-20 2014-06-26 Glenn A. Glass Conversion of thin transistor elements from silicon to silicon germanium
CN104134697A (en) * 2014-08-11 2014-11-05 北京大学 Asymmetric Schottky source drain transistor and preparing method thereof
CN104241371A (en) * 2014-07-31 2014-12-24 上海华力微电子有限公司 Nanowire transistor
CN105810720A (en) * 2015-01-16 2016-07-27 台湾积体电路制造股份有限公司 Inducing localized strain in vertical nanowire transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080001171A1 (en) * 2006-06-30 2008-01-03 Tsutomu Tezuka Field effect transistor, integrated circuit element, and method for manufacturing the same
US20140175543A1 (en) * 2012-12-20 2014-06-26 Glenn A. Glass Conversion of thin transistor elements from silicon to silicon germanium
CN104241371A (en) * 2014-07-31 2014-12-24 上海华力微电子有限公司 Nanowire transistor
CN104134697A (en) * 2014-08-11 2014-11-05 北京大学 Asymmetric Schottky source drain transistor and preparing method thereof
CN105810720A (en) * 2015-01-16 2016-07-27 台湾积体电路制造股份有限公司 Inducing localized strain in vertical nanowire transistors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471292A (en) * 2021-07-02 2021-10-01 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof
CN113471292B (en) * 2021-07-02 2023-10-24 长鑫存储技术有限公司 Semiconductor structure and manufacturing method thereof

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