CN104465377A - Pmos transistor and forming method thereof - Google Patents
Pmos transistor and forming method thereof Download PDFInfo
- Publication number
- CN104465377A CN104465377A CN201310425758.5A CN201310425758A CN104465377A CN 104465377 A CN104465377 A CN 104465377A CN 201310425758 A CN201310425758 A CN 201310425758A CN 104465377 A CN104465377 A CN 104465377A
- Authority
- CN
- China
- Prior art keywords
- semiconductor layer
- layer
- pmos transistor
- transistor according
- grid structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 192
- 239000000463 material Substances 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 230000000873 masking effect Effects 0.000 claims description 35
- 150000002500 ions Chemical class 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 31
- 239000010703 silicon Substances 0.000 claims description 31
- 238000005468 ion implantation Methods 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 12
- 238000002347 injection Methods 0.000 claims description 9
- 239000007924 injection Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000003384 imaging method Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 238000005516 engineering process Methods 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 239000002800 charge carrier Substances 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 230000005012 migration Effects 0.000 description 4
- 238000013508 migration Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
A PMOS transistor and a forming method thereof are provided; the PMOS transistor forming method comprises the following steps: providing a semiconductor substrate; forming a first semiconductor layer on a surface of the semiconductor substrate; forming an imaging mask layer on a surface of the first semiconductor layer so as to cover certain part of the first semiconductor layer; using the imaging mask layer as a mask so as to etch the first semiconductor layer, thus forming a first groove exposing certain part of the surface of the semiconductor substrate; forming a second semiconductor layer in the first groove, and an energy gap of the second semiconductor layer material is bigger than that of the first semiconductor layer material; forming a medium layer on a surface of the second semiconductor layer, a surface of the medium layer is flush with that of the imaging mask layer; removing the imaging mask layer so as to form a second groove; forming a grid electrode structure in the second groove; removing medium layer on two sides of the grid electrode so as to form a source electrode and a drain electrode in the second semiconductor layer; the PMOS transistor forming method can improve the performance of the PMOS transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of PMOS transistor and forming method thereof.Background technology
MOS transistor is most basic electronic component in integrated circuit, and the performance of performance to whole chip of MOS transistor has tremendous influence.
Please refer to Fig. 1, is the structural representation of the MOS transistor of prior art.
Described MOS transistor comprises: Semiconductor substrate 10; Be positioned at the grid structure 20 on Semiconductor substrate 10 surface, described grid structure 20 comprises the gate dielectric layer 21 being positioned at Semiconductor substrate 10 surface and the grid 22 being positioned at described gate dielectric layer 21 surface; Be positioned at the side wall 30 of grid structure 20 both sides sidewall surfaces; Be positioned at source electrode and the drain electrode 40 of the Semiconductor substrate 10 of described grid structure 20 both sides.Different according to MOS transistor carriers type, described metal-oxide-semiconductor can be nmos pass transistor or PMOS transistor, and the charge carrier of described nmos pass transistor is electronics, and the charge carrier of PMOS transistor is hole.
The material of the Semiconductor substrate 10 adopted in prior art is generally silicon, i.e. channel region material below the grid structure 20 of described MOS transistor is silicon.
And due in nmos pass transistor, charge carrier is electronics, in silicon, mobility is comparatively large, and nmos pass transistor has higher saturation current; And in PMOS transistor, charge carrier is hole, the mobility of hole in silicon is lower, causes the saturation current of PMOS transistor lower, and the performance of described PMOS transistor needs further to be improved.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, improves the performance of PMOS transistor.
For solving the problem, the invention provides a kind of formation method of PMOS transistor, comprising: Semiconductor substrate is provided; The first semiconductor layer is formed at described semiconductor substrate surface; Patterned masking layer is formed, described Patterned masking layer cover part first semiconductor layer in described first semiconductor layer surface; With described Patterned masking layer for mask, etch described first semiconductor layer, form the first groove, described first groove exposes the surface of part semiconductor substrate; In described first groove, form the second semiconductor layer, the energy gap of the material of described second semiconductor layer is greater than the energy gap of the material of the first semiconductor layer; Form dielectric layer in described second semiconductor layer surface, the surface of described dielectric layer flushes with the surface of Patterned masking layer; Remove described Patterned masking layer, form the second groove; Grid structure is formed in described second groove; Remove the dielectric layer of described grid structure both sides, in the semiconductor layer of described grid structure both sides second, form source electrode and drain electrode.
Optionally, the material of described first semiconductor layer is SiGe.
Optionally, the thickness of described first semiconductor layer is 2nm ~ 200nm.
Optionally, described Patterned masking layer comprises the silicon oxide layer being positioned at described first semiconductor layer surface and the silicon nitride layer being positioned at described silicon oxide layer surface.
Optionally, the material of described second semiconductor layer is silicon.
Optionally, the technique forming the second semiconductor layer in described first groove is selectivity depositing operation.
Optionally, the surface of described second semiconductor layer flushes with the surface of the first semiconductor layer.
Optionally, the method forming described dielectric layer comprises: filled media material in described first groove, and described dielectric material fills full first groove and the surface of cover graphics mask layer; With the surface of described Patterned masking layer for stop-layer, adopt chemical machinery masking process to carry out planarization to described dielectric material, form described dielectric layer.
Optionally, the material of described dielectric layer is silica.
Optionally, after removing the dielectric layer of described grid structure both sides, before forming described source electrode and drain electrode, light dope ion implantation and pocket ion implantation is carried out in the second semiconductor layer of described grid structure both sides, form light doping section and pocket region respectively, described pocket region surrounds described light doping section.
Optionally, the ionic type of described light dope ion implantation is not identical with the ionic type of pocket ion implantation.
Optionally, the method forming described source electrode and drain electrode comprises: form side wall in described grid structure both sides sidewall surfaces, with described grid structure and side wall for mask, carries out heavy doping ion injection in the second semiconductor layer of described grid structure both sides.
Optionally, the ionic type of described heavy doping ion injection is identical with the ionic type of light dope ion implantation.
Optionally, part source electrode and drain electrode are positioned at Semiconductor substrate.
For solving the problem, the present invention also provides a kind of transistor adopting said method to be formed, and comprising: Semiconductor substrate; First semiconductor layer of cover part semiconductor substrate surface; Be positioned at the second semiconductor layer of the semiconductor substrate surface of described first semiconductor layer both sides, the energy gap of the material of described second semiconductor layer is greater than the energy gap of the material of the first semiconductor layer; Be positioned at the grid structure of described first semiconductor layer surface; Be positioned at source electrode and the drain electrode of the second semiconductor layer of described grid structure both sides.
Optionally, the material of described first semiconductor layer is germanium silicon, and the material of the second semiconductor layer is silicon.
Optional volume, the surface of described second semiconductor layer flushes with the surface of the first semiconductor layer.
Optionally, also comprise light doping section and the pocket region of the second semiconductor layer being positioned at grid structure both sides, described pocket region surrounds described light doping section, and the Doped ions type in described light doping section is not identical with the Doped ions type in pocket region.
Optionally, described source electrode is identical with the Doped ions type in light doping section with the Doped ions type in drain electrode.
Optionally, part source electrode and drain electrode are positioned at Semiconductor substrate.
Compared with prior art, technical scheme of the present invention has the following advantages:
After technical scheme of the present invention forms the first semiconductor layer on a semiconductor substrate, remove part first semiconductor layer, form the first groove, the second semiconductor layer is formed in described first groove, the energy gap of the material of described second semiconductor layer is greater than the energy gap of the material of the first semiconductor layer, follow-up source electrode and the drain electrode forming PMOS transistor in described second semiconductor layer.With directly in described first semiconductor layer, form source electrode and compare with drain electrode, material energy gap due to the second semiconductor layer is greater than the energy gap of the material of the first semiconductor layer, the leakage current of PN junction that can reduce source electrode and be formed between drain electrode and Semiconductor substrate, thus the performance of transistor can be improved.And, charge carrier due to PMOS transistor is hole, the energy gap of source electrode and drain material is greater than the energy gap of the material of channel region, can't affect holoe carrier in source electrode, migration between drain electrode and channel region, thus can not have influence on the performance of PMOS transistor.
Further, in technical scheme of the present invention, the material of described first semiconductor layer is SiGe, and the material of the second semiconductor layer is silicon, and the energy gap of described silicon is greater than the energy gap of SiGe.Form the grid structure of transistor in the first semiconductor layer surface, the material due to the first semiconductor layer is SiGe, can improve the mobility in hole, thus improves the carrier mobility of the PMOS transistor formed, and improves the performance of PMOS transistor.
Further, in technical scheme of the present invention, before the described source electrode of formation and drain electrode, in described silicon layer, carry out light dope ion implantation and pocket ion implantation, form light doping section and pocket region.Described light doping section can reduce short-channel effect, and described pocket region can stop that the source electrode of follow-up formation spreads in channel region with the Doped ions in drain electrode, avoids Punchthrough effect, thus improves the performance of transistor.
Accompanying drawing explanation
Fig. 1 is the structural representation of the PMOS transistor of prior art of the present invention;
Fig. 2 to Figure 14 is the structural representation of the forming process of the PMOS transistor of embodiments of the invention.
Embodiment
As described in the background art, the performance need of the PMOS transistor formed in prior art improves further.
Research finds, the migration rate of carrier hole in SiGe of PMOS transistor is greater than the migration rate in silicon, adopt silicon germanium material can improve the hole mobility of PMOS transistor as the channel material of transistor, thus improve the saturation current of PMOS transistor.But, in described germanium-silicon layer, directly form the source electrode of described PMOS transistor and drain electrode and channel region, can make there is larger junction leakage between source electrode and the PN junction formed between drain electrode and substrate, affect the performance of PMOS transistor.Further research finds, makes the larger reason of described junction leakage be because the energy gap of silicon germanium material is less, and electronics easily occurs that transition causes.
Technical scheme of the present invention, adopt the first semiconductor layer as the channel region material of PMOS transistor, adopt the second semiconductor layer as the material of source electrode and drain electrode, the energy gap of the material of described second semiconductor layer is greater than the energy gap of the material of the first semiconductor layer, source electrode and the leakage current between drain electrode and Semiconductor substrate can be reduced, thus the performance of PMOS transistor can be improved.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Please refer to Fig. 2, Semiconductor substrate 100 is provided.
The material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, and described Semiconductor substrate 100 can be body silicon materials also can be that composite construction is as silicon-on-insulator.Those skilled in the art can select the type of described Semiconductor substrate 100 according to the semiconductor device that Semiconductor substrate 100 is formed, therefore the type of described Semiconductor substrate should not limit the scope of the invention.In the present embodiment, described Semiconductor substrate 100 is crystalline silicon.Follow-uply in described Semiconductor substrate 100, form PMOS transistor.
Please refer to Fig. 3, form the first semiconductor layer 200 on described Semiconductor substrate 100 surface.
In the present embodiment, the material of described first semiconductor layer 200 is SiGe, and in other embodiments of the invention, the material of described first semiconductor layer 200 can also be that other have the material of higher hole mobility.
Concrete, in the present embodiment, adopt epitaxy technique to form described first semiconductor layer 200.The temperature of described epitaxy technique is 600 DEG C ~ 1100 DEG C, and pressure is that 1 holder ~ 500 are held in the palm, and the silicon source gas of employing is SiH
4or SiH
2cl
2, germanium source gas is GeH
4, also comprise HCl gas and hydrogen, wherein the flow of silicon source gas, germanium source gas, HCl is 1sccm ~ 1000sccm, and the flow of hydrogen is 0.1slm ~ 50slm.
The thickness of described first semiconductor layer 200 adopting epitaxy technique to be formed is 2nm ~ 200nm, follow-up at described first semiconductor layer 200 surface formation grid structure, the channel region of the PMOS transistor formed is made to be positioned at described first semiconductor layer 200, material due to described first semiconductor layer 200 be SiGe or other there is the material of higher hole mobility, so the mobility in hole in PMOS transistor can be improved, thus improve the performance of PMOS transistor.
Please refer to Fig. 4, form mask layer 300 on described first semiconductor layer 200 surface.
In the present embodiment, described mask layer 300 comprises the silicon oxide layer 301 being positioned at described first semiconductor layer 200 surface and the silicon nitride layer 302 being positioned at described silicon oxide layer 301 surface.Described silicon oxide layer 301 can reduce between silicon nitride layer 302 with the first semiconductor layer 200 because lattice does not mate the stress caused.
In other embodiments of the invention, described mask layer 300 also can be silicon oxide layer or the silicon nitride layer of individual layer, can also be NON(silicon-nitride and silicon oxide-silicon nitride) three level stack structure.
Described mask layer 300 is follow-up for the formation of Patterned masking layer, defines the position of grid structure.
Please refer to Fig. 5, etch described mask layer 300(and please refer to Fig. 4), form Patterned masking layer 310, described Patterned masking layer 310 cover part silicon first semiconductor layer 200.
The method of the described Patterned masking layer of concrete formation 310 comprises: form photoresist layer on described mask layer 300 surface, carry out exposure imaging, define position and the size of the Patterned masking layer of follow-up formation to described photoresist layer; With described photoresist layer for mask, dry etch process is adopted to etch described mask layer 300, form Patterned masking layer 310, described Patterned masking layer 310 comprises: be positioned at the partial oxidation silicon layer 311 on described first semiconductor layer 200 surface and be positioned at the partial nitridation silicon layer 312 on described partial oxidation silicon layer 311 surface.Described Patterned masking layer 310 defines size and the position of the grid structure of the PMOS transistor of follow-up formation.
Please refer to Fig. 6, with described Patterned masking layer 310 for mask, etch described first semiconductor layer 200(and please refer to Fig. 5), form the first groove 201, described first groove 201 exposes the surface of part semiconductor substrate 100.
In the present embodiment, the described first semiconductor layer 200(of dry etch process etching is adopted to please refer to Fig. 5), form part first semiconductor layer 210 be positioned at below Patterned masking layer 310, and be positioned at the first groove 201 of described part first semiconductor layer 200 both sides.
Described first groove 201 exposes the surface of part semiconductor substrate 100, follow-up in described first groove 201 filling semiconductor material, form source electrode and drain electrode.
Please refer to Fig. 7, in described first groove, form the second semiconductor layer 202.
In the present embodiment, the material of described second semiconductor layer 202 is silicon, and the energy gap of silicon is greater than the energy gap of SiGe.In other embodiments of the invention, can, according to the material of suitable the second semiconductor layer of the Material selec-tion of the first semiconductor layer 200, the energy gap of the material of the second semiconductor layer be made to be greater than the energy gap of the material of the first semiconductor layer.
In the present embodiment, adopt epitaxy technique to form described second semiconductor layer 202, the temperature of described epitaxy technique is 600 DEG C ~ 1100 DEG C, and pressure is that 1 holder ~ 500 are held in the palm, and silicon source gas is SiH
4or SiH
2cl
2, also comprise HCl gas and hydrogen, wherein the flow of silicon source gas, HCl is 1sccm ~ 1000sccm, and the flow of hydrogen is 0.1slm ~ 50slm.
Described epitaxy technique can control the thickness of the second semiconductor layer 202 formed preferably, in the present embodiment, the thickness of described second semiconductor layer 202 and the consistency of thickness of part first semiconductor layer 210, the surface of described second semiconductor layer 202 flushes with the surface of part first semiconductor layer 210.
In other embodiments of the invention, the surface of described second semiconductor layer 202 also can a little less than the surface of described part first semiconductor layer 210.If, the surface of described second semiconductor layer 202 is higher than the surface of described part first semiconductor layer 210, described second semiconductor layer 202 can be connected between the surperficial grid structure formed of germanium-silicon layer 210 with follow-up, affects the performance of the transistor of follow-up formation.
Please refer to Fig. 8, form dielectric layer 400 on described second semiconductor layer 202 surface, the surface of described dielectric layer 400 flushes with the surface of Patterned masking layer 310.
The material of described dielectric layer 400 is silica or silicon oxynitride, and the material of described dielectric layer 400 is not identical with the material of Patterned masking layer 310, is convenient to remove described Patterned masking layer 310 in subsequent technique.In the present embodiment, the material of described dielectric layer 400 is silica.
Concrete, the method forming described dielectric layer 400 in the present embodiment comprises: adopt chemical vapor deposition method filled media material in described first groove 201, and described dielectric material is filled full described first groove 201 and covered the surface of described Patterned masking layer 310; With the top surface of described Patterned masking layer 310 for stop-layer, adopt chemical machinery masking process to carry out planarization to described dielectric material, form described dielectric layer 400, the surface of described dielectric layer 400 is flushed with the top surface of Patterned masking layer 310.
Please refer to Fig. 9, remove described Patterned masking layer 310(and please refer to Fig. 8), form the second groove 401.
Wet etching or dry etch process can be adopted to remove described Patterned masking layer 310, form the second groove 401.Described second groove 401 exposes the surface of part first semiconductor layer 210, and follow-up formation in described second groove 401 is positioned at the grid structure on described part first semiconductor layer 210 surface.
Please refer to Figure 10, please refer to Fig. 9 at described second groove 401() lower surface forms gate dielectric layer 501 and is positioned at described gate dielectric layer 501 surface and fills full described second groove 401, and the gate material layers 500 of blanket dielectric layer 400.
The material of described gate dielectric layer 501 is silica, and thickness is 1nm ~ 100nm.Described gate dielectric layer 501 adopts oxidation technology to be formed, described oxidation technology can be thermal oxidation technology or wet process oxidation technology, oxidation technology is adopted to form described gate dielectric layer 501, the damage that described first semiconductor layer surface causes due to etching technics can be repaired, in oxidation technology, the synthesis speed of described gate dielectric layer is lower, can control the thickness of the final described gate dielectric layer 501 formed preferably.
The material of described gate material layers 500 is polysilicon, adopts chemical deposition process to form described gate material layers 500.
In other embodiments of the invention, the material of described gate dielectric layer 501 can also be HfO
2, La
2o
3, HfSiON or other high K dielectric materials, described gate dielectric layer 501 can also adopt atom layer deposition process to be formed.The material of described gate material layers 500 can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
Please refer to Figure 11, with described dielectric layer 400 for stop-layer, Figure 10 be please refer to described gate material layers 500() carry out planarization formation grid 502.
The surface of described grid 502 flushes with the surface of dielectric layer 400.Described gate dielectric layer 501 and the grid structure of grid 502 as the PMOS transistor of follow-up formation.Described grid structure is positioned at the top of part first semiconductor layer 210.Be positioned at part first semiconductor layer 210 below grid structure as channel region, the mobility in hole can be improved, thus improve the performance of the PMOS transistor of follow-up formation.
Please refer to Figure 12, remove the dielectric layer of described gate dielectric layer 501 and grid structure both sides, expose the surface of the second semiconductor layer 202.
Wet etching or dry etch process can be adopted to remove described dielectric layer 400.In the present embodiment, adopt wet-etching technology to remove described dielectric layer 400, the solution of described wet etching is hydrofluoric acid solution.
Follow-up formation source electrode and drain electrode in described second semiconductor layer 202.
Please refer to Figure 13, in the second semiconductor layer 202 of described grid structure both sides, carry out light dope ion implantation and pocket ion implantation, form light doping section 601 and pocket region 602 respectively, described pocket region 602 surrounds described light doping section.
The ionic type that described light dope ion implantation is injected is P type ion, at least comprises a kind of ion in B, Ga or In.Described light dope ion implantation forms light doping section 601, can improve short-channel effect, improves the performance of transistor.
The ionic type that described pocket ion implantation is injected is N-type ion, at least comprises the one in P, As, Sb.Described pocket ion implantation forms pocket region 602, and the degree of depth of described pocket region 602 is greater than the degree of depth of light doping section 601.In the present embodiment, described pocket region 602 surrounds described light doping section 601.Described pocket ion implantation forms pocket region 602 can stop that the source electrode of follow-up formation spreads in channel region with the Doped ions in drain electrode, avoids Punchthrough effect.
In the present embodiment, first carry out described light dope ion implantation and form light doping section 601.The ion of described light dope ion implantation is B, and the dosage of described ion implantation is 1E14atom/cm
2~ 3E15atom/cm
2, the energy range of injection is 0.5KeV ~ 10KeV, and the range of tilt angles of injection is 0 degree ~ 15 degree.
After the described light doping section 601 of formation, with described grid structure for mask carries out pocket ion implantation to described silicon layer 202, the ion of described pocket ion implantation is P, and ion energy is 15KeV ~ 60KeV, and dosage is 3E13atom/cm
2~ 3E14atom/cm
2, ion implantation angle is 25 degree ~ 35 degree.The Doped ions of described pocket region 602 is electrically contrary with the Doped ions of light doping section, described light doping section 601 is narrowed in the depletion region below grid structure, alleviates short-channel effect.
Please refer to Figure 14, side wall 503 is formed in the sidewall surfaces of described gate dielectric layer 501 and grid 502, with described side wall 503 and grid 502 and mask, carry out heavy doping ion injection in the second semiconductor layer 202 of described grid 502 both sides, form source electrode 603 and drain electrode 604.
The ionic type that described heavy doping ion is injected is P type ion, at least comprises the one in B, Ga, In.Carry out heavy doping ion injection to described second semiconductor layer 202, form source electrode 603 and drain electrode 604, described source electrode 603 and drain electrode 604 are positioned at silicon layer 202.In other embodiments of the invention, part source electrode 603 and drain electrode 604 are also positioned at Semiconductor substrate 100.
In the present embodiment, after carrying out described heavy doping ion injection, also carry out annealing in process, activate the Doped ions in described light doping section 601, pocket region 602 and source electrode 603 and drain electrode 604.
In other embodiments of the invention, also can after carrying out described light dope ion implantation, pocket ion implantation, the injection of middle Doped ions, carry out annealing in process respectively, activate the Doped ions in described light doping section 601, pocket region 602 and source electrode 603 and drain electrode 604 respectively.
In the present embodiment, because the material of described source electrode 603 and drain electrode 604 is silicon, the energy gap of silicon is greater than the energy gap of SiGe, so more difficult generation electron transition, thus compare with drain material as source electrode with directly adopting silicon germanium material, the junction leakage of the PN junction that can reduce source electrode 603 and formed between drain electrode 604 and substrate, thus improve the saturation current of transistor.And, charge carrier due to PMOS transistor is hole, the energy gap of source electrode 603 and drain electrode 604 materials is greater than the energy gap of the material of channel region, can't affect holoe carrier in source electrode, migration between drain electrode and channel region, thus can not have influence on the performance of PMOS transistor.
And the channel region material of the PMOS transistor that described employing said method is formed is SiGe, can improve the mobility in hole in raceway groove, thus improves the performance of transistor.
Embodiments of the invention, additionally provide a kind of transistor adopting said method to be formed.
Please refer to Figure 14, described transistor comprises: Semiconductor substrate 100; First semiconductor layer 210 on cover part Semiconductor substrate 100 surface; Be positioned at second semiconductor layer 202 on Semiconductor substrate 100 surface of described first semiconductor layer 210 both sides; Be positioned at the grid structure on described first semiconductor layer 210 surface, described grid structure comprises the gate dielectric layer 501 being positioned at the first semiconductor layer 210 surface and the grid 502 being positioned at described gate dielectric layer 501 surface; Be positioned at source electrode and the drain electrode 603 of the second semiconductor layer 202 of described grid structure both sides.
In the present embodiment, the surface of described second semiconductor layer 202 flushes with the first semiconductor layer 210 surface.
Also be formed with light doping section 601 and pocket region 602 in second semiconductor layer 202 of described grid structure both sides, described pocket region 602 surrounds described light doping section 601, and described light doping section 601 is not identical with the Doped ions type in pocket region 602.
Described source electrode 603 is identical with the Doped ions type in light doping section 601 with the Doped ions type of drain electrode 604.
Described grid structure both sides sidewall surfaces is also formed with side wall 503.
In other embodiments of the invention, the described source electrode 603 of part and drain electrode 604 can also be positioned at Semiconductor substrate 100.
Channel region below the grid structure of above-mentioned PMOS transistor is the first semiconductor layer 210, in the present embodiment, the material of described first semiconductor layer 210 is SiGe, can improve the mobility in hole in PMOS transistor, thus improves the performance of the PMOS transistor formed.And the material of the second semiconductor layer 202 is silicon, the source electrode 603 of described PMOS transistor and the material of drain electrode 604 is made to be silicon, described silicon has larger energy gap, make the more difficult generation transition of electronics, thus the junction leakage of source electrode 603 and the PN junction between drain electrode 604 and Semiconductor substrate can be reduced, thus improve the performance of transistor.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for PMOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
The first semiconductor layer is formed at described semiconductor substrate surface;
Patterned masking layer is formed, described Patterned masking layer cover part first semiconductor layer in described first semiconductor layer surface;
With described Patterned masking layer for mask, etch described first semiconductor layer, form the first groove, described first groove exposes the surface of part semiconductor substrate;
In described first groove, form the second semiconductor layer, the energy gap of the material of described second semiconductor layer is greater than the energy gap of the material of the first semiconductor layer;
Form dielectric layer in described second semiconductor layer surface, the surface of described dielectric layer flushes with the surface of Patterned masking layer;
Remove described Patterned masking layer, form the second groove;
Grid structure is formed in described second groove;
Remove the dielectric layer of described grid structure both sides, in the second semiconductor layer of described grid structure both sides, form source electrode and drain electrode.
2. the formation method of PMOS transistor according to claim 1, is characterized in that, the material of described first semiconductor layer is SiGe.
3. the formation method of PMOS transistor according to claim 2, is characterized in that, the thickness of described first semiconductor layer is 2nm ~ 200nm.
4. the formation method of PMOS transistor according to claim 1, is characterized in that, described Patterned masking layer comprises the silicon oxide layer being positioned at described first semiconductor layer surface and the silicon nitride layer being positioned at described silicon oxide layer surface.
5. the formation method of PMOS transistor according to claim 2, is characterized in that, the material of described second semiconductor layer is silicon.
6. the formation method of PMOS transistor according to claim 5, is characterized in that, the technique forming the second semiconductor layer in described first groove is selectivity depositing operation.
7. the formation method of PMOS transistor according to claim 1, is characterized in that, the surface of described second semiconductor layer flushes with the first semiconductor layer surface.
8. the formation method of PMOS transistor according to claim 1, it is characterized in that, the method forming described dielectric layer comprises: filled media material in described first groove, and described dielectric material fills full first groove and the surface of cover graphics mask layer; With the surface of described Patterned masking layer for stop-layer, adopt chemical machinery masking process to carry out planarization to described dielectric material, form described dielectric layer.
9. the formation method of PMOS transistor according to claim 8, is characterized in that, the material of described dielectric layer is silica.
10. the formation method of PMOS transistor according to claim 5, it is characterized in that, after removing the dielectric layer of described grid structure both sides, before forming described source electrode and drain electrode, light dope ion implantation and pocket ion implantation is carried out in the second semiconductor layer of described grid structure both sides, form light doping section and pocket region respectively, described pocket region surrounds described light doping section.
The formation method of 11. PMOS transistor according to claim 10, is characterized in that, the ionic type of described light dope ion implantation is not identical with the ionic type of pocket ion implantation.
The formation method of 12. PMOS transistor according to claim 11, it is characterized in that, the method forming described source electrode and drain electrode comprises: form side wall in described grid structure both sides sidewall surfaces, with described grid structure and side wall for mask, carry out heavy doping ion injection in the second semiconductor layer of described grid structure both sides.
The formation method of 13. PMOS transistor according to claim 12, is characterized in that, the ionic type that described heavy doping ion is injected is identical with the ionic type of light dope ion implantation.
The formation method of 14. PMOS transistor according to claim 13, is characterized in that, part source electrode and drain electrode are positioned at Semiconductor substrate.
15. 1 kinds of PMOS transistor, is characterized in that, comprising:
Semiconductor substrate;
First semiconductor layer of cover part semiconductor substrate surface;
Be positioned at the second semiconductor layer of the semiconductor substrate surface of described first semiconductor layer both sides, the energy gap of the material of described second semiconductor layer is greater than the energy gap of the material of the first semiconductor layer;
Be positioned at the grid structure of described first semiconductor layer surface;
Be positioned at source electrode and the drain electrode of the second semiconductor layer of described grid structure both sides.
16. PMOS transistor according to claim 15, is characterized in that, the material of described first semiconductor layer is germanium silicon, and the material of the second semiconductor layer is silicon.
17. PMOS transistor according to claim 16, is characterized in that, the surface of described second semiconductor layer flushes with the first semiconductor layer surface.
18. PMOS transistor according to claim 17, it is characterized in that, also comprise light doping section and the pocket region of the second semiconductor layer being positioned at grid structure both sides, described pocket region surrounds described light doping section, and the Doped ions type in described light doping section is not identical with the Doped ions type in pocket region.
19. PMOS transistor according to claim 18, is characterized in that, described source electrode is identical with the Doped ions type in light doping section with the Doped ions type in drain electrode.
20. PMOS transistor according to claim 19, is characterized in that, part source electrode and drain electrode are positioned at Semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310425758.5A CN104465377B (en) | 2013-09-17 | 2013-09-17 | Pmos transistor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310425758.5A CN104465377B (en) | 2013-09-17 | 2013-09-17 | Pmos transistor and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104465377A true CN104465377A (en) | 2015-03-25 |
| CN104465377B CN104465377B (en) | 2018-10-16 |
Family
ID=52911242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310425758.5A Active CN104465377B (en) | 2013-09-17 | 2013-09-17 | Pmos transistor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104465377B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630546A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN112928153A (en) * | 2019-12-05 | 2021-06-08 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207519B1 (en) * | 1997-10-08 | 2001-03-27 | Samsung Electronics Co., Ltd | Method of making semiconductor device having double spacer |
| CN1717798A (en) * | 2002-11-27 | 2006-01-04 | 英特尔公司 | Novel field effect transistor and method of fabrication |
| US20070001222A1 (en) * | 2005-06-30 | 2007-01-04 | Freescale Semiconductor, Inc. | Single transistor memory cell with reduced recombination rates |
| CN101355102A (en) * | 2007-07-25 | 2009-01-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
| CN101604693A (en) * | 2008-06-13 | 2009-12-16 | 旺宏电子股份有限公司 | Memory component |
| CN102368501A (en) * | 2011-10-20 | 2012-03-07 | 中山大学 | GaN based enhanced MOSHFET device and preparation method thereof |
| CN103155123A (en) * | 2010-10-15 | 2013-06-12 | 国际商业机器公司 | Method and structure for pFET junction profile with SiGe channel |
-
2013
- 2013-09-17 CN CN201310425758.5A patent/CN104465377B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6207519B1 (en) * | 1997-10-08 | 2001-03-27 | Samsung Electronics Co., Ltd | Method of making semiconductor device having double spacer |
| CN1717798A (en) * | 2002-11-27 | 2006-01-04 | 英特尔公司 | Novel field effect transistor and method of fabrication |
| US20070001222A1 (en) * | 2005-06-30 | 2007-01-04 | Freescale Semiconductor, Inc. | Single transistor memory cell with reduced recombination rates |
| CN101355102A (en) * | 2007-07-25 | 2009-01-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for forming the same |
| CN101604693A (en) * | 2008-06-13 | 2009-12-16 | 旺宏电子股份有限公司 | Memory component |
| CN103155123A (en) * | 2010-10-15 | 2013-06-12 | 国际商业机器公司 | Method and structure for pFET junction profile with SiGe channel |
| CN102368501A (en) * | 2011-10-20 | 2012-03-07 | 中山大学 | GaN based enhanced MOSHFET device and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108630546A (en) * | 2017-03-17 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN112928153A (en) * | 2019-12-05 | 2021-06-08 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104465377B (en) | 2018-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10217672B2 (en) | Vertical transistor devices with different effective gate lengths | |
| CN102117750B (en) | Metal-oxide-semiconductor field effect transistor (MOSFET) structure and manufacturing method thereof | |
| US8999794B2 (en) | Self-aligned source and drain structures and method of manufacturing same | |
| US10170469B2 (en) | Vertical field-effect-transistors having multiple threshold voltages | |
| CN103137488B (en) | Semiconductor device and manufacture method thereof | |
| CN104253046B (en) | Fin formula field effect transistor and forming method thereof | |
| US20100078733A1 (en) | Transistor performance improving method with metal gate | |
| US20130187207A1 (en) | Replacement source/drain finfet fabrication | |
| KR20160016508A (en) | Nonplanar device and strain-generating channel dielectric | |
| CN103811351A (en) | Method for forming epitaxial feature | |
| US9640660B2 (en) | Asymmetrical FinFET structure and method of manufacturing same | |
| US9048267B2 (en) | Semiconductor device | |
| US20110108894A1 (en) | Method of forming strained structures in semiconductor devices | |
| CN110571192A (en) | Semiconductor structure and forming method thereof | |
| CN103681346B (en) | Transistors, semiconductor devices, and methods of manufacture thereof | |
| CN102237277B (en) | Semiconductor device and method for forming same | |
| CN103377946B (en) | A kind of semiconductor structure and manufacture method thereof | |
| CN104752228A (en) | Semiconductor device structure and method of manufacturing the same | |
| US20130032877A1 (en) | N-channel transistor comprising a high-k metal gate electrode structure and a reduced series resistance by epitaxially formed semiconductor material in the drain and source areas | |
| CN109216278B (en) | Semiconductor structure and forming method thereof | |
| JP2016157798A (en) | Semiconductor device | |
| WO2012119336A1 (en) | Semiconductor structure and manufacturing method thereof | |
| US8729639B2 (en) | Semiconductor device and method for producing the same | |
| US20220199460A1 (en) | Method for forming semiconductor structure | |
| CN104465377A (en) | Pmos transistor and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |