CN102420192A - Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory) - Google Patents
Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory) Download PDFInfo
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Abstract
The invention discloses a manufacturing method of a twin-transistor and zero-capacitance dynamic RAM (Random Access Memory), aiming at providing the manufacturing method of the twin-transistor and zero-capacitance dynamic RAM which is manufactured by adopting a silicon of insulator-based gate-last process and has a design for manufacturability. In the process, the characteristics different from the characteristics of greater Overlap between a T1 source/drain electrode and a gate and greater distance Underlap between a T2 source/drain electrode and the gate in a conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process are effectively achieved by self aligning; the manufacturing method is suitable for manufacturing of an integrated circuit in the gate-last process of a high-dielectric-constant oxidation layer metal gate of below 45nm; and by adjusting work functions of the gates of the T1 and the T2, which are close to the source electrode and the drain electrode, or doping types of channel regions at the lower parts of the gates, which are close to the source electrode and the drain electrode through ion implantation, the channel regions in the channel regions of the T1, which are close to the source electrode and the drain electrode, are inverted to be the same types with the source region and the drain region under the condition of no increase of the pressure of the gates and diffusion regions below the gates of the source electrode and the drain electrode of the T2 are inverted into the opposite types of the source region and the drain region under the condition of no increase of the pressure of the gates.
Description
Technical field
The present invention relates generally to technical field of manufacturing semiconductors, or rather, the present invention relates to a kind of preparation method based on the pair transistor zero capacitance dynamic ram of the back grid technology of silicon-on-insulator with manufacturability design.
Background technology
Along with semiconductor integrated circuit gets into the more high-order technology epoch; Tradition one transistor one capacitor (One Transistor One Capacity; Being abbreviated as 1T1C) DRAM of structure processes by electric capacity and transistor; Electric capacity is used for storing data and transistor leads to the switch block of system as data, and this has aggravated the complexity of manufacturing process undoubtedly, and especially to prepare difficulty be increasing to the capacitor of high density of integration, low electric leakage.Therefore; Present pair transistor (Two Transistors to substituting 1T1C structure DRAM; Be abbreviated as 2T) even the zero capacitance dynamic ram of single-transistor structure or do not have electric capacity dynamic ram (Zero-Capacitor RAM or Capacitorless RAM; Being abbreviated as Z-RAM) research is more and more popular, and Z-RAM can double the storage density of DRAM, and the buffer memory capacity of processor is improved five times; And need not to require to use special material or more advanced manufacturing process, have a good application prospect.U.S. Pat 2010/0329043 A1 discloses a kind of buoyancy aid/grid unit (FBGC:Floating Body/Gate Cell; Be abbreviated as FBGC) pair transistor dynamic ram structure; Figure one is its cellular construction (is example with NMOS); The dual-MOS structure that it is based on silicon-on-insulator (Silicon On Insulator is abbreviated as SOI) (can be that part depletion < Partial Depletion, PD>perhaps all exhausts < Full Depletion; FD >); Among the figure, the source of T1 is leaked and is connected BL1 (Bit Line 1, bit line 1) together; When it utilizes the T1 grid that leak in grid and source when OFF state to induce drain leakage (Gate-Induced Drain Leakage is abbreviated as GIDL) effect its buoyancy aid (Floating Body) is filled positive charge and T1 ON state buoyancy aid discharged and realizes " 0 ", " 1 " and storage and conversion; Figure two is the change in voltage characteristic of each node under the various states of this 2T DRAM that utilize the UFDG/Spice3 model emulation, and BL2 voltage or electric current are for reading the result.In order fast T1 to be discharged and recharged, realize promptly writing the high-speed of process, requiring the T1 source to leak with grid has bigger overlapping (Overlap), to increase the GIDL effect as far as possible.In order to make T1 buoyancy aid electric charge fast driving T2; Require to reduce the T2 parasitic capacitance as far as possible; Require source leakage and the grid of T2 bigger distance (Underlap) to be arranged to reduce the parasitic capacitance between the leakage of T2 grid and source for this reason; This FBGC 2T DRAM structure has certain uniqueness; But it does not solve manufacturability (DFM, Design for Manufacturability) problem, promptly how on technology, to realize effectively that through autoregistration the T1 source leakage that is different from conventional cmos technology has bigger overlapping and the leakage of T2 source with grid bigger range performance to be arranged with grid.
Summary of the invention
Problem to above-mentioned existence; The preparation method who the purpose of this invention is to provide the pair transistor zero capacitance dynamic ram that a kind of back grid technology based on silicon-on-insulator with manufacturability design makes; On technology, realize effectively that through autoregistration the T1 source leakage that is different from conventional cmos technology has bigger overlapping (Overlap) and the leakage of T2 source with grid bigger distance (Underlap) characteristic to be arranged with grid; Be applicable in the integrated circuit preparation of grid technology behind the high dielectric constant oxide layer metal gates below the 45nm, realize through following technical proposals:
A kind of preparation method of pair transistor zero capacitance dynamic ram, pair transistor wherein is two cascade MOS transistor T1 and the T2 that is formed on the common substrate, wherein, is equipped with operation before comprising, is equipped with operation before said to comprise:
T1 and T2 separately the channel surface between source-drain electrode be formed with thin oxide layer respectively;
Above thin oxide layer, be formed with T1 and T2 gate trench separately respectively, and in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it respectively through wet the eat-backing of appended sample grid.
Through T1, the T2 opening of gate trench separately; Inject the metal oxide dielectric materials layer change T1, T2 respectively and comprised work function near the two ends of source electrode and drain electrode through ion; So that transoid is the doping type identical with source-drain area under the grid voltage situation not adding near the zone of source electrode and drain electrode in the T1 channel region, transoid is the doping type opposite with source-drain area under the grid voltage situation not adding near the zone of source electrode and drain electrode in the T2 channel region.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram wherein, when two cascade MOS transistor T1 and T2 are the NMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode be formed with thin oxide layer respectively;
Above thin oxide layer, be formed with T1 and T2 gate trench separately respectively, and in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it respectively through wet the eat-backing of appended sample grid;
Carry out photoetching; The T1 regional window is opened; The T2 regional window is closed; Carry out angle tilt, rotate and to carry out two-way ion behind 180 degree and inject so that grid reduce work function near source and leak, cause under the grid that transoid is the N type under the grid voltage situation not adding near the channel region of source and leakage, the injection ion is the ion of little work function;
Carry out photoetching; The T2 regional window is opened; The T1 regional window is closed; Carry out angle tilt, rotate and to carry out that two-way ion injects so that grid increase work function near source and leak behind 180 degree, transoid is the P type under the grid voltage situation not adding to cause under the grid of source and leakage diffusion zone, and the injection ion is mainly the ion of big work function.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram wherein, when two cascade MOS transistor T1 and T2 are the PMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode be formed with thin oxide layer respectively;
Above thin oxide layer, be formed with T1 and T2 gate trench separately respectively, and in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it respectively through wet the eat-backing of appended sample grid;
Carry out photoetching; The T1 regional window is opened; The T2 regional window is closed; Carry out angle tilt, rotate and to carry out that two-way ion injects so that grid increase work function near source and leak behind 180 degree, cause under the grid that transoid is the P type under the grid voltage situation not adding near the channel region of source and leakage, the injection ion is mainly the ion of big work function;
Carry out photoetching; The T2 regional window is opened; The T1 regional window is closed; Carry out angle tilt, rotate and to carry out two-way ion behind 180 degree and inject so that grid reduce work function near source and leak, cause under the grid that transoid is the N type under the grid voltage situation not adding near the channel region of source and leakage, the injection ion is mainly the ion of little work function.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram; Wherein, Above thin oxide layer, form T1 and T2 gate trench separately respectively earlier, in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it more respectively through wet the eat-backing of appended sample grid.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, high dielectric layer and metal oxide dielectric materials layer form earlier when the sample grid prepare, and wet at the appended sample grid and do not remove when eat-backing.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, the operation of said twice regulatory work function can be exchanged.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram; Wherein, the ion of said little work function comprises a kind of ion or the combination of different kinds of ions: Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, the Th of following column element for base.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram; Wherein, the ion of said big work function comprises a kind of ion or the combination of different kinds of ions: B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, the Po of following column element for base.
A kind of preparation method of pair transistor zero capacitance dynamic ram, pair transistor wherein is two cascade MOS transistor T1 and the T2 that is formed on the common substrate, wherein, is equipped with operation before comprising, wherein: be equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid;
Inject through ion and to make that transoid is the doping type identical with source-drain area under the grid voltage situation not adding near the channel region of source electrode and drain electrode for the channel region of T1, and make in the channel region of T2 that transoid is the doping type opposite with source-drain area under the grid voltage situation not adding near the channel region of source electrode and drain electrode.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram wherein, when two cascade MOS transistor T1 and T2 are the NMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid;
Carry out photoetching, the T1 regional window is opened, the T2 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection P in back or As ions, cause under the grid that transoid is the N type under the grid voltage situation not adding near the channel region of source and leakage;
Carry out photoetching, the T2 regional window is opened, the T1 regional window is closed, carry out angle tilt, rotate the 180 degree two-way injection B in back or BF2 or BF or In ions, transoid is the P type under the grid voltage situation not adding to cause under the grid of source and leakage diffusion zone.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram wherein, when two cascade MOS transistor T1 and T2 are the PMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid;
Carry out photoetching, the T1 regional window is opened, the T2 regional window is closed, carry out angle tilt, rotate the 180 degree two-way injection B in back or BF2 or BF or In ions, cause under the grid that transoid is the P type under the grid voltage situation not adding near the channel region of source and leakage;
Carry out photoetching, the T2 regional window is opened, the T1 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection P in back or As ions, transoid is the N type under the grid voltage situation not adding to cause under the grid of source and leakage diffusion zone.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, said twice ion is injected the operation of compensation and can be exchanged.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram wherein, adopts annealing of rapid thermal treatment or transient peak or flash annealing to inject ion to activate.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after the accompanying drawing, of the present invention these are incited somebody to action obvious with otherwise advantage undoubtedly.
Description of drawings
With reference to appended accompanying drawing, describing embodiments of the invention more fully, yet appended accompanying drawing only is used for explanation and sets forth, and does not constitute limitation of the scope of the invention.
Fig. 1 is the NMOS cellular construction of buoyancy aid of the prior art/grid unit pair transistor dynamic ram structure;
Fig. 2 is the change in voltage characteristic that buoyancy aid of the prior art/grid unit pair transistor dynamic ram structure prepares each node under the various states of this pair transistor dynamic ram that utilize the UFDG/Spice3 model emulation in the process;
Fig. 3 A ~ Fig. 3 D is respectively that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of NMOS structure to regulate the flowage structure sketch map of the embodiment of pattern;
Fig. 4 is the status architecture sketch map after flow process that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of NMOS structure to regulate the embodiment of pattern is accomplished;
Fig. 5 A ~ Fig. 5 D is respectively that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of PMOS structure to regulate the flowage structure sketch map of the embodiment of pattern;
Fig. 6 is the status architecture sketch map after flow process that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of PMOS structure to regulate the embodiment of pattern is accomplished;
Fig. 7 A ~ Fig. 7 D is respectively that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the ion of NMOS structure to inject the flowage structure sketch map of the embodiment of compensation model;
Fig. 8 is the status architecture sketch map after flow process that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the ion of NMOS structure to inject the embodiment of compensation model is accomplished;
Fig. 9 A ~ Fig. 9 D is respectively that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the ion of PMOS structure to inject the flowage structure sketch map of the embodiment of compensation model;
Figure 10 is the status architecture sketch map after flow process that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the ion of PMOS structure to inject the embodiment of compensation model is accomplished.
Embodiment
The present invention for a kind of silicon-on-insulator with manufacturability design after the preparation method of grid pair transistor zero capacitance dynamic ram; Pair transistor wherein is two cascade MOS transistor T1 and the T2 that is formed on the common substrate; Be equipped with operation and subsequent handling before specifically comprising; Wherein, the preceding operation that is equipped with comprises:
T1 and T2 separately the channel surface between source-drain electrode be formed with thin oxide layer respectively;
Above thin oxide layer, form T1 and T2 gate trench separately respectively, and in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it respectively through wet the eat-backing of appended sample grid.Alternatively, high dielectric layer and metal oxide dielectric materials layer also can form earlier when the sample grid prepare, and wet at the appended sample grid and do not remove when eat-backing;
Through T1, the T2 opening of gate trench separately; Inject the metal oxide dielectric materials layer change T1, T2 respectively and comprised work function near the two ends of source electrode and drain electrode through ion; So that change (being transoid) under the grid voltage situation and be the doping type identical with source-drain area not adding near the zone of source electrode and drain electrode in the T1 channel region, to change (being transoid) under the grid voltage situation be the doping type opposite with source-drain area not adding near the zone of source electrode and drain electrode in the T2 channel region;
Subsequent handling comprises:
At two cascade MOS transistor T1 and difference plated metal barrier layer, T2 surface and metal level, form grid through cmp afterwards;
Deposit an insulating barrier;
Above grid, source electrode and drain electrode, form through hole in the insulating barrier and contact, and draw lead through the back segment interconnection process.
Embodiment one, when two cascade MOS transistor T1 and T2 are the NMOS structure all, specifically comprise the steps:
Shown in Fig. 3 A; Form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid; The gate dielectric layer of T1 and T2 comprises the metal oxide dielectric materials layer 3 (Cap layer) of high dielectric layer 2 (HK layer) and its top; The high dielectric layer 2 belows one deck thin oxide layer 1 of can growing alternatively, the gate dielectric layer of T1 and T2 can form in the wet back of eat-backing of sample grid, also can when the sample grid prepare, form and wets at the sample grid and not remove when eat-backing;
Shown in Fig. 3 B; Carry out photoetching; The T1 regional window is opened, the T2 regional window is closed, carry out carrying out two-way ion injection so that grid reduce work function near source and leak behind angle tilt, rotation 180 degree; Cause under the grid near the channel region of source and leakage and change (being transoid) under the grid voltage situation and be the N type not adding; Injecting ion is the ion of little work function, and the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding, and variation has taken place, and thin oxide layer 1 is not affected with high dielectric layer 2;
Shown in Fig. 3 C; Carry out photoetching; The T2 regional window is opened, the T1 regional window is closed, carry out carrying out two-way ion injection so that grid increase work function near source and leak behind angle tilt, rotation 180 degree; Cause under the grid of source and leakage diffusion zone to change (being transoid) under the grid voltage situation and be the P type not adding; Inject the ion that ion is mainly big work function, the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding, and variation has taken place, and thin oxide layer 1 is not affected with high dielectric layer 2.
The operation of above-mentioned twice regulatory work function can be exchanged, and the sketch map after the completion work function is regulated referring to the double-head arrow indication of below, realized that the source leakage of T1 on one side has bigger overlapping with grid, and the leakage of the source of another side T2 does not have overlapping with grid shown in Fig. 3 D.
Wherein, The ion of above-mentioned little work function is to be the ion of base with elements such as Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, Th, and the ion of above-mentioned big work function is to be the ion of base with elements such as B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po.
After accomplishing above-mentioned steps,, form grid 0 through cmp afterwards then at two cascade nmos pass transistor T1 and T2 surface deposition metal barrier and metal level; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, form through hole in the insulating barrier and contact 5; And draw lead through the back segment interconnection process; Connect according to the circuit diagram among Fig. 1 respectively, guarantee that the tagma of T1 is to link to each other with the grid of T2, the status architecture sketch map after the completion is as shown in Figure 4.
Embodiment two,When two cascade MOS transistor T1 and T2 are the PMOS structure all, specifically comprise the steps:
Shown in Fig. 5 A; Form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid; The gate dielectric layer of T1 and T2 comprises the metal oxide dielectric materials layer 3 (Cap layer) of high dielectric layer 2 (HK layer) and its top; The high dielectric layer 2 belows one deck thin oxide layer 1 of can growing alternatively, the gate dielectric layer of T1 and T2 can form in the wet back of eat-backing of sample grid, also can when the sample grid prepare, form and wets at the sample grid and not remove when eat-backing;
Shown in Fig. 5 B; Carry out photoetching; The T1 regional window is opened, the T2 regional window is closed, carry out carrying out two-way ion injection so that grid increase work function near source and leak behind angle tilt, rotation 180 degree; Cause under the grid near the channel region of source and leakage and change (being transoid) under the grid voltage situation and be the P type not adding; Inject the ion that ion is mainly big work function, the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding, and variation has taken place, and thin oxide layer 1 is not affected with high dielectric layer 2;
Shown in Fig. 5 C; Carry out photoetching; The T2 regional window is opened, the T1 regional window is closed, carry out carrying out two-way ion injection so that grid reduce work function near source and leak behind angle tilt, rotation 180 degree; Cause under the grid near the channel region of source and leakage and change (being transoid) under the grid voltage situation and be the N type not adding; Inject the ion that ion is mainly little work function, the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding, and variation has taken place, and thin oxide layer 1 is not affected with high dielectric layer 2.
The operation of above-mentioned twice regulatory work function can be exchanged, and the sketch map after the completion work function is regulated referring to the double-head arrow indication of below, realized that the source leakage of T1 on one side has bigger overlapping with grid, and the leakage of the source of another side T2 does not have overlapping with grid shown in Fig. 5 D.
Wherein, The ion of above-mentioned little work function is to be the ion of base with elements such as Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, Th, and the ion of above-mentioned big work function is to be the ion of base with elements such as B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po.
After accomplishing above-mentioned steps,, form grid 0 through cmp afterwards then at two cascade PMOS transistor Ts 1 and T2 surface deposition metal barrier and metal level; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, form through hole in the insulating barrier and contact 5; And draw lead through the back segment interconnection process; Connect according to the circuit diagram among Fig. 1 respectively, guarantee that the tagma of T1 is to link to each other with the grid of T2, the status architecture sketch map after the completion is as shown in Figure 6.
The present invention for a kind of silicon-on-insulator with manufacturability design after the preparation method of grid pair transistor zero capacitance dynamic ram; Pair transistor wherein is two cascade MOS transistor T1 and the T2 that is formed on the common substrate; Be equipped with operation and subsequent handling before specifically comprising; Wherein, the preceding operation that is equipped with comprises: T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid; Through T1, the T2 opening of gate trench separately; Inject through ion and to make the channel region of T1 change (being transoid) under the grid voltage situation and be the doping type identical not adding, and make in the channel region of T2 that change (being transoid) is the doping type opposite with source-drain area under the grid voltage situation not adding near the channel region of source electrode and drain electrode with source-drain area near the channel region of source electrode and drain electrode;
Form the metal oxide dielectric materials layer of high dielectric layer and its top;
Subsequent handling comprises:
At two cascade MOS transistor T1 and T2 surface deposition metal barrier and metal level, form grid through cmp afterwards;
Deposit an insulating barrier;
Above grid, source electrode and drain electrode, form through hole in the insulating barrier and contact, and draw lead through the back segment interconnection process.
Embodiment one,When two cascade MOS transistor T1 and T2 are the NMOS structure all; Specifically comprise the steps: shown in Fig. 7 A; Form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid, T1 and T2 separately the channel surface between source-drain electrode only form a thin oxide layer 1;
Shown in Fig. 7 B; Carry out photoetching, the T1 regional window is opened, the T2 regional window is closed; Carry out angle tilt, rotate 180 degree two-way injection P in back or As ions, cause under the grid that to change (being transoid) under the grid voltage situation be the N type not adding near the channel region of source and leakage;
Shown in Fig. 7 C, carry out photoetching, the T2 regional window is opened, the T1 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection B in back or BF
2Perhaps BF or In ion, transoid is the P type under the grid voltage situation not adding to cause under the grid of source and leakage diffusion zone.
The operation of above-mentioned twice ion injection compensation can be exchanged, and adopts rapid thermal treatment (RTP) or transient peak annealing (Spike Anneal) or flash annealing (Flash Anneal) to activate the injection ion.Sketch map after the completion ion injection compensated regulation is shown in Fig. 7 D.
After accomplishing above-mentioned steps, then in T1 and T2 gate trench separately, be formed with the metal oxide dielectric materials layer 3 (Cap layer) of high dielectric layer 2 (HK layer) and its top; At two cascade nmos pass transistor T1 and T2 surface deposition metal level, form grid 0 through cmp afterwards; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, form through hole in the insulating barrier and contact 5; And draw lead through the back segment interconnection process; Connect according to the circuit diagram among Fig. 1 respectively, guarantee that the tagma of T1 is to link to each other with the grid of T2, the status architecture sketch map after the completion is as shown in Figure 8.
Embodiment two,When two cascade MOS transistor T1 and T2 are the PMOS structure all, specifically comprise the steps:
Shown in Fig. 9 A, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid, T1 and T2 separately the channel surface between source-drain electrode only form a thin oxide layer 1;
Shown in Fig. 9 B, carry out photoetching, the T1 regional window is opened, the T2 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection B in back or BF
2Perhaps BF or In ion cause under the grid near the channel region of source and leakage to change (being transoid) under the grid voltage situation and be the P type not adding;
Shown in Fig. 9 C; Carry out photoetching, the T2 regional window is opened, the T1 regional window is closed; Carry out angle tilt, rotate 180 degree two-way injection P in back or As ions, to change (being transoid) under the grid voltage situation be the N type not adding to cause under the grid of source and leakage diffusion zone.
The operation of above-mentioned twice ion injection compensation can be exchanged, and adopts rapid thermal treatment (RTP) or transient peak annealing (Spike Anneal) or flash annealing (Flash Anneal) to activate the injection ion.Sketch map after the completion ion injection compensated regulation is shown in Fig. 9 D.
After accomplishing above-mentioned steps, then in T1 and each comfortable gate trench of T2, be formed with the metal oxide dielectric materials layer 3 (Cap layer) of high dielectric layer 2 (HK layer) and its top; At two cascade PMOS transistor Ts 1 and T2 surface deposition metal level, form grid 0 through cmp afterwards; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, form through hole in the insulating barrier and contact 5; And draw lead through the back segment interconnection process; Connect according to the circuit diagram among Fig. 1 respectively, guarantee that the tagma of T1 is to link to each other with the grid of T2, the status architecture sketch map after the completion is shown in figure 10.
Through explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, for example, this case is to set forth with PMOS device and nmos device, based on the present invention's spirit, chip also can be done the conversion of other types.Therefore, although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read above-mentioned explanation after, various variations and revise undoubtedly will be obvious.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as, and any and all scope of equal value and contents all should be thought still to belong in the intent of the present invention and the scope in claims scope.
Claims (13)
1. the preparation method of a pair transistor zero capacitance dynamic ram, pair transistor wherein is two cascade MOS transistor T1 and the T2 that is formed on the common substrate, it is characterized in that, is equipped with operation before comprising, is equipped with operation before said to comprise:
T1 and T2 separately the channel surface between source-drain electrode be formed with thin oxide layer respectively;
Above thin oxide layer, be formed with T1 and T2 gate trench separately respectively, and in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it respectively through wet the eat-backing of appended sample grid;
Through T1, the T2 opening of gate trench separately; Inject the metal oxide electricity dielectric material layer change T1, T2 respectively and comprised work function near the two ends of source electrode and drain electrode through ion; So that transoid is the doping type identical with source-drain area under the grid voltage situation not adding near the zone of source electrode and drain electrode in the T1 channel region, transoid is the doping type opposite with source-drain area under the grid voltage situation not adding near the zone of source electrode and drain electrode in the T2 channel region.
2. the preparation method of pair transistor zero capacitance dynamic ram according to claim 1 is characterized in that, when two cascade MOS transistor T1 and T2 are the NMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode be formed with thin oxide layer respectively;
Above thin oxide layer, be formed with T1 and T2 gate trench separately respectively, and in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it respectively through wet the eat-backing of appended sample grid;
Carry out photoetching; The T1 regional window is opened; The T2 regional window is closed; Carry out angle tilt, rotate and to carry out two-way ion behind 180 degree and inject so that grid reduce work function near source and leak, cause under the grid that transoid is the N type under the grid voltage situation not adding near the channel region of source and leakage, the injection ion is the ion of little work function;
Carry out photoetching; The T2 regional window is opened; The T1 regional window is closed; Carry out angle tilt, rotate and to carry out that two-way ion injects so that grid increase work function near source and leak behind 180 degree, transoid is the P type under the grid voltage situation not adding to cause under the grid of source and leakage diffusion zone, and the injection ion is mainly the ion of big work function.
3. the preparation method of pair transistor zero capacitance dynamic ram according to claim 1 is characterized in that, when two cascade MOS transistor T1 and T2 are the PMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode be formed with thin oxide layer respectively;
Above thin oxide layer, be formed with T1 and T2 gate trench separately respectively, and in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it respectively through wet the eat-backing of appended sample grid;
Carry out photoetching; The T1 regional window is opened; The T2 regional window is closed; Carry out angle tilt, rotate and to carry out that two-way ion injects so that grid increase work function near source and leak behind 180 degree, cause under the grid that transoid is the P type under the grid voltage situation not adding near the channel region of source and leakage, the injection ion is mainly the ion of big work function;
Carry out photoetching; The T2 regional window is opened; The T1 regional window is closed; Carry out angle tilt, rotate and to carry out two-way ion behind 180 degree and inject so that grid reduce work function near source and leak, cause under the grid that transoid is the N type under the grid voltage situation not adding near the channel region of source and leakage, the injection ion is mainly the ion of little work function.
4. according to the preparation method of claim 1 or 2 or 3 described pair transistor zero capacitance dynamic rams; It is characterized in that; Above thin oxide layer, form T1 and T2 gate trench separately respectively earlier, in T1 and T2 gate trench separately, be formed with high dielectric layer and the metal oxide dielectric materials layer above it more respectively through wet the eat-backing of appended sample grid.
5. according to the preparation method of claim 1 or 2 or 3 described pair transistor zero capacitance dynamic rams, it is characterized in that high dielectric layer and metal oxide dielectric materials layer form earlier when the sample grid prepare, wet at the appended sample grid and do not remove when eat-backing.
6. according to the preparation method of claim 2 or 3 described pair transistor zero capacitance dynamic rams, it is characterized in that the operation of said twice regulatory work function can be exchanged.
7. according to the preparation method of claim 2 or 3 described pair transistor zero capacitance dynamic rams; It is characterized in that the ion of said little work function comprises a kind of ion or the combination of different kinds of ions: Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, the Th of following column element for base.
8. according to the preparation method of claim 2 or 3 described pair transistor zero capacitance dynamic rams; It is characterized in that the ion of said big work function comprises a kind of ion or the combination of different kinds of ions: B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, the Po of following column element for base.
9. the preparation method of a pair transistor zero capacitance dynamic ram, pair transistor wherein is two cascade MOS transistor T1 and the T2 that is formed on the common substrate, it is characterized in that, is equipped with operation before comprising, wherein: be equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid;
Inject through ion and to make that transoid is the doping type identical with source-drain area under the grid voltage situation not adding near the channel region of source electrode and drain electrode for the channel region of T1, and make in the channel region of T2 that transoid is the doping type opposite with source-drain area under the grid voltage situation not adding near the channel region of source electrode and drain electrode.
10. the preparation method of pair transistor zero capacitance dynamic ram according to claim 9 is characterized in that, when two cascade MOS transistor T1 and T2 are the NMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid;
Carry out photoetching, the T1 regional window is opened, the T2 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection P in back or As ions, cause under the grid that transoid is the N type under the grid voltage situation not adding near the channel region of source and leakage;
Carry out photoetching, the T2 regional window is opened, the T1 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection B in back or BF
2Perhaps BF or In ion, transoid is the P type under the grid voltage situation not adding to cause under the grid of source and leakage diffusion zone.
11. the preparation method of pair transistor zero capacitance dynamic ram according to claim 10 is characterized in that, when two cascade MOS transistor T1 and T2 are the PMOS structure all, are equipped with operation before said and comprise:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, form T1 and T2 gate trench separately respectively through wet the eat-backing of appended sample grid;
Carry out photoetching, the T1 regional window is opened, the T2 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection B in back or BF
2Perhaps BF or In ion cause under the grid that transoid is the P type under the grid voltage situation not adding near the channel region of source and leakage;
Carry out photoetching, the T2 regional window is opened, the T1 regional window is closed, carry out angle tilt, rotate 180 degree two-way injection P in back or As ions, transoid is the N type under the grid voltage situation not adding to cause under the grid of source and leakage diffusion zone.
12. the preparation method according to claim 10 or 11 described pair transistor zero capacitance dynamic rams is characterized in that, said twice ion is injected the operation of compensation and can be exchanged.
13. the preparation method according to claim 10 or 11 described pair transistor zero capacitance dynamic rams is characterized in that, adopts annealing of rapid thermal treatment or transient peak or flash annealing to inject ion to activate.
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