CN108630521B

CN108630521B - Method for manufacturing semiconductor device

Info

Publication number: CN108630521B
Application number: CN201710161581.0A
Authority: CN
Inventors: 刘佳
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-03-17
Filing date: 2017-03-17
Publication date: 2020-11-03
Anticipated expiration: 2037-03-17
Also published as: CN108630521A

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS (N-channel metal oxide semiconductor) region, a pseudo gate structure consisting of a gate dielectric layer and a pseudo gate electrode layer which are stacked from bottom to top is formed on the semiconductor substrate of the NMOS region, and the pseudo gate structure is formed in the dielectric layer; forming a metal hard mask layer covering the pseudo gate structure and the dielectric layer; removing the metal hard mask layer in the NMOS area; forming a covering layer covering the metal hard mask layer; performing ion implantation on the pseudo gate structure of the NMOS region to inhibit the hot carrier injection effect of the semiconductor device; and removing the covering layer. According to the manufacturing method of the semiconductor device, the covering layer is formed on the metal hard mask layer, so that the metal hard mask layer is prevented from polluting an ion injection cavity, ion injection can be carried out on the grid structure, and the hot carrier injection effect of the NMOS device is inhibited.

Description

Method for manufacturing semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.

Background

As the integration of semiconductor devices continues to increase and their feature sizes become smaller, the Source/Drain and Source/Drain extensions (Source/Drain extensions) become correspondingly shallower, and the current state of the art requires semiconductor devices with Source/Drain junctions that are less than 1000 angstroms deep and, ultimately, may require junctions that are on the order of 200 angstroms or less deep.

The reduction of junction depth requires lower heat treatment temperatures, which (less than 500 degrees celsius, or even lower) cause the lateral dimensions of the junction to be reduced, the reduction in the lateral dimension of the junction will cause the electric field between the junction and the channel region that is created during operation of the device to spike at the interface edge of the junction and the channel region, that is, a high electric field is formed at the boundary edge of the junction and the channel region, electrons are accelerated into high-energy particles by the high electric field in the moving process, the energetic particle collisions produce electron-hole pairs, called hot carriers, which gain energy from the electric field, may enter the gate dielectric layer, or gate electrode, and in turn affect the threshold voltage control of the device and the drift of transconductance, that is, an HCI (Hot carrier injection) effect is generated, thereby causing a rise in threshold voltage, a fall in saturation current, a fall in carrier mobility, and the like.

The conduction carriers of the NMOS device are electrons, the conduction carriers of the PMOS transistor are holes, and the mobility of the electrons is much higher than that of the holes, so that the electrons can obtain larger energy under the same electric field, and under a high electric field, the electrons are accelerated to be "hot electrons", and the hot holes are difficult to appear. Therefore, how to suppress the HCI effect of the NMOS device, i.e. to suppress hot carriers from entering the gate dielectric layer or penetrating the gate dielectric layer to enter the gate, is a problem to be solved by those skilled in the art.

Currently, in order to improve HCI of NMOS devices, an optimized method of LDD (Lightly Doped Drain) ion implantation is usually adopted, and by reducing the dose of LDD ion implantation and increasing the LDD implantation energy, a deeper LDD junction is obtained, and the lateral electric field strength is reduced, thereby improving HCI. However, the above method has a limited Effect and may cause problems such as Short Channel Effect (SCE).

Therefore, in order to solve the above problems, it is necessary to provide a new method for manufacturing a semiconductor device.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, the method comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises an NMOS (N-channel metal oxide semiconductor) region, a pseudo gate structure consisting of a gate dielectric layer and a pseudo gate electrode layer which are stacked from bottom to top is formed on the semiconductor substrate of the NMOS region, and the pseudo gate structure is formed in the dielectric layer;

forming a metal hard mask layer covering the pseudo gate structure and the dielectric layer;

removing the metal hard mask layer in the NMOS area;

forming a covering layer covering the metal hard mask layer;

performing ion implantation on the pseudo gate structure of the NMOS region to inhibit the hot carrier injection effect of the semiconductor device;

and removing the covering layer.

Illustratively, the implanted ions are fluorine ions.

Illustratively, after removing the metal hard mask layer in the NMOS region and before forming the capping layer, the method further includes removing the dummy gate electrode layer to a predetermined depth.

Illustratively, the material of the covering layer is SiO₂。

Illustratively, an interface layer is further formed between the gate dielectric layer and the semiconductor substrate, wherein ions are implanted at an interface of the gate dielectric layer and the interface layer in the ion implantation step.

Illustratively, the semiconductor substrate further comprises a PMOS region, a dummy gate structure is formed on the semiconductor substrate of the PMOS region, and the dummy gate structure is formed in the dielectric layer.

Illustratively, embedded germanium-silicon structures are formed on two sides of the dummy gate structure of the PMOS region.

Illustratively, the metal hard mask layer also covers the dummy gate structure of the PMOS region.

Illustratively, the step of removing the metal hard mask layer in the NMOS region includes:

forming a photoresist layer on the metal hard mask layer;

patterning the photoresist layer to enable a window of the photoresist layer to expose the NMOS region;

and performing etching to remove the metal hard mask layer in the NMOS area.

Illustratively, the gate dielectric layer is a high-k dielectric layer, and sidewall structures are further formed on two sides of the dummy gate structure.

According to the manufacturing method of the semiconductor device, the covering layer is formed on the metal hard mask layer, so that the metal hard mask layer is prevented from polluting an ion injection cavity, ion injection can be carried out on the grid structure, and the hot carrier injection effect of the NMOS device is inhibited.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1 shows a process flow diagram of a method for manufacturing a semiconductor device according to the present invention.

Fig. 2A-2F are schematic cross-sectional views of devices respectively obtained by steps carried out in sequence according to the method of the invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Since the conduction carriers of the NMOS device are electrons, a high electric field is formed at the boundary edge of the junction and the channel region, and the electrons are accelerated into "hot electrons" by the high electric field in the moving process, and enter the gate dielectric layer or the gate electrode, which affects the threshold voltage control and the transconductance shift of the device, i.e., HCI (hot carrier injection) effect is generated, thereby causing the increase of threshold voltage, the decrease of saturation current, the decrease of carrier mobility, and the like. How to suppress the HCI effect of an NMOS device, i.e., to suppress hot carriers from entering a gate dielectric layer or penetrating the gate dielectric layer to enter a gate electrode, is a problem to be solved by those skilled in the art.

Fluorine ions are injected into the grid electrode through an ion injection process, and the injected fluorine ions can form stable chemical bonds at the interface of the grid electrode dielectric layer, so that the HCI effect resistance of the NMOS device is effectively improved. However, in the conventional method for manufacturing a metal gate, dummy gate structures are usually formed in an NMOS region and a PMOS region on a substrate, a dielectric layer covering the dummy gate structures is deposited, planarization is performed to make the dielectric layer flush with the upper surface of the dummy gate structures, then a metal hard mask layer covering only the PMOS region is formed on the dummy gate structures and the dielectric layer, etching is performed to empty the dummy gate electrode layer in the NMOS region, and finally a metal material is filled to form the metal gate. Since the metal hard mask layer is used in the process, the metal hard mask layer can pollute the ion implantation chamber in the ion implantation process, and thus, the fluorine ion implantation cannot be carried out.

In view of the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

removing the metal hard mask layer in the NMOS area;

forming a covering layer covering the metal hard mask layer;

and removing the covering layer.

The implanted ions are fluorine ions.

After the metal hard mask layer in the NMOS region is removed and before the covering layer is formed, the method further comprises the step of removing the dummy gate electrode layer with a preset depth.

The covering layer is made of SiO₂。

An interface layer is also formed between the gate dielectric layer and the semiconductor substrate, wherein ions are implanted at an interface of the gate dielectric layer and the interface layer in the ion implantation step.

The semiconductor substrate further comprises a PMOS region, a dummy gate structure is formed on the semiconductor substrate of the PMOS region, and the dummy gate structure is formed in the dielectric layer. And embedded germanium-silicon structures are formed on two sides of the pseudo gate structure of the PMOS region. The metal hard mask layer also covers the dummy gate structure of the PMOS region.

The step of removing the metal hard mask layer in the NMOS area comprises the following steps:

forming a photoresist layer on the metal hard mask layer;

and performing etching to remove the metal hard mask layer in the NMOS area.

The gate dielectric layer is a high-k dielectric layer, and side wall structures are formed on two sides of the pseudo gate structure.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

[ exemplary embodiment one ]

A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail below with reference to fig. 1 and fig. 2A to 2F.

First, step 101 is executed, as shown in fig. 2A, a semiconductor substrate 200 is provided, the semiconductor substrate 200 includes an NMOS region 201, a dummy gate structure formed by a gate dielectric layer 205 and a dummy gate electrode layer 206 stacked from bottom to top is formed on the semiconductor substrate 200 of the NMOS region 201, and the dummy gate structure is formed in a dielectric layer 210.

Specifically, the constituent material of the semiconductor substrate 200 may be undoped single-crystal silicon, impurity-doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stack (SSOI), silicon-on-insulator germanium (S-SiGeOI), silicon-on-insulator germanium (SiGeOI), germanium-on-insulator (GeOI), or the like. As an example, in the present embodiment, the constituent material of the semiconductor substrate 200 is monocrystalline silicon. An isolation structure 203 is formed in the semiconductor substrate 200, and the isolation structure 203 is, for example, a Shallow Trench Isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. In the present embodiment, the isolation structure 203 is a shallow trench isolation structure that divides the semiconductor substrate 200 into an NMOS region and a PMOS region. Various well structures are also formed in the semiconductor substrate 200, and are omitted from the drawing for simplicity.

In the present embodiment, a dummy gate structure is formed on each of the NMOS region 201 and the PMOS region 202 of the semiconductor substrate 200, and includes, as an example, an interface layer 204, a gate dielectric layer 205, and a dummy gate electrode layer 206 stacked from bottom to top. The constituent material of the interfacial layer 204 includes silicon oxide (SiO)_x) Which functions to improve the interface characteristics between the gate dielectric layer 205 and the semiconductor substrate 200; gate dielectric layer 205 is preferably a high-k dielectric layer, and has a k value (dielectric constant) of usually 3.9 or more, and is made of a material such as hafnium oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, and particularly preferably hafnium oxide, zirconium oxide, or aluminum oxide; the material of the dummy gate electrode layer 206 includes polysilicon, silicon nitride, or amorphous carbon, and is preferably polysilicon.

Further, as an example, sidewall structures 207 are formed at both sides of the dummy gate structure. In one embodiment, the sidewall structure 207 comprises at least an oxide layer and a nitride layer.

An embedded sige layer 209 is formed in the semiconductor substrate 200 in the PMOS region 202 on both sides of the dummy gate structure, and the formation process generally includes the following steps: forming sigma-shaped grooves in PMOS regions on two sides of the pseudo gate structure by adopting a process of firstly performing dry etching and then performing wet etching; embedded sige layer 209 is formed to completely fill the sigma-shaped recess using a selective epitaxial growth process, which may employ one of Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), and Molecular Beam Epitaxy (MBE), to form embedded sige layer 209 that may be doped with boron. The process of firstly performing dry etching and then performing wet etching comprises the following specific steps: firstly, the semiconductor substrate of the PMOS regions at two sides of the pseudo gate structure is longitudinally etched by adopting a dry etching process to form a groove, in the embodiment, CF is adopted₄HBr is used as main etching gas, the temperature is 40-60 ℃, the power is 200-; and continuously etching the groove by adopting an isotropic dry etching process to form an oval groove below the groove, namely forming a bowl-shaped groove₂And NF₃As main etching gas, the temperature is 40-60 ℃, the power is 100-; and finally, expanding and etching the bowl-shaped groove by adopting a wet etching process to form the sigma-shaped groove, wherein the temperature of the wet etching is 30-60 ℃, the time is determined according to the expected size of the sigma-shaped groove and is generally 100-300s, and in the embodiment, a tetramethylammonium hydroxide (TMAH) solution is adopted as an etching solution of the wet etching.

Salicide is formed on top of the embedded sige layer 209 and on the source/drain regions of the NMOS region 201 and is omitted from the figure for simplicity. The process of forming the salicide is well known to those skilled in the art and will not be described herein.

After the salicide is formed, a contact hole etch stop layer 208 and a dielectric layer 210 are formed on the semiconductor substrate 200 to completely cover the dummy gate structure. The contact hole etch stop layer 208 is preferably made of silicon nitride, and the dielectric layer 210 is preferably made of an oxide formed by a plasma enhanced chemical vapor deposition process. Then, chemical mechanical polishing is performed to expose the top of the dummy gate structure.

Next, step 102 is performed to form a metal hard mask layer 211 covering the dummy gate structure and the dielectric layer 210. The metal hard mask layer 211 covers the dielectric layer 210 and the dummy gate structures of the NMOS region 201 and the PMOS region 202. The metal hard mask layer 211 may be TiN, Ti, Ta, or TaN, and may have a thickness of, for example, 50 to 200 angstroms. Of course, other suitable metal materials may be used for the metal hard mask 211. Illustratively, the metal hard mask layer 211 may be formed using an MOCVD method (metal organic chemical vapor deposition), a PVD method (physical vapor deposition), or an ALD method (atomic layer deposition).

Next, step 103 is executed to remove the metal hard mask layer 211 located in the NMOS region 201. Specifically, a patterned photoresist layer 212 is first formed on the metal hard mask layer 211, and a window of the photoresist layer exposes the NMOS region. Illustratively, a photoresist layer is coated on the metal hard mask layer 211, and exposure, development, and the like are performed to obtain a photoresist layer 212 covering only the PMOS region 202.

Next, as shown in fig. 2B, etching is performed by using the patterned photoresist layer 212 as a mask to remove the metal hard mask layer in the NMOS region. The photoresist layer 212 may then be removed using ashing or the like.

Next, as shown in fig. 2C, the dummy gate electrode layer in the NMOS region 201 is removed to a predetermined depth. In this embodiment, the removing is performed by a dry etching process, and the process parameters include: the flow rate of the etching gas HBr is 20-500sccm, the pressure is 2-40mTorr, and the power is 100-. After removing the dummy gate electrode layer of a predetermined depth, the remaining dummy gate electrode layer 206' can ensure that the surface of the gate dielectric layer 205 is not damaged while ions implanted by ion implantation are allowed to enter the semiconductor substrate 200.

Next, step 104 is performed, as shown in the figure2D, a capping layer 213 is formed overlying the metal hard mask layer. The cover layer 213 completely covers the metal hard mask layer 211, thereby preventing the metal hard mask layer 211 from contaminating the ion implantation chamber during the ion implantation process. In this embodiment, the material of the capping layer 213 is SiO₂The forming method thereof includes, but is not limited to, Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), and the like. Illustratively, the capping layer 213 also covers the dielectric layer 210 of the NMOS region 201 and the bottom and sidewalls of the dummy gate structure, and its thickness should not affect the subsequent ion implantation.

Next, step 105 is performed, as shown in fig. 2E, to perform ion implantation on the dummy gate structure of the NMOS region to suppress the hot carrier injection effect of the semiconductor device. In the present embodiment, the implanted ions are fluorine ions. Other ions that can suppress the HCI effect of NMOS devices may also be used for ion implantation. Since the capping layer 213 is formed on the metal hard mask layer 211 in the present invention, the metal hard mask layer 211 does not contaminate the ion implantation chamber. Illustratively, the implantation energy of fluorine ions ranges from 1KeV to 20KeV, and the implantation dose ranges from 1E14/cm²To 3E15/cm²(ii) a The fluorine ions implanted into the dummy gate electrode layer 206 'pass through the dummy gate electrode layer 206', the gate dielectric layer 205 and the interface layer 204 until entering the semiconductor substrate 200 below the interface layer 204. A heat treatment process may then be performed. In this embodiment, the fluorine ions form Hf-F and Si-F bonds at the interface between the gate dielectric layer 205 and the interface layer 204 and at the interface between the interface layer 204 and the semiconductor substrate 200, and since the Hf-F and Si-F bonds have high energy, interface states are not easily generated during the operation of the NMOS device, which is beneficial to reducing high-speed electrons entering the gate dielectric layer 205, thereby suppressing the hot carrier injection effect of the NMOS device and prolonging the service life of the device. In addition, annealing using hydrogen or hydrogen plasma as an annealing atmosphere can promote diffusion of fluorine ions previously implanted into the semiconductor substrate 200, so that the fluorine ions are distributed more uniformly at the interface between the gate dielectric layer 205 and the interface layer 204 and the interface between the interface layer 204 and the semiconductor substrate 200, thereby further improving the interface state.

Next, step 106 is performed, as shown in FIG. 2F, to remove the capping layer. Etching may be performed using a dry etching or wet etching process to remove the capping layer so as to perform a subsequent process. In this embodiment, the removing is performed by a plasma etching process, and the process parameters include: etching gas H₂The flow rate is 100-. Illustratively, the etching step also removes the remaining dummy gate electrode layer 206' to form a recess that fills the metal gate electrode.

And then, filling a metal material in the groove to form a metal gate. As an example, the material of the metal gate material layer includes tungsten, aluminum, or the like. The metal gate may further include a plurality of stacked layers, such as a work function layer and a barrier layer. The method for forming the metal gate comprises the steps of depositing a metal gate material layer by using an atomic layer deposition process, a physical vapor deposition process or a chemical vapor deposition process and the like, and then performing a planarization process, such as a chemical mechanical polishing process, on the surface of the device until the interlayer dielectric layer is exposed.

Then, the subsequent steps in the existing process may be continued, for example, a mask layer covering the NMOS region 201 is formed; removing the dummy gate electrode layer of the PMOS region 202 to form a groove; and filling a metal material in the groove to form a metal gate electrode and the like, which is not described herein for brevity.

Thus, the description of the steps related to the method of manufacturing a semiconductor device of the embodiment of the present invention is completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above-described steps but also other necessary steps before, during or after the above-described steps, which are included in the scope of the manufacturing method of the present embodiment.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

removing the metal hard mask layer in the NMOS area;

forming a covering layer covering the metal hard mask layer;

and removing the covering layer.

2. The method of claim 1, wherein the implanted ions are fluorine ions.

3. The method according to claim 1, further comprising a step of removing the dummy gate electrode layer to a predetermined depth after removing the metal hard mask layer in the NMOS region and before forming the capping layer.

4. The method of claim 1, wherein the material of the cap layer is SiO₂。

5. The manufacturing method according to claim 1, wherein an interface layer is further formed between the gate dielectric layer and the semiconductor substrate, wherein ions are implanted at an interface of the gate dielectric layer and the interface layer in the ion implantation step.

6. The method of manufacturing of claim 1, wherein the semiconductor substrate further comprises a PMOS region, wherein a dummy gate structure is formed on the semiconductor substrate in the PMOS region, and wherein the dummy gate structure is formed in the dielectric layer.

7. The method of claim 6, wherein embedded SiGe structures are formed on both sides of the dummy gate structure in the PMOS region.

8. The method of claim 6, wherein the metal hard mask layer further covers a dummy gate structure of the PMOS region.

9. The method of claim 8, wherein the step of removing the metal hard mask layer in the NMOS region comprises:

forming a photoresist layer on the metal hard mask layer;

and performing etching to remove the metal hard mask layer in the NMOS area.

10. The method of claim 1, wherein the gate dielectric layer is a high-k dielectric layer, and sidewall structures are formed on both sides of the dummy gate structure.