CN107045985B - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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CN107045985B
CN107045985B CN201610083793.7A CN201610083793A CN107045985B CN 107045985 B CN107045985 B CN 107045985B CN 201610083793 A CN201610083793 A CN 201610083793A CN 107045985 B CN107045985 B CN 107045985B
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forming
substrate
layer
gate structure
region
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CN107045985A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure, comprising: forming a substrate including a peripheral region for forming an input-output device; forming a pseudo gate structure on the surface of the substrate, wherein the pseudo gate structure comprises a pseudo gate, and the pseudo gate structure positioned in the peripheral region is a peripheral region pseudo gate structure; carrying out a light doping leakage process on the substrates on two sides of the peripheral region pseudo gate structure to form a first doping layer; annealing the first doping layer to homogenize the distribution of doped ions in the first doping layer; forming a source region or a drain region in the substrate at two sides of the pseudo gate structure; and forming a metal gate structure. According to the invention, after the step of forming the first doping layer, the first doping layer is subjected to annealing treatment, so that the doping ions in the first doping layer are uniformly distributed, the performance of the first penetration preventing layer can be effectively improved, the shallow junction can be maintained, the short channel effect can be further prevented, the channel leakage current can be reduced, and the performance of the formed semiconductor structure can be improved.

Description

Method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a semiconductor structure.
Background
In a semiconductor device, a transistor is an important basic device. The basic structure of a transistor includes three main regions: source (Source), Drain (Drain), and Gate (Gate). Wherein the source and drain are formed by high doping. Depending on the device type, N-type doping (NMOS) and P-type doping (PMOS) can be distinguished.
As the integrated circuit is developed to the ultra-large scale integrated circuit, the circuit density inside the integrated circuit is increased, the number of the contained components is increased, and the sizes of the components are reduced. As the size of MOS devices decreases, the channels of MOS devices shrink accordingly. Due to the shortened channel, the graded channel approximation of MOS devices is no longer true, and various adverse physical effects (especially short channel effects) are highlighted, which degrade device performance and reliability, limiting further device scaling. Currently, an Ultra Shallow Junction (Ultra Shallow Junction) structure is generally used to improve the short channel effect of the device.
The ultra-shallow junction structure is that light doped (LDD) regions are arranged at two ends of a channel region between a heavily doped source electrode and a Drain electrode, so that the light doped region (namely, a light doped Drain region) of the Drain region bears partial voltage to control the short channel effect of a transistor and improve the performance of a device.
However, transistors formed by this method still have junction leakage problems that affect the performance of the devices formed.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which can inhibit junction leakage of an ultra-shallow junction device and improve the performance of a formed transistor.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
forming a substrate including a peripheral region for forming an input-output device;
forming a pseudo gate structure on the surface of the substrate, wherein the pseudo gate structure comprises a pseudo gate, and the pseudo gate structure positioned in the peripheral region is a peripheral region pseudo gate structure;
carrying out a light doping leakage process on the substrates on two sides of the peripheral region pseudo gate structure to form a first doping layer;
annealing the first doping layer to homogenize the distribution of doped ions in the first doping layer;
forming a source region or a drain region in the substrate at two sides of the pseudo gate structure;
forming a dielectric layer covering the pseudo gate structure, the source region or the drain region on the substrate, wherein the dielectric layer exposes the pseudo gate;
removing the peripheral region dummy gate to form a first opening;
and forming a metal gate structure in the first opening.
Optionally, the annealing the first doped layer includes: and annealing the first doping layer in a transient enhanced diffusion annealing mode.
Optionally, the annealing the first doped layer by a transient enhanced diffusion annealing method includes: the temperature of the annealing treatment is in the range of 750 ℃ to 850 ℃.
Optionally, the annealing the first doped layer by a transient enhanced diffusion annealing method includes: the time of the annealing treatment is in the range of 20 minutes to 60 minutes.
Optionally, the step of performing the light doping drain process on the substrates on the two sides of the peripheral region pseudo gate structure includes: a first ion implantation is carried out on the substrates on two sides of the peripheral region pseudo gate structure to form a first doping layer.
Optionally, the step of performing the first ion implantation includes: the formed input-output device is an NMOS device, the first ion implantation ions are N-type ions, the implantation energy is in the range of 3KeV to 12KeV, and the implantation dosage is in the range of 5.0E13atom/cm2 to 1.0E15atom/cm 2; or, the formed input-output device is a PMOS device, the first ion implantation ions are P-type ions, the implantation energy is in the range of 4KeV to 10KeV, and the implantation dosage is in the range of 5.0E13atom/cm2 to 8.0E14atom/cm 2.
Optionally, after the step of forming the substrate and before the step of forming the dummy gate structure on the surface of the substrate, the forming method further includes: forming a first penetration-preventing layer in the substrate of the peripheral area; and in the step of forming first doping layers in the substrate at two sides of the peripheral region pseudo gate structure, the first doping layers are positioned above the first punch-through prevention layer.
Optionally, the step of forming a first penetration preventing layer in the substrate in the peripheral region includes: and carrying out second ion implantation on the substrate in the peripheral area so as to form a first anti-punch-through layer in the substrate in the peripheral area.
Optionally, the semiconductor structure includes a fin field effect transistor, and a fin portion is formed on the surface of the substrate; the step of performing a second ion implantation comprises: and performing second ion implantation on the substrate of the peripheral region by adopting a lateral diffusion implantation process so as to form the first penetration preventing layer in the fin part on the surface of the substrate of the peripheral region.
Optionally, the step of performing the second ion implantation includes: the formed input-output device is an NMOS device, the second ion implantation ions are P-type ions, the implantation energy is in the range of 10KeV to 30KeV, and the implantation dosage is in the range of 5.0E12 atom/cm2 to 1.0E14atom/cm 2; or the formed input-output device is a PMOS device, the second ion implantation ions are N-type ions, the implantation energy is in the range of 60KeV to 120KeV, and the implantation dosage is in the range of 1.0E12 atom/cm2 to 5.0E13atom/cm 2.
Optionally, in the step of forming the substrate, the substrate further includes a core region for forming a core device; in the step of forming the dummy gate structure on the surface of the substrate, the dummy gate structure positioned in the core region is the core region dummy gate structure; after the step of annealing the first doping layer and before the step of forming a source region or a drain region in the substrate on both sides of the dummy gate structure, the forming method further includes: and carrying out a light doping leakage process on the substrates on the two sides of the core region pseudo gate structure to form a second doping layer.
Optionally, the light-doping drain process is performed on the substrates on the two sides of the pseudo gate structure in the outer core region, and the step of forming the second doping layer includes: and performing third ion implantation on the substrate at two sides of the pseudo gate structure of the core region to form a second doped layer.
Optionally, the third ion implantation step includes: the formed core device is an NMOS device, the third ion implantation ions are N-type ions, the implantation energy is in the range of 1KeV to 4KeV, and the implantation dosage is in the range of 8.0E13 atom/cm2 to 1.0E15atom/cm 2; alternatively, the formed core device is a PMOS device, the third ion implantation ions are P-type ions, the implantation energy is in the range of 2KeV to 4KeV, and the implantation dosage is in the range of 8.0E13 atom/cm2 to 8.0E14atom/cm 2.
Optionally, the forming method further includes: after the dielectric layer is formed, removing the dummy grid electrode of the dummy grid structure in the core region to form a second opening before removing the dummy grid electrode in the peripheral region to form a first opening; forming a second anti-punch-through layer in the core region substrate below the second opening, wherein the second anti-punch-through layer is located below the second doping layer; in the step of forming the metal gate structure, the metal gate structure is formed in the second opening.
Optionally, the step of forming the second penetration-preventing layer includes: and performing fourth ion implantation on the substrate at the bottom of the opening to form a second penetration preventing layer below the second doping layer.
Optionally, the step of performing the fourth ion implantation includes: the formed core device is an NMOS device, the fourth ion implantation ions are P-type ions, the implantation energy is in the range of 10KeV to 30KeV, and the implantation dosage is in the range of 1.0E13 atom/cm2 to 2.0E14 atom/cm 2; alternatively, the formed core device is a PMOS device, the fourth ion implantation ions are N-type ions, the implantation energy is in the range of 60KeV to 120KeV, and the implantation dosage is in the range of 5.0E12 atom/cm2 to 8.0E13atom/cm 2.
Optionally, the semiconductor structure includes a fin field effect transistor, a fin portion is formed on the surface of the substrate, and the fin portion located in the core region is a fin portion in the core region; and in the step of forming the second doping layer, forming the second doping layer in the fin parts of the core region at two sides of the pseudo gate structure of the core region.
Optionally, the semiconductor structure includes a fin field effect transistor, a fin portion is formed on the surface of the substrate, and the fin portion located in the peripheral region is a peripheral region fin portion; the step of forming the substrate comprises: raising the semiconductor substrate; forming a patterned mask layer on the semiconductor substrate; etching the semiconductor substrate by taking the mask layer as a mask to form the substrate and the fin part; after the step of forming the substrate, before the step of forming the dummy gate structure, the forming method further includes: removing the mask layer; in the step of forming a dummy gate structure on the surface of the substrate, the dummy gate structure crosses the fin and covers partial surfaces of the side wall and the top of the fin; in the step of forming the first doping layer, forming the first doping layer in the fin part of the peripheral region at two sides of the pseudo gate structure of the peripheral region; in the step of forming the source region or the drain region, forming the source region or the drain region in the fin parts at two sides of the pseudo gate structure; the step of forming the metal gate structure comprises: the metal gate structure crosses the fin and covers the sidewall and the top of the fin.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, after the step of forming the first doping layer, the first doping layer is subjected to annealing treatment, so that the doping ions in the first doping layer are uniformly distributed, the performance of the first penetration preventing layer can be effectively improved, the shallow junction can be maintained, the short channel effect can be further prevented, the channel leakage current can be reduced, and the performance of the formed semiconductor structure can be improved.
Drawings
Fig. 1 to 9 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
In the prior art, when forming a source region or a Drain region of a transistor, two implants are performed, a shallow implant, which is sequentially referred to as a Lightly Doped Drain (LDD) implant, followed by a medium or high dose source/Drain implant. Wherein the lightly doped drain implant uses a high mass of dopant material to render the upper surface of the silicon wafer amorphous. The combination of the high mass material and the surface amorphization helps to maintain shallow junctions, which also helps to reduce channel leakage.
The leakage current of the transistors formed in the prior art is still large. In the prior art, after the lightly doped drain implantation is performed, the doping ions in the doping region are not uniformly distributed, and the concentration gradient is large, so that the performance of the formed shallow junction is influenced, and the performance of the formed semiconductor structure is influenced.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
forming a substrate including a peripheral region for forming an input-output device; forming a pseudo gate structure on the surface of the substrate, wherein the pseudo gate structure comprises a pseudo gate, and the pseudo gate structure positioned in the peripheral region is a peripheral region pseudo gate structure; carrying out a light doping leakage process on the substrates on two sides of the peripheral region pseudo gate structure to form a first doping layer; annealing the first doping layer to homogenize the distribution of doped ions in the first doping layer; forming a source region or a drain region in the substrate at two sides of the pseudo gate structure; forming a dielectric layer covering the pseudo gate structure, the source region or the drain region on the substrate, wherein the dielectric layer exposes the pseudo gate; removing the peripheral region dummy gate to form a first opening; and forming a metal gate structure in the first opening.
According to the invention, after the step of forming the first doping layer, the first doping layer is subjected to annealing treatment, so that the doping ions in the first doping layer are uniformly distributed, the performance of the first penetration preventing layer can be effectively improved, the shallow junction can be maintained, the short channel effect can be further prevented, the channel leakage current can be reduced, and the performance of the formed semiconductor structure can be improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 1 to 9, schematic structural diagrams of steps of an embodiment of a method for forming a semiconductor structure of the present invention are shown.
Referring to fig. 1, a substrate 100 is formed, the substrate 100 including a peripheral region 100i for forming an input-output device.
It should be noted that, in the present embodiment, the formed semiconductor structure is a finfet, accordingly, fins 101 are formed on the surface of the substrate 100, and the fins located in the peripheral region 100i are peripheral region fins. The substrate 100 further includes a core region 100c for forming a core device, and the fin portion located in the core region 100c is a core region fin portion.
The step of forming the substrate 100 includes: providing a semiconductor substrate; forming a patterned mask layer 102 on the semiconductor substrate; and etching the semiconductor substrate by taking the mask layer 102 as a mask to form the substrate 100 and the fin part 101.
The semiconductor substrate is used for providing an operation platform for subsequent processes and etching to form the fin portion 101. The material of the semiconductor substrate is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the semiconductor substrate may also be other semiconductor materials. The invention is not limited in this regard. In this embodiment, the semiconductor substrate is a monocrystalline silicon substrate, so the base 100 and the fin 101 are made of monocrystalline silicon.
In other embodiments of the present invention, the semiconductor substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure. Specifically, the semiconductor substrate may include a substrate and a semiconductor layer on a surface of the substrate. The semiconductor layer may be formed on the substrate surface using a selective epitaxial deposition process. The substrate can be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate; the material of the semiconductor layer is silicon, germanium, silicon carbide, silicon germanium or the like. The selection of the substrate and the semiconductor layer is not limited, and the substrate and the material for forming the fin portion can be selected according to the process requirements or the integration easiness. And the thickness of the semiconductor layer can be controlled by an epitaxial process, so that the height of the formed fin portion 101 can be accurately controlled.
The mask layer 102 is used to define the location and size of the fin 101. The step of forming the patterned mask layer 102 includes: forming a mask material layer on the surface of the semiconductor substrate; forming a first patterning layer on the surface of the mask material layer; and etching the mask material layer by taking the first patterning layer as a mask until the surface of the semiconductor substrate is exposed so as to form a patterned mask layer 102. Specifically, the mask layer 102 is made of silicon nitride.
It should be noted that, in this embodiment, before the step of forming the patterned mask layer 102, the forming method further includes forming a buffer layer (not shown in the figure) on the surface of the semiconductor substrate to improve the problem of reducing the lattice mismatch between the mask layer 102 and the semiconductor substrate. Specifically, in this embodiment, the buffer layer is made of an oxide.
The first patterned layer may be a patterned photoresist layer formed using a coating process and a photolithography process. In addition, in order to reduce the feature size of the fins 101 and the distance between adjacent fins 101, the first patterning layer may be formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned triple patterning (Self-aligned triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
It should be noted that, in the process of forming the fin portion 101, there may be damage or minute unevenness on the surface of the etched semiconductor substrate, and in order to repair the damage or the unevenness on the surface of the semiconductor substrate to improve the performance of the formed semiconductor structure, in this embodiment, after the step of forming the fin portion 101, the forming method further includes: a Liner oxide (Liner oxide) (not shown) is formed on the surface of the substrate 100 and the fin 101. The liner oxide layer may also smooth sharp corners on the surface of the substrate 100 and the fin 101, and serve as a buffer layer between a subsequently formed film and the substrate 100 and the fin 101 to reduce lattice mismatch.
Specifically, the liner oxide layer may be formed by chemical vapor deposition or thermal oxidation. However, in other embodiments of the present invention, the liner oxide layer may not be formed, and the substrate and the fin portion may be annealed to repair the damage, which is not limited in the present invention.
In this embodiment, an isolation structure 103 is further formed between adjacent fins 101 to achieve electrical isolation, and the material thereof may be silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material (dielectric constant is greater than or equal to 2.5 and less than 3.9) or an ultra-low-K dielectric material (dielectric coefficient is less than 2.5).
The step of forming the isolation structure 103 includes: forming an isolation material layer, wherein the isolation material layer is filled between adjacent fins 101, and the top surface of the isolation material layer is higher than the top surface of each fin 101; and removing part of the thickness of the top of the isolation material layer to expose part of the sidewall of the fin 101 to form an isolation structure 103.
With the increase of the density of the semiconductor device, the dimension between adjacent fins 101 is correspondingly reduced, so that the aspect ratio of the trench between adjacent fins 101 is increased, and in order to enable the isolation material layer to be fully filled in the trench between adjacent fins 101, the step of forming the isolation material layer includes: the isolation material layer is formed using a Fluid Chemical Vapor Deposition (FCVD) process.
Referring to fig. 2 and 3, wherein fig. 3 is a sectional view taken along direction a in fig. 2. Forming a dummy gate structure 110 on the surface of the substrate 100, where the dummy gate structure 110 includes a dummy gate 112, and the dummy gate structure 110 located in the peripheral region 100i is a peripheral region dummy gate structure.
The substrate 100 further includes a core region 100c for forming a core device, and therefore, in the step of forming the dummy gate structure 110 on the surface of the substrate 100, the dummy gate structure located in the core region 100c is a core region dummy gate structure.
In addition, in the embodiment, the semiconductor structure includes a fin field effect transistor, and a fin 101 is formed on the surface of the substrate 100. Therefore, in the step of forming the dummy gate structure 110, the dummy gate structure 110 crosses the fin 101 and covers a portion of the surface of the sidewall and the top of the fin 101.
In this embodiment, the forming method further includes: after the step of forming the substrate 100, before the step of forming the dummy gate structure 110, the forming method further includes: a first punch-through prevention layer 104i is formed within the substrate 100 in the peripheral region 100 i.
In the present embodiment, the first punch-through prevention layer 104i is formed in the substrate 100 in the peripheral region 100i by ion doping. The doped ions in the first penetration preventing layer 104i are P-type ions or N-type ions. Specifically, the type of the doped ions in the first anti-punch-through layer 104i is opposite to the type of the transistor to be formed, that is, the type of the doped ions in the first anti-punch-through layer 104i is opposite to the type of the doped ions in the source region or the drain region to be formed subsequently, so that a PN junction can be formed with the source region or the drain region to be formed subsequently, and further, the bottom punch-through phenomenon caused by the too close distance of the bottom of the source region or the drain region can be prevented.
Specifically, the first anti-punch-through layer 104i may be formed in the substrate 100 in the peripheral region 100i by performing a second ion implantation on the substrate in the peripheral region. In this embodiment, the semiconductor structure includes a fin field effect transistor, and the fin 101 is formed on the surface of the substrate 100, so the step of performing the second ion implantation includes: performing a second ion implantation on the substrate 100 of the peripheral region 100i by using a lateral diffusion implantation (lareralstaggle implantation) process, and forming the first anti-punch-through layer 104i in the fin 101 on the surface of the substrate 100 of the peripheral region 100 i.
In this embodiment, when the formed input/output device is an NMOS device, the doped ions in the first anti-punch through layer 104i are P-type ions, such as B, the energy of the second ion implantation is in the range of 10KeV to 30KeV, and the implantation dose is 5.0E12 atom/cm2To 1.0E14atom/cm2Within the range; when the formed input/output device is a PMOS device, the doped ions in the first anti-punch-through layer 104i are N-type ions, such As As, the energy of the second ion implantation is in the range of 60KeV to 120KeV, and the implantation dosage is 1.0E12 atom/cm2To 5.0E13atom/cm2Within the range.
It should be noted that, in the step of forming the substrate 100, the mask layer 102 is further formed on the top surface of the fin 101, so that after the step of forming the substrate 100 and before the step of forming the dummy gate structure 101, the forming method further includes removing the mask layer 102 (as shown in fig. 1) to expose the top surface of the fin 101.
In this embodiment, the mask layer 102 may be removed after the step of performing the second ion implantation. The mask layer 102 may function to protect the fin 101 during the second ion implantation. However, the method of removing the mask layer 102 after the step of forming the first punch-through prevention layer 104i is merely an example, and the sequence of the step of forming the first punch-through prevention layer 104i and the step of removing the mask layer 102 is not limited in the present invention.
With continued reference to fig. 2 and 3, the dummy gate structure 110 further includes an oxide layer 111 on the surface of the substrate 100.
The step of forming the dummy gate structure 110 includes: forming an oxide layer 111, wherein the oxide layer 111 covers the surface of the fin portion 101; forming a dummy gate 112 on the surface of the oxide layer 111, wherein the dummy gate 112 crosses the fin 101 and covers the top and the sidewall of the fin 101.
Specifically, the step of forming the oxide layer 111 covering the surface of the fin portion 110 includes: the oxide layer 111 is formed by In-Situ Steam Generation (ISSG). The oxide layer 111 formed in the in-situ water vapor generation manner is high in density, uniform in thickness, good in step coverage capability and capable of tightly covering the side wall and the top surface of the fin portion 101.
It should be noted that, in order to repair the damage on the surface of the fin 101 in the preceding semiconductor process, before the step of forming the oxide layer 111, the fin 101 is also repaired in this embodiment. Specifically, the repair process includes: a sacrificial layer (not shown) is formed to cover the surface of the fin 101 and removed.
It should be further noted that, due to the higher operating voltage, the subsequently formed input/output device has a thicker gate dielectric layer, so as to obtain a higher threshold voltage. Therefore, the oxide layer 111 formed on the surface of the substrate 100 in the peripheral region 100i is reserved as a part of the gate dielectric layer in the subsequent process, and in order to further improve the dielectric coefficient of the oxide layer 111 and prevent the formed gate dielectric layer from being broken down, in this embodiment, the step of forming the oxide layer 111 further includes: the oxide layer 111 is doped with nitrogen by using a process of Decoupled Plasma Nitridation (DPN) and Post-Nitridation annealing (PNA). However, the method of forming the oxide layer 111 by in-situ water vapor generation and then doping the oxide layer 111 with nitrogen is only an example, and the invention is not limited thereto.
The step of forming the dummy gate 112 includes: forming a pseudo gate material layer on the surface of the oxide layer 111, and forming a second patterned layer 113 on the surface of the pseudo gate material layer; and etching the pseudo gate material layer by taking the second patterning layer 113 as a mask to form the pseudo gate 112. Specifically, in this embodiment, the material of the dummy gate 112 is polysilicon.
The second patterning layer 113 is used to define the size and position of the dummy gate, and also can protect the dummy gate 112 in a subsequent semiconductor process, thereby improving the yield of the semiconductor structure. In this embodiment, the second patterned layer 113 is made of silicon nitride.
With reference to fig. 3, the substrate 100 at both sides of the dummy gate structure 110 in the peripheral region 100i is lightly doped with a drain to form a first doped layer 120 i.
The first doped layer 120i is used for forming a shallow junction to suppress channel leakage current, and can also reduce electric field distribution of a source region or a drain region of a formed transistor in a channel to overcome a hot carrier effect. The dopant ions of the first doped layer 120i are related to the type of transistor formed: when forming an NMOS device, the doping ions of the first doping layer 120i are N-type ions, such as arsenic ions; when forming a PMOS device, the doping ions of the first doping layer 120i are P-type ions, such as boron ions.
In this embodiment, the first punch-through prevention layer 104i is further formed in the substrate 100 in the peripheral region 100i, so that in the step of forming the first doped layer 120i in the substrate 100 at two sides of the pseudo gate structure 110 in the peripheral region 100i, the first doped layer 120i is located above the first punch-through prevention layer 104 i.
In this embodiment, the semiconductor structure includes a fin field effect transistor, a fin 101 is formed on the surface of the substrate 100, and the fin 101 located in the peripheral region 100i is a peripheral region fin; therefore, in the step of forming the first doped layer 120i, the first doped layer 120i is formed in the fin 101 in the peripheral region 100i on both sides of the pseudo gate structure 110 in the peripheral region 100 i.
Specifically, the first doping layer 120i may be formed by performing first ion implantation on the substrate 100 at both sides of the dummy gate structure 110 in the peripheral region 100 i. The first doping layer 120i is formed by ion implantation, and has the advantage that an amorphous state can be formed, and the combination of the doping ions and the amorphous state helps to maintain a shallow junction.
In this embodiment, a first doping layer 120i is formed by performing first ion implantation on the fins 101 on two sides of the peripheral region 100i pseudo gate structure 110, where the first doping layer 120i is located above the first punch-through prevention layer 104i, and the peripheral region 100i fins 101 on two sides of the peripheral region 100i pseudo gate structure 110.
When the formed input/output device is an NMOS device, the doped ions in the first doped layer 120i are N-type ions, such as P, the energy of the first ion implantation is in the range of 3KeV to 12KeV, and the implantation dose is 5.0E13atom/cm2To 1.0E15atom/cm2Within the range; when the formed input/output device is a PMOS device, the doped ions in the first doped layer 120i are P-type ions, such as BF2The energy of the first ion implantation is in the range of 4KeV to 10KeV, and the implantation dosage is 5.0E13atom/cm2To 8.0E14atom/cm2Within the range.
The step of forming the first doped layer 120i by the first ion implantation further includes performing a first activation annealing process on the first ion implantation after the implantation to activate the doped ions in the implanted first doped layer 120 i. In order to avoid the formed first doping layer 120i from diffusing into the channel and affecting the performance of the formed transistor, the first activation annealing process is usually performed by a short-time high-energy annealing method such as spike annealing or laser annealing. Specifically, the annealing temperature for the spike annealing is generally in the range of 950 ℃ to 1100 ℃, while the annealing temperature for the laser annealing is generally in the range of 950 ℃ to 1200 ℃, and the annealing time is generally not more than 10 seconds. The short-time high-energy annealing mode can enable implanted ions to be activated instantly, so that the phenomenon that the ions diffuse into a channel to influence the performance of a formed transistor can be avoided.
Referring to fig. 4, the first doping layer 120i is annealed to homogenize the distribution of the doped ions in the first doping layer 120 i.
The distribution of the doped ions in the first doped layer 120i is relatively concentrated, and the concentration gradient is large, so that the performance of a shallow junction formed subsequently by the first doped layer 120i is influenced, and the inhibition effect of the shallow junction on the channel leakage current of a device is influenced, therefore, the doped ions in the first doped layer 120i are further uniformly diffused through the annealing treatment, so that the performance of the shallow junction formed by the doped ions is improved, and the inhibition effect on the channel leakage current is improved.
Specifically, the step of annealing the first doped layer 120i includes: the first doping layer 120i is annealed by a Transient Enhanced Diffusion (TED) anneal. The transient enhanced diffusion annealing is to enhance the transient enhanced diffusion effect of the doped ions by adopting an annealing mode with relatively low temperature and relatively long time, so that the doped ions in the first doped layer 120i are further uniformly diffused, the concentration gradient of the doped ions is reduced, and the performance of the shallow junction formed by the doped ions is improved.
If the annealing temperature is too low, the doped ions in the first doped layer 120i are difficult to diffuse, the instantaneous enhanced diffusion effect of the doped ions is difficult to enhance, and the purpose of reducing the concentration gradient of the doped ions is realized; if the annealing temperature is too high, the doping ions are activated, and the purposes of enhancing diffusion and reducing concentration gradient cannot be achieved. In this embodiment, the annealing includes: the temperature of the annealing treatment is in the range of 750 ℃ to 850 ℃;
if the annealing treatment time is too short, the doped ions are difficult to have enough time to realize diffusion, and the concentration gradient of the doped ions is difficult to effectively reduce; if the anneal time is too long, the dopant ions are likely to diffuse into the channel and affect the performance of the transistor formed. In this embodiment, the annealing includes: the time of the annealing treatment is in the range of 20 minutes to 60 minutes.
Referring to fig. 5 and 6, a source region or a drain region 130 is formed in the substrate 100 at both sides of the dummy gate structure 110.
The substrate 100 further includes a core region 100c for forming a core device, and thus as shown in fig. 5, after the step of annealing the first doped layer 120i and before the step of forming a source region or a drain region 130 in the substrate 100 on both sides of the dummy gate structure 110, the forming method further includes: the substrate 100 at both sides of the dummy gate structure 110 in the core region 100c is lightly doped with a drain process to form a second doped layer 120 c.
In this embodiment, the semiconductor structure includes a fin field effect transistor, a fin 101 is formed on the surface of the substrate 100, and the fin 101 located in the core region 100c is a core region fin; therefore, in the step of forming the second doped layer 120c, the second doped layer 120c is formed in the fin 101 of the core region 100c on both sides of the pseudo gate structure 110 of the core region 100 c.
Similar to the first doped layer 120i, the second doped layer 120c also functions to form a shallow junction to suppress channel leakage current and reduce the electric field distribution of the source or drain region at the channel to overcome the hot carrier effect. However, since the size of the core device is smaller than that of the input/output device, the doping ion distribution of the second doping layer 120c is relatively concentrated, and the problem of non-uniform distribution is not obvious. Moreover, since the core device has a small size and a relatively short channel, the diffusion of the dopant ions in the second doped layer 120c is more likely to enter the channel to affect the performance of the transistor. Therefore, after the step of annealing the first doped layer 120i, the second doped layer 120c is formed to prevent the diffusion of the dopant ions in the second doped layer 120c from affecting the performance of the formed semiconductor structure.
Specifically, the step of forming the second doped layer 120c in the substrate 100 at two sides of the pseudo gate structure 110 in the core region 100c includes: and performing third ion implantation on the substrate 100 at two sides of the pseudo gate structure 110 in the core region 100c to form a second doped layer 120 c.
In this embodiment, third ion implantation is performed on the fins 101 on two sides of the pseudo gate structure 110 in the core region 100c to form a second doped layer 120c, and the second doped layer 120c is located in the fins 110 in the core region 100c on two sides of the pseudo gate structure 110 in the core region 100 c.
When the core device is an NMOS device, the dopant ions in the second doped layer 120c are N-type ions, such As, the energy of the third ion implantation is in the range of 1KeV to 4KeV, and the implantation dose is 8.0E13atom/cm2To 1.0E15atom/cm2Within the range; when the core device is a PMOS device, the dopant ions in the second doped layer 120c are P-type ions, such as BF2The energy of the third ion implantation is in the range of 2KeV to 4KeV, and the implantation dosage is 8.0E13atom/cm2To 8.0E14atom/cm2Within the range.
Referring collectively to fig. 6, after the step of forming the second doped layer 120c, a source or drain region 130 is formed.
Specifically, the step of forming the source or drain region 130 includes: etching the fin parts 101 on two sides of the dummy gate structure 110 by taking the dummy gate structure 110 as a mask, and forming second openings in the fin parts 101; and filling the second opening with a semiconductor material to form a stress layer, and doping ions in the stress layer to form a source region or a drain region 130.
In this embodiment, the transistors forming the core device and the input/output device are PMOS devices. Therefore, the stress layer is a sigma-shaped stress layer, and the material for filling the opening to form the stress layer is a germanium-silicon material. The sigma-shaped stress layer formed by the silicon germanium material has a convex tip facing the channel in the channel region, so that greater stress can be introduced into the channel region to enable the channel to obtain faster carrier mobility.
Specifically, an epitaxial growth process is adopted to fill the opening with a semiconductor material so as to form a stress layer. In addition, in-situ doping is performed during the epitaxial growth of the semiconductor material to form the source or drain region 130. In this embodiment, the transistor formed is a PMOS device, and therefore P-type ions (e.g., boron ions) are doped in the silicon germanium material during the formation of the source and drain regions 130.
In this embodiment, the semiconductor structure includes a fin field effect transistor, and the fin 101 is formed on the surface of the substrate 100, so in the step of forming the source region or the drain region 130, the source region or the drain region 130 is formed in the fin 101 on both sides of the dummy gate structure 110. The source or drain region 130 is a raised (raised) source or drain region.
Referring to fig. 7, a dielectric layer 140 covering the dummy gate structure 110 and the source or drain region 130 is formed on the substrate 100, and the dielectric layer 140 exposes the dummy gate 112.
It should be noted that, in this embodiment, after the step of forming the source region or the drain region 130 and before the step of forming the dielectric layer 140, the forming method further includes forming a Contact Etch stop layer (not shown) (CESL), where the Contact Etch stop layer is used as an Etch stop layer in a subsequent process of forming an interconnect structure. Specifically, the material of the contact etch stop layer may be silicon nitride.
The dielectric layer 140 is used to achieve electrical isolation between different semiconductor structures. The dielectric layer 140 is made of silicon oxide and may be formed by film deposition techniques such as chemical vapor deposition, physical vapor deposition, and atomic layer deposition.
The step of forming the dielectric layer 140 includes: forming a dielectric material layer covering the isolation structure 103, the fin 101, the dummy gate structure 110 and the source region or the drain region 130; the dielectric material layer is planarized, which is stopped when the top surface of the dummy gate 112 is exposed, to form a dielectric layer 140.
Specifically, in the step of planarizing the dielectric material layer, a chemical mechanical polishing method may be used to planarize the dielectric material layer. Specifically, the chemical mechanical polishing is stopped when the dummy gate 112 is exposed.
Referring to fig. 7 and 8 in combination, the peripheral region dummy gate 112 is removed, and a first opening 160 is formed.
The substrate 100 further includes a core region 100c for forming a core device, and thus the forming method further includes: after the dielectric layer 140 is formed, and before the dummy gate 112 in the peripheral region 100i is removed to form the first opening 160, the dummy gate 112 in the dummy gate structure 110 in the core region 100c is removed to form the second opening 150; a second penetration preventing layer 140c is formed in the core region 100c under the second opening 150 in the substrate 100, and the second penetration preventing layer 140c is located under the second doped layer 120 c.
In this embodiment, the step of removing the dummy gate 112 of the dummy gate structure 110 in the core region 100c includes: forming a third mask covering the peripheral region 100 i; and removing the dummy gate 112 of the dummy gate structure 110 in the core region 100c by using the third mask as a mask and adopting a wet etching manner to form a second opening 150.
The third mask is used to protect the peripheral region 100i during the process of removing the dummy gate structure 110 of the core region 100 c. The material of the third mask includes: the photoresist may be formed by a photoresist coating process.
After the step of forming the second opening 150, a second penetration preventing layer 140c is formed in the substrate 100 in the core region 100c under the second opening 150. Specifically, the step of forming the second penetration preventing layer 140c includes: a fourth ion implantation is performed on the substrate 100 at the bottom of the second opening 150 to form a second anti-punch-through layer 140c under the second doped layer 120 c.
In this embodiment, when the formed core device is an NMOS device, the doped ions in the second anti-punch-through layer 104c are P-type ions, such as B, the energy of the fourth sub-implantation is in the range of 10KeV to 30KeV, and the implantation dose is 1.0E13atom/cm2To 2.0E14 atom/cm2Within the range; when the formed core device is a PMOS device, the dopant ions in the second anti-punch through layer 104c are N-type ions, such As As, the fourth ion implantation energy is in the range of 60KeV to 120KeV, and the implantation dosage is 5.0E12 atom/cm2To 8.0E13atom/cm2Within the range.
With reference to fig. 8, the oxide layer 111 exposed at the bottom of the second opening 150 is removed to expose the surface of the fin 101 in the core region 100 c.
Because the working voltage of the core device is lower, the thickness of the gate dielectric layer of the core device is smaller, and therefore the oxide layer 111 of the core region pseudo gate structure is removed, so that the thickness of the gate dielectric layer of the core region device is reduced. In addition, during the process of forming the first punch-through preventing layer 104c by performing the first punch-through preventing implantation, the oxide layer 111 may be damaged, and removing the oxide layer 111 may also prevent the performance of the transistor formed from being affected by the corresponding damage.
Thereafter, the step of forming the first opening 160 includes: forming a fourth mask covering the core region 100 c; and removing the peripheral region dummy gate 112 by wet etching using the fourth mask as a mask to form a first opening 160.
It should be noted that, because the operating voltage is higher and the thickness of the gate dielectric layer of the input/output device is larger, the oxide layer 111 in the peripheral region 100i is used as a part of the gate dielectric layer to increase the gate dielectric layer of the input/output device.
Referring to fig. 9, a metal gate structure 200 is formed in the first opening 160.
In this embodiment, the substrate 100 includes a core region 100c for forming a core device, and a second opening 150 is formed in a dielectric layer of the core region 100 c. The step of forming the metal gate structure 200 thus further comprises: a metal gate structure 200 is formed in the second opening 150.
The semiconductor structure comprises a fin field effect transistor, wherein a fin 101 is formed on the surface of the substrate 100, so that the metal gate structure 200 crosses the fin 101 and covers partial surfaces of the side wall and the top of the fin 101.
The metal gate structure 200 includes: a high-K dielectric layer 210 and a metal electrode 220 on the surface of the high-K dielectric layer 210. The step of forming the metal gate structure 200 includes: a high-K dielectric layer 210 and a metal gate 220 are sequentially formed.
The step of forming the high-K dielectric layer 210 includes: a high-K dielectric layer is formed covering the bottom and sidewalls of the first opening 160 and the second opening 150. The high-K dielectric layer 210 is used to form a gate dielectric layer of the metal gate structure 200. Specifically, the material of the high-K dielectric layer 210 includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
The step of forming the metal gate 220 includes: filling the first opening 160 and the second opening 150 with a metal material to form the metal gate 220,
it should be noted that, in order to improve the problem of lattice mismatch between the substrate 100 and the high-K dielectric layer 210, in this embodiment, before the step of forming the high-K dielectric layer 210, the forming method further includes: an Interface Layer (IL) (not shown) is formed. In this embodiment, the step of forming the interface layer includes: forming an interface layer covering the bottom and sidewalls of the first opening 160 and the second opening 150; the step of forming the high-K dielectric layer comprises the following steps: and forming a high-K dielectric layer covering the interface layer.
In addition, in order to prevent the metal ions of the metal electrode 220 from diffusing and affecting the performance of the formed semiconductor device, after the high-K dielectric layer 210 is formed and before the metal electrode 220 is formed, the forming method further includes: a protection Layer 221 (not shown) is formed to cover the high-K dielectric Layer 210, and the material of the protection Layer 221 includes titanium nitride.
In summary, in the invention, after the step of forming the first doping layer, the annealing treatment is performed on the first doping layer, so that the doping ions in the first doping layer are uniformly distributed, the performance of the first punch-through prevention layer can be effectively improved, the shallow junction can be maintained, the short channel effect can be further prevented, the channel leakage current can be reduced, and the performance of the formed semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
forming a substrate including a peripheral region for forming an input-output device;
forming a pseudo gate structure on the surface of the substrate, wherein the pseudo gate structure comprises a pseudo gate, and the pseudo gate structure positioned in the peripheral region is a peripheral region pseudo gate structure;
carrying out a light doping leakage process on the substrates on two sides of the peripheral region pseudo gate structure to form a first doping layer;
annealing the first doping layer to homogenize the distribution of doped ions in the first doping layer;
forming a source region or a drain region in the substrate at two sides of the pseudo gate structure;
forming a dielectric layer covering the pseudo gate structure, the source region or the drain region on the substrate, wherein the dielectric layer exposes the pseudo gate;
removing the peripheral region dummy gate to form a first opening;
and forming a metal gate structure in the first opening.
2. The method of forming as claimed in claim 1, wherein the step of annealing the first doped layer comprises: and annealing the first doping layer in a transient enhanced diffusion annealing mode.
3. The method of claim 2, wherein annealing the first doped layer by a transient enhanced diffusion anneal comprises: the temperature of the annealing treatment is in the range of 750 ℃ to 850 ℃.
4. The method of claim 2, wherein annealing the first doped layer by a transient enhanced diffusion anneal comprises: the time of the annealing treatment is in the range of 20 minutes to 60 minutes.
5. The method of claim 1, wherein the step of performing the lightly doped drain process on the substrate at two sides of the dummy gate structure of the peripheral region comprises: a first ion implantation is carried out on the substrates on two sides of the peripheral region pseudo gate structure to form a first doping layer.
6. The method of forming of claim 5, wherein performing a first ion implantation comprises:
the formed input-output device is an NMOS device, the first ion implantation ions are N-type ions, the implantation energy is in the range of 3KeV to 12KeV, and the implantation dosage is 5.0E13atom/cm2To 1.0E15atom/cm2Within the range;
or,
the formed input-output device is a PMOS device, the first ion implantation ions are P-type ions, the implantation energy is in the range of 4KeV to 10KeV, and the implantation dosage is 5.0E13atom/cm2To 8.0E14atom/cm2Within the range.
7. The forming method of claim 1, wherein after the step of forming the substrate and before the step of forming the dummy gate structure on the surface of the substrate, the forming method further comprises: forming a first penetration-preventing layer in the substrate of the peripheral area;
and in the step of forming first doping layers in the substrate at two sides of the peripheral region pseudo gate structure, the first doping layers are positioned above the first punch-through prevention layer.
8. The method of forming as claimed in claim 7, wherein the step of forming a first anti-punch through layer in the substrate in the peripheral region comprises: and carrying out second ion implantation on the substrate in the peripheral area so as to form a first anti-punch-through layer in the substrate in the peripheral area.
9. The method of claim 8, wherein the semiconductor structure comprises a fin field effect transistor, and wherein a fin is formed on the substrate surface;
the step of performing a second ion implantation comprises: and performing second ion implantation on the substrate of the peripheral region by adopting a lateral diffusion implantation process so as to form the first penetration preventing layer in the fin part on the surface of the substrate of the peripheral region.
10. The method of forming of claim 8, wherein performing a second ion implantation comprises:
the formed input/output device is an NMOS device, the second ion implantation ions are P-type ions, the implantation energy is in the range of 10KeV to 30KeV, and the implantation dosage is 5.0E12 atom/cm2To 1.0E14atom/cm2Within the range;
or,
the formed input-output device is a PMOS device, the second ion implantation ions are N-type ions, the implantation energy is in the range of 60KeV to 120KeV, and the implantation dosage is 1.0E12 atom/cm2To 5.0E13atom/cm2Within the range.
11. The method of forming of claim 1, wherein in the step of forming a substrate, the substrate further comprises a core region for forming a core device;
in the step of forming the dummy gate structure on the surface of the substrate, the dummy gate structure positioned in the core region is the core region dummy gate structure;
after the step of annealing the first doping layer and before the step of forming a source region or a drain region in the substrate on both sides of the dummy gate structure, the forming method further includes: and carrying out a light doping leakage process on the substrates on the two sides of the core region pseudo gate structure to form a second doping layer.
12. The method as claimed in claim 11, wherein the step of forming the second doping layer by performing a light doping drain process on the substrate at two sides of the dummy gate structure in the outer core region comprises: and performing third ion implantation on the substrate at two sides of the pseudo gate structure of the core region to form a second doped layer.
13. The method of forming of claim 12, wherein the third ion implantation step comprises:
the formed core device is an NMOS device, the third ion implantation ions are N-type ions, the implantation energy is in the range of 1KeV to 4KeV, and the implantation dosage is 8.0E13atom/cm2To 1.0E15atom/cm2Within the range;
or,
the formed core device is a PMOS device, the third ion implantation ions are P-type ions, the implantation energy is in the range of 2KeV to 4KeV, and the implantation dosage is 8.0E13atom/cm2To 8.0E14atom/cm2Within the range.
14. The method of forming as claimed in claim 11, further comprising: after the dielectric layer is formed, removing the dummy grid electrode of the dummy grid structure in the core region to form a second opening before removing the dummy grid electrode in the peripheral region to form a first opening;
forming a second anti-punch-through layer in the core region substrate below the second opening, wherein the second anti-punch-through layer is located below the second doping layer;
in the step of forming the metal gate structure, the metal gate structure is formed in the second opening.
15. The method of forming as claimed in claim 14, wherein the step of forming a second penetration preventing layer comprises: and performing fourth ion implantation on the substrate at the bottom of the opening to form a second penetration preventing layer below the second doping layer.
16. The method of forming of claim 15, wherein performing a fourth ion implantation comprises:
the formed core device is an NMOS device, the fourth ion implantation ions are P-type ions, the implantation energy is in the range of 10KeV to 30KeV, and the implantation dosage is 1.0E13atom/cm2To 2.0E14 atom/cm2Within the range;
or,
the formed core device is a PMOS device, the fourth ion implantation ions are N-type ions, the implantation energy is in the range of 60KeV to 120KeV, and the implantation dosage is 5.0E12 atom/cm2To 8.0E13atom/cm2Within the range.
17. The method of claim 11, wherein the semiconductor structure comprises a finfet, wherein the substrate has fins formed on a surface thereof, and wherein the fins in the core region are core region fins;
and in the step of forming the second doping layer, forming the second doping layer in the fin parts of the core region at two sides of the pseudo gate structure of the core region.
18. The method of claim 1, wherein the semiconductor structure comprises a fin field effect transistor, wherein fins are formed on the surface of the substrate, and the fins in the peripheral region are peripheral region fins; the step of forming the substrate comprises:
providing a semiconductor substrate;
forming a patterned mask layer on the semiconductor substrate;
etching the semiconductor substrate by taking the mask layer as a mask to form the substrate and the fin part;
after the step of forming the substrate, before the step of forming the dummy gate structure, the forming method further includes: removing the mask layer;
in the step of forming a dummy gate structure on the surface of the substrate, the dummy gate structure crosses the fin and covers partial surfaces of the side wall and the top of the fin;
in the step of forming the first doping layer, forming the first doping layer in the fin part of the peripheral region at two sides of the pseudo gate structure of the peripheral region;
in the step of forming the source region or the drain region, forming the source region or the drain region in the fin parts at two sides of the pseudo gate structure;
the step of forming the metal gate structure comprises: the metal gate structure crosses the fin and covers the sidewall and the top of the fin.
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JPH03278540A (en) * 1990-03-28 1991-12-10 Nec Corp Manufacture of semiconductor device
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