CN108281482B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108281482B CN108281482B CN201710011818.7A CN201710011818A CN108281482B CN 108281482 B CN108281482 B CN 108281482B CN 201710011818 A CN201710011818 A CN 201710011818A CN 108281482 B CN108281482 B CN 108281482B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate is provided with a fin part; forming a grid electrode structure on the fin part, wherein the grid electrode structure stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part; performing first etching treatment to form openings in the fin parts on two sides of the grid structure; performing electrostatic discharge injection on the fin part with the opening, and forming an electrostatic discharge doping region in the fin part, wherein the electrostatic discharge doping region is internally provided with first type ions; and forming a stress layer in the opening to form a source drain doped region on the electrostatic discharge doped region, wherein the source drain doped region is internally provided with second type ions. The technical scheme of the invention effectively improves the quality of the formed stress layer, reduces the stress released by the stress layer in the forming process of the source-drain doped region, is beneficial to improving the performance of the formed stress layer and is beneficial to improving the performance of the formed semiconductor structure.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
As the integrated circuit is developed to the ultra-large scale integrated circuit, the circuit density inside the integrated circuit is increased, the number of the contained components is increased, and the sizes of the components are reduced. As the size of MOS devices decreases, the channels of MOS devices shrink accordingly. Due to the shortened channel, the graded channel approximation of MOS devices is no longer true, and various adverse physical effects (especially short channel effects) are highlighted, which degrade device performance and reliability, limiting further device scaling.
In order to further reduce the size of the MOS device, a multi-plane gate field effect transistor structure is developed to improve the control capability of the gate of the MOS device and suppress the short channel effect. The finfet is a common multi-plane gate transistor.
The fin field effect transistor is of a three-dimensional structure and comprises a substrate, wherein one or more protruding fins are formed on the substrate, and insulating isolation components are arranged among the fins; a gate spans the fin and covers the top and sidewalls of the fin. Since such a three-dimensional structure is greatly different from a transistor of a conventional planar structure, part of the process may have a great influence on the electrical properties of the formed device if it is not operated properly.
In addition, as the technological capability of semiconductor processes is continuously improved, the size of semiconductor devices is continuously reduced. The more significant the damage to semiconductor integrated circuits by Electrostatic Discharge (ESD) becomes. Moreover, with the widespread use of semiconductor chips, the factors causing electrostatic damage to the semiconductor chips are increasing. Statistically, 35% of the products with integrated circuit failures are due to electrostatic discharge problems. Therefore, in order to adjust the junction breakdown voltage (the junction breakdown voltage) and the trigger voltage (trigger voltage) of the esd device, esd injection is required during the formation of the semiconductor structure.
However, the semiconductor structure with the electrostatic discharge injection is often poor in electrical performance.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the electrical performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part; forming a grid electrode structure on the fin part, wherein the grid electrode structure stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part; performing first etching treatment to form openings in the fin parts on two sides of the grid structure; performing electrostatic discharge injection on the fin part with the opening, and forming an electrostatic discharge doping region in the fin part, wherein the electrostatic discharge doping region is internally provided with first type ions; and forming a stress layer in the opening to form a source drain doped region on the electrostatic discharge doped region, wherein the source drain doped region is internally provided with second type ions.
Optionally, the step of performing the first etching process includes: and performing first etching treatment, and forming openings with the depth ranging from 15nm to 40nm in the fin parts on two sides of the grid structure.
Optionally, the step of performing the first etching process includes: the first etching treatment is performed by a dry method.
Optionally, in the step of performing electrostatic discharge injection on the fin portion formed with the opening, when the semiconductor structure is an NMOS device, the process parameters are as follows: the implanted ions are B, the implantation energy is in the range of 3KeV to 15KeV, and the implantation dose is 1.0E12atom/cm2To 2.0E15atom/cm2Within the range; when the semiconductor structure is a PMOS device, the process parameters are as follows: implanting ions P with an implantation energy of 5KeV to 30KeV and an implantation dose of 1.0E12atom/cm2To 2.0E15atom/cm2Within the range.
Optionally, the forming method further includes: after a grid electrode structure is formed on the fin part, before an opening is formed in the fin part on the two sides of the grid electrode structure, lightly doped drain injection is carried out on the fin part on the two sides of the grid electrode structure, a lightly doped area is formed in the fin part, and second type ions are arranged in the lightly doped area; the step of performing electrostatic discharge injection on the fin portion with the opening comprises the following steps: performing electrostatic discharge injection on the fin part with the opening, and forming an electrostatic discharge doping region in the fin part under the lightly doped region; and after performing electrostatic discharge injection on the fin part with the opening and before forming a stress layer in the opening, performing first annealing treatment on the fin part with the lightly doped region and the electrostatic discharge doped region.
Optionally, the step of performing a first annealing process on the fin portion formed with the lightly doped region and the electrostatic discharge doped region includes: and carrying out first annealing treatment on the fin part formed with the lightly doped region and the electrostatic discharge doped region in a spike annealing mode.
Optionally, in the step of performing the first annealing treatment on the fin portion formed with the lightly doped region and the electrostatic discharge doped region, the annealing temperature is in a range of 950 ℃ to 1100 ℃.
Optionally, the forming method further includes: and after the first annealing treatment is carried out on the fin part formed with the lightly doped region and the electrostatic discharge doped region, and before a stress layer is formed in the opening, second etching treatment is carried out to remove partial materials on the side wall and the bottom of the opening.
Optionally, the step of performing the second etching process includes: and performing second etching treatment to remove the material with the thickness of 10nm to 20nm on the side wall and the bottom of the opening.
Optionally, the step of performing second etching on the side wall and the bottom of the opening includes: and carrying out the second etching treatment in a dry method.
Optionally, the step of forming the source-drain doped region on the electrostatic discharge doped region includes: filling a semiconductor material into the opening, and forming a stress layer in the opening; and performing source-drain injection on the stress layer to form a source-drain doped region on the electrostatic discharge doped region.
Optionally, the step of filling the semiconductor material into the opening includes: and filling the semiconductor material into the opening in an epitaxial growth mode.
Optionally, in the step of performing source-drain injection on the stress layer, when the semiconductor structure is a PMOS device, the process parameters are as follows: the implanted ions are B, the implantation energy is in the range of 1KeV to 5KeV, and the implantation dose is 1.0E15atom/cm2To 5.0E15atom/cm2Within the range; when the semiconductor structure is an NMOS device, the implanted ions are P, the implantation energy is in the range of 3KeV to 10KeV, and the implantation dosage is 1.0E15atom/cm2To 5.0E15atom/cm2Within the range.
Optionally, after performing source-drain implantation on the stress layer, the forming method further includes: and carrying out second annealing treatment to activate the doped ions in the source-drain doped region.
Optionally, the step of performing the second annealing process includes: the second annealing treatment is performed by means of spike annealing or laser annealing.
Optionally, in the step of performing the second annealing treatment by spike annealing, the annealing temperature is in a range of 1000 ℃ to 1100 ℃; in the step of performing the second annealing treatment by means of laser annealing, the annealing temperature is in the range of 1200 ℃ to 1300 ℃.
Accordingly, the present invention also provides a semiconductor structure comprising:
a substrate having a fin portion thereon; the grid electrode structure is positioned on the fin part and stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part; the openings are positioned in the fin parts at two sides of the grid structure; and the electrostatic discharge doping region is positioned in the fin part below the opening and is internally provided with first type ions.
Optionally, the depth of the opening is in the range of 15nm to 40 nm.
Optionally, when the semiconductor structure is an NMOS device, the doped ions in the electrostatic discharge doped region are B, and the concentration of the doped ions is 1.0E18atom/cm3To 5.0E19atom/cm3Within the range; when the semiconductor structure is a PMOS device, the doped ions in the electrostatic discharge doped region are P, and the concentration of the doped ions is 1.0E18atom/cm3To 5.0E19atom/cm3Within the range.
Optionally, the semiconductor structure further includes: and the lightly doped region is positioned in the fin parts at two sides of the grid structure, the lightly doped region is internally provided with second type ions, and the lightly doped region is positioned on the electrostatic discharge doping region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the invention, after the opening is formed in the fin parts at two sides of the grid structure; performing electrostatic discharge injection on the fin part with the opening, and forming an electrostatic discharge doping region with first type ions in the fin part; and after the electrostatic discharge doped region is formed, forming a stress layer and a source drain doped region in the opening. Because the electrostatic discharge injection is carried out before the formation of the stress layer and the source-drain doped region, the electrostatic discharge injection does not cause lattice damage to the stress layer and the source-drain doped region, the quality of the formed stress layer can be effectively improved, the stress released by the stress layer in the formation process of the source-drain doped region is reduced, the performance of the formed stress layer is favorably improved, and the performance of the formed semiconductor structure is favorably improved.
In the alternative of the invention, after the grid electrode structure is formed on the fin part, before the opening is formed in the fin part at two sides of the grid electrode structure, the lightly doped drain injection is carried out on the fin part at two sides of the grid electrode structure, and a lightly doped region is formed in the fin part; and after performing electrostatic discharge injection on the fin part with the opening and before forming a stress layer in the opening, performing annealing treatment on the fin part with the lightly doped region and the electrostatic discharge doped region. The annealing treatment is used for activating the doping ions in the lightly doped region, repairing the damage to the fin part after the electrostatic discharge injection and the light doping injection, and providing a good growth surface for the formation of the subsequent stress layer; the method can effectively improve the quality of the formed stress layer, can reduce the times of heating process in the semiconductor forming method, and is beneficial to improving the performance of the formed semiconductor structure.
In an alternative aspect of the present invention, the forming method further includes: and after annealing treatment is carried out on the fin part formed with the lightly doped region and the electrostatic discharge doped region, second etching treatment is carried out before a stress layer is formed in the opening, and partial materials on the side wall and the bottom of the opening are removed. The second etching is used for removing materials which are not repaired on the side wall and the bottom of the opening in the annealing treatment, so that the quality of the bottom and the side wall of the opening in the process of forming the stress layer is improved, a good growth surface is improved for the formation of the stress layer, the quality of the formed stress layer is improved, and the performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure formed in accordance with a corresponding step of a method for forming the semiconductor structure;
fig. 2 to 10 are schematic cross-sectional views corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As can be seen from the background art, the semiconductor structure with the electrostatic discharge injection introduced in the prior art has the problem of poor electrical performance. The reason for the poor electrical performance of the semiconductor structure is analyzed in combination with a method for forming the semiconductor structure by introducing electrostatic discharge injection:
referring to fig. 1, a schematic cross-sectional structure of a semiconductor structure in accordance with the steps of a method for forming a semiconductor structure is shown.
As shown in fig. 1, the method for forming the semiconductor structure includes:
providing a substrate 10 having a fin 11 thereon; forming a gate structure 13 on the fin 11, wherein the gate structure 13 crosses over the fin 11 and covers part of the top and part of the sidewall of the fin 11; and forming a stress layer 14 in the fin part 11 on two sides of the gate structure 13, doping the stress layer 14, and performing annealing treatment to activate doped ions to form a source-drain doped region.
In order to adjust the junction breakdown voltage, the trigger voltage of the electrostatic discharge device is adjusted; in addition, in order to reduce the use of a heating process and reduce the thermal budget (thermal budget) for forming the semiconductor structure, after doping the stress layer 14 and before performing an annealing process, the forming method further includes: and performing electrostatic discharge injection 15 on the fin parts 11 on two sides of the gate structure 13, and forming an electrostatic discharge doped region 16 under the source-drain doped region.
Since the formed esd doped region 16 is located under the source/drain doped region, the depth of the esd doped region 16 is larger, and thus the implantation energy of the esd implant 15 is larger. During the step of performing the electrostatic discharge implantation 15, a stress layer 14 is formed in the fin 11 on both sides of the gate structure 13, so that the implanted ions of the electrostatic discharge implantation 15 pass through the stress layer 14.
The higher energy electrostatic discharge implant 15 causes greater lattice damage within the stress layer 14. Therefore, the annealing treatment after the electrostatic discharge implantation 15 is not only used for activating the doped ions to form the source/drain doped region, but also used for repairing the lattice damage in the stress layer 14. But the process of annealing to repair lattice damage within the stress layer 14 can cause stress relief problems for the stress layer 14. The stress release of the stress layer 14 is too large, which may affect the stress applied by the stress layer 14 to the channel region of the semiconductor structure, and affect the performance of the formed stress layer 14, thereby causing the performance degradation of the formed semiconductor structure and causing the problem of poor electrical performance of the semiconductor structure.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
providing a substrate, wherein the substrate is provided with a fin part; forming a grid electrode structure on the fin part, wherein the grid electrode structure stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part; performing first etching treatment to form openings in the fin parts on two sides of the grid structure; performing electrostatic discharge injection on the fin part with the opening, and forming an electrostatic discharge doping region in the fin part, wherein the electrostatic discharge doping region is internally provided with first type ions; and forming a stress layer in the opening to form a source drain doped region on the electrostatic discharge doped region, wherein the source drain doped region is internally provided with second type ions.
In the technical scheme of the invention, after the opening is formed in the fin parts at two sides of the grid structure; performing electrostatic discharge injection on the formed and opened fin part, and forming an electrostatic discharge doping region with first type ions in the fin part; and after the electrostatic discharge doped region is formed, forming a stress layer and a source drain doped region in the opening. Because the electrostatic discharge injection is carried out before the formation of the stress layer and the source-drain doped region, the electrostatic discharge injection does not cause lattice damage to the stress layer and the source-drain doped region, the quality of the formed stress layer can be effectively improved, the stress released by the stress layer in the formation process of the source-drain doped region is reduced, the performance of the formed stress layer is favorably improved, and the performance of the formed semiconductor structure is favorably improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 2 to 10, schematic cross-sectional structures corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention are shown.
It should be noted that the present embodiment is described by taking a process of forming two non-adjacent N-type transistors as an example. In other embodiments of the present invention, the method for forming a semiconductor structure may also be used to form other semiconductor structures such as a P-type transistor, or may also be used to form an adjacent semiconductor structure, which should not be construed as limiting the present invention.
Referring to fig. 2, a substrate 100 is provided, the substrate 100 having a fin 101 thereon.
The substrate 100 is used to provide a process platform.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for process requirements or easy to integrate.
The fin 101 is used to provide a channel of the finfet.
In this embodiment, the material of the fin 101 is the same as that of the substrate 100, and is also monocrystalline silicon. In other embodiments of the present invention, the material of the fin may be different from the material of the substrate, and may be selected from materials suitable for forming a fin, such as germanium, silicon carbon, or gallium arsenide.
Specifically, the substrate 100 and the fin 101 may be formed simultaneously. The steps of forming the substrate 100 and the fin 101 include: providing an initial substrate; forming a fin mask layer (not shown) on the surface of the initial substrate; and etching the initial substrate by taking the fin part mask layer as a mask to form the substrate 100 and a fin part 101 positioned on the substrate 100.
The fin mask layer is used to define the size and position of the fin 101.
The step of forming the fin mask layer includes: forming a mask material layer on the initial substrate; forming a pattern layer on the mask material layer; and etching the mask material layer by taking the pattern layer as a mask to expose the initial substrate so as to form the fin part mask layer.
The pattern layer is used for patterning the mask material layer so as to define the size and the position of the fin portion.
In this embodiment, the pattern layer is a patterned photoresist layer and may be formed through a coating process and a photolithography process. In other embodiments of the present invention, the patterned layer may also be a mask formed by a multi-patterning mask process, so as to reduce the feature size of the fin portion and the distance between adjacent fin portions, and improve the integration level of the formed semiconductor structure. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
It should be noted that, in this embodiment, after the substrate 100 and the fin 101 are formed, the fin mask layer on the top of the fin 101 is retained. The fin mask layer is made of silicon nitride and is used for defining the position of a stop layer of a planarization process in a subsequent process and playing a role in protecting the fin 101.
In this embodiment, after the substrate 100 and the fin 101 are formed, the forming method further includes: an isolation layer (not shown) is formed on the substrate 100 exposed by the fin 101, and the top of the isolation layer is lower than the top of the fin 101 and covers a part of the surface of the sidewall of the fin 101.
The isolation layer is used to achieve electrical isolation between adjacent fins 101 and between adjacent semiconductor structures.
In this embodiment, the isolation layer is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.
The step of forming the isolation layer includes: forming an isolation material layer on the substrate 100 which is not covered by the fin 101 by a chemical vapor deposition (for example: fluid chemical vapor deposition) method, and the like, wherein the isolation material layer covers the fin mask layer; removing the isolation material layer higher than the fin mask layer by chemical mechanical polishing and the like; and removing part of the thickness of the residual isolating material layer by back etching to form the isolating layer.
After the forming the isolation layer, the forming method further includes: and removing the fin part mask layer to expose the top surface of the fin part 101.
With continued reference to fig. 2, a gate structure 110 is formed on the fin 101, wherein the gate structure 110 crosses over the fin 101 and covers a portion of the top and a portion of the sidewall of the fin 101.
The gate structure 110 is used for shielding part of the fin portion 101 in the subsequent process of forming the source-drain doped region, so that the formed source-drain doped region is prevented from being in direct contact. In this embodiment, the gate structure 110 is a dummy gate structure, and therefore the gate structure 110 is also used to occupy a space for a subsequently formed gate structure. In other embodiments of the present invention, the gate structure may also be an actual gate structure of the formed semiconductor structure, and therefore, the gate structure 110 is also used for controlling the conduction and the cut-off of the channel in the formed semiconductor structure.
In the present embodiment, the gate structure 110 is a single-layer structure and includes a dummy gate (not shown) made of polysilicon material. In other embodiments of the present invention, the dummy gate may be made of other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In other embodiments of the present invention, the dummy gate structure may also be a stacked structure, and includes a dummy gate and a dummy oxide layer located on the dummy gate, where the dummy oxide layer may be made of silicon oxide and silicon oxynitride.
The step of forming the gate structure 110 includes: forming a gate material layer on the substrate 100; a gate mask layer (not labeled in the figure) is formed on the gate material layer, and the gate material layer is etched by taking the gate mask layer as a mask to form the gate structure 110.
It should be noted that after the gate structure 110 is formed, a sidewall spacer (not shown) is further formed on the sidewall of the gate structure 110. The side wall can be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and can be of a single-layer structure or a laminated structure. In this embodiment, the sidewall is of a single-layer structure, and the material of the sidewall is silicon nitride.
Referring to fig. 2 to 4, a first etching process 131 is performed to form an opening 130 in the fin 101 on both sides of the gate structure 110. Wherein fig. 4 is a schematic cross-sectional view taken along line AA in fig. 3.
The opening 130 is used to provide a process foundation for the formation of a subsequent stress layer. In addition, the first etching process 131 is used to remove a portion of the material of the fin 101 on two sides of the gate structure 110, so as to reduce the height of the fin 101 at the opening 130. The reduction of the height of the fin portion 101 can effectively reduce the injection energy in the subsequent electrostatic discharge injection step, is beneficial to reducing the damage of the electrostatic discharge injection to the fin portion 101, and is beneficial to improving the performance of the formed semiconductor structure.
In this embodiment, the formation of an N-type transistor is taken as an example, so the opening 130 is a "U" shaped opening. The step of performing the first etch process 131 includes: the first etching process 131 is performed by a dry method to remove a portion of the material of the fin 101 on both sides of the gate structure 110, so as to form the opening 130. In other embodiments of the present invention, when the semiconductor structure is a P-type transistor, the shape of the opening may be sigma-shaped.
Specifically, in the step of performing the first etching treatment 131, the process gas includes: CF (compact flash)4The flow rate is in the range of 10sccm to 80 sccm; h2The flow rate is in the range of 50sccm to 210 sccm; o is2In the range of 50sccm to 215 sccm; the process temperature is in the range of 60 ℃ to 80 ℃; the process time is in the range of 5s to 20 s.
In another embodiment of the present invention, in the step of performing the first etching process, the process gas includes: CH (CH)3F, the flow rate is in the range of 50sccm to 800 sccm; he, the flow rate is in the range of 80sccm to 500 sccm; the process temperature is in the range of 50 ℃ to 350 ℃; the process time is in the range of 8s to 100 s.
It should be noted that, in the step of performing the first etching treatment 131, the depth of the opening 130 is not too large or too small.
In the step of performing the first etching treatment 131, if the depth of the opening 130 is too small, the height of the remaining fin 101 is too large, which is not favorable for reducing the injection energy in the subsequent electrostatic discharge injection step and is not favorable for reducing the damage of the fin 101 caused by the electrostatic discharge injection; in the step of performing the first etching treatment 131, if the depth of the opening 130 is too large, the height of the remaining fin 101 is too small, which may cause too small a distance between the subsequently formed electrostatic discharge doped region and the source/drain doped region, and the existence of the electrostatic discharge doped region may affect the performance of the source/drain doped region, which may cause the degradation of the performance of the formed semiconductor structure. Therefore, in this embodiment, the step of performing the first etching process 131 includes: a first etching process 131 is performed to form openings 130 with a depth in a range of 15nm to 40nm in the fin 101 on both sides of the gate structure 110.
It should be noted that, as shown in fig. 2 and fig. 3, in order to suppress the short channel effect in the formed semiconductor structure, after forming the gate structure 110 on the fin 101, before forming the opening 130 in the fin 101 on both sides of the gate structure 110, the forming method further includes: and performing light doping drain implantation 121 on the fin part 101 at two sides of the gate structure 110, and forming a light doping region 120 in the fin part 101, wherein the light doping region 120 has second type ions.
The lightly doped region 120 is used to form a shallow junction in the semiconductor structure to suppress a short channel effect and suppress a channel leakage current effect.
In this embodiment, the semiconductor structure is an N-type transistor, so the second type of ions implanted by the lightly doped drain implant 121 are N-type ions, such as P-type ions. In other embodiments of the present invention, the semiconductor structure is a P-type transistor, so the second type of ions implanted into the lightly doped drain are P-type ions, such as B-ions.
Referring to fig. 5, an electrostatic discharge implantation 150 is performed on the fin 101 with the opening 130 formed therein, and an electrostatic discharge doped region 160 is formed in the fin 101, wherein the electrostatic discharge doped region 160 has a first type of ions therein.
The step of electrostatic discharge implantation 150 is used to form an electrostatic discharge doped region 160 within the fin 101. The conductivity type of the doped ions in the electrostatic discharge doped region 160 is different from the conductivity type of the formed semiconductor structure channel when the channel is conducted, that is, the conductivity type of the doped ions in the electrostatic discharge doped region 160 is different from the conductivity type of the subsequently formed source/drain doped region. Therefore, a PN junction can be formed between the electrostatic discharge doped region 160 and the subsequently formed source-drain doped region, so as to achieve the purpose of adjusting the junction breakdown voltage and the trigger voltage of the electrostatic discharge device.
Since the opening 130 is formed in the fin 101 at two sides of the gate structure 110, the height of the fin 101 is lower in the step of performing the electrostatic discharge implantation 150. The reduction of the height of the fin portion 101 can effectively reduce the implantation energy of the electrostatic discharge implantation 150, and is beneficial to reducing the damage to the fin portion 101 in the process of the electrostatic discharge implantation 150.
Specifically, in the step of performing the electrostatic discharge implantation 150 on the fin 101 formed with the opening 130, when the semiconductor structure is an NMOS device, the process parameters are as follows: the implanted ions are B, the implantation energy is in the range of 3KeV to 15KeV, and the implantation dose is 1.0E12atom/cm2To 2.0E15atom/cm2Within the range; when the semiconductor structure is a PMOS device, the process parameters are as follows: implanting ions P with an implantation energy of 5KeV to 30KeV and an implantation dose of 1.0E12atom/cm2To 2.0E15atom/cm2Within the range.
It should be noted that, in the present embodiment, the fin 101 has a lightly doped region 120 therein for forming a shallow junction, and therefore, the step of performing the electrostatic discharge implantation 150 on the fin 101 with the opening 130 includes: performing an electrostatic discharge implantation 150 on the fin 101 with the opening 130, and forming the electrostatic discharge doping region 160 in the fin 101 under the lightly doped region 120, that is, the electrostatic discharge doping region 160 is located under the lightly doped region 120.
Referring to fig. 6 to 10, a stress layer 181 is formed in the opening 130 to form a source-drain doped region located on the electrostatic discharge doped region 160, where the source-drain doped region has the second type ions therein. Fig. 10 is a schematic cross-sectional view along line BB in fig. 9.
The stress layer 181 is used for forming a source-drain doped region of the semiconductor structure.
The step of forming the source/drain doped region on the esd doped region 160 includes: filling a semiconductor material into the opening 130 (shown in fig. 7), and forming a stress layer 181 (shown in fig. 8) in the opening 130; performing source-drain implantation 182 (as shown in fig. 8) on the stress layer 181 to form a source-drain doped region located on the esd doped region 180.
In this embodiment, the semiconductor structure is an N-type transistor, so the semiconductor material is SiC, that is, the material of the stress layer 181 is SiC. The SiC stress layer 181 can apply tensile stress to the channel of the formed semiconductor structure, thereby facilitating the increase of the mobility of carriers in the channel and improving the performance of the formed semiconductor structure.
In other embodiments of the present invention, when the semiconductor structure is a P-type transistor, the semiconductor material is SiGe, that is, the stress layer is SiGe. The SiGe stress layer can apply compressive stress to the channel of the formed semiconductor structure, so that the mobility of carriers in the channel is improved, and the performance of the formed semiconductor structure is improved.
Specifically, the step of filling the opening 130 with the semiconductor material includes: the opening 130 is filled with a semiconductor material by means of epitaxial growth.
Since the stress layer 181 is formed in the opening 130 by epitaxial growth, the quality of the stress layer 181 is related to the lattice quality of the bottom and sidewall surfaces of the opening 130. The esd implant 150 (shown in fig. 5) may cause lattice damage in the fin 101, thereby affecting the quality of the lattice at the bottom and sidewall surfaces of the opening 130, and affecting the quality of the stress layer 181 formed. As shown in fig. 6, after the electrostatic discharge implantation 150 is performed on the fin 101 with the opening 130, and before the stress layer 181 is formed in the opening 130, the first annealing treatment 170 is performed on the fin 101 with the lightly doped region 120 and the electrostatic discharge doped region 160.
The first annealing treatment 170 is used to repair lattice damage in the fin 101, so as to improve lattice quality at the bottom of the opening 139 and on the surface of the sidewall, and provide a better growth surface for forming the stress layer 181; furthermore, after the lightly doped drain implant 121 (shown in fig. 2) and the electrostatic discharge implant 150 (shown in fig. 5), the first annealing process 170 is performed, and the first annealing process 170 is further used for activating the dopant ions in the lightly doped region 120 and the electrostatic discharge doped region 160.
The step of performing the first annealing 170 after the esd implantation 150 can simultaneously activate the lightly doped region 120 and repair the fin 101 in the step of performing the first annealing 170, thereby reducing the usage of the heating process, reducing the thermal budget of the semiconductor structure, and improving the performance of the semiconductor structure.
Specifically, the step of performing the first annealing 170 on the fin 101 having the lightly doped region 120 and the esd doped region 160 includes: the fin 101 formed with the lightly doped region 120 and the esd doped region 160 is subjected to a first annealing process 170 by spike annealing.
It should be noted that, in the step of performing the first annealing treatment 170, the annealing temperature is not too high or too low, and the annealing time is not too long or too short.
In the step of performing the first annealing treatment 170, if the annealing temperature is too low and the annealing time is too short, activation of the dopant ions in the lightly doped region 120 and the electrostatic discharge doped region 160 may be affected, and a repairing effect of the first annealing treatment 170 on lattice damage of the fin 101 may also be affected, so that it is difficult to effectively improve lattice quality at the bottom of the opening 130 and on the sidewall surface, and thus the performance of the formed stress layer 181 may be degraded; if the annealing temperature is too high and the annealing time is too long, the diffusion degree of the dopant ions in the lightly doped region 120 and the electrostatic discharge doped region 160 is too severe, since the lightly doped region 120 is close to the channel region of the formed semiconductor structure, the diffusion degree of the dopant ions in the lightly doped region 120 is too severe, which may cause the deterioration of the short channel effect, and affect the performance of the formed semiconductor structure, and since the type of the dopant ions in the electrostatic discharge doped region 160 is opposite to the type of the dopant ions in the subsequently formed source/drain doped region, the diffusion degree of the dopant ions in the electrostatic discharge doped region 160 is too severe, which may cause the counter ions in the electrostatic discharge doped region 160 to affect the performance of the formed source/drain doped region, thereby causing the performance degradation of the formed semiconductor structure.
Therefore, in the present embodiment, the annealing temperature in the first annealing process 170 is in the range of 950 ℃ to 1100 ℃ for the fin 101 formed with the lightly doped region 120 and the esd doped region 160.
In addition, after the first annealing 170 is performed on the fin 101 with the lightly doped region 120 and the electrostatic discharge doped region 160, and before the stress layer 181 is formed in the opening 130, in this embodiment, as shown in fig. 7, the forming method further includes: a second etching process 132 is performed to remove a portion of the material on the sidewalls and bottom of the opening 130.
As device dimensions decrease, the size of fin 101 also decreases. The reduction in the size of the fin 101 may affect the repair effect of the first annealing process 170 on the lattice damage of the fin 101, and therefore, the second etching process 132 is used to remove a portion of the material on the sidewall and the bottom of the opening 130 to remove the material with the lattice damage, thereby providing a high-quality growth surface for the formation of the stress layer 181.
Specifically, in order to reduce the damage to the fin 101 caused by the second etching treatment 132, the step of performing the second etching 132 on the sidewall and the bottom of the opening 130 includes: the second etching process 132 is performed by a dry method.
It should be noted that, in the step of performing the second etching 132, the thickness of the material on the sidewall and the bottom of the opening 130 is not too large or too small.
In the step of performing the second etching 132, if the thicknesses of the materials on the sidewall and the bottom of the opening 130 are too small, the effect of removing the lattice damage by the second etching 132 is affected, and more lattice damage remains on the surface of the bottom and the sidewall of the opening 130, so that a good growth surface cannot be provided for forming the stress layer 181, and the quality of the stress layer 181 is affected; if the thickness of the material on the sidewall and the bottom of the opening 130 is too large, the material is wasted, the process difficulty is increased, and the distance between the source and drain doped regions formed subsequently and the electrostatic discharge doped region 160 is reduced, which affects the performance of the formed source and drain doped region, thereby degrading the performance of the formed semiconductor structure. Specifically, in this embodiment, the step of performing the second etching treatment 132 includes: a second etch process 132 is performed to remove 10nm to 20nm of material from the sidewalls and bottom of the opening 130.
Referring to fig. 8, after forming a stress layer 181, performing source-drain implantation 182 on the stress layer 181 to form a source-drain doped region.
The source-drain injection 182 is used for injecting doping ions into the stress layer 181 to form a source-drain doped region; the source and drain doped regions are used for forming a source region or a drain region of the semiconductor structure.
Specifically, in this embodiment, the formed semiconductor structure is an N-type transistor, and therefore in the step of performing source/drain implantation 182 on the stress layer 181, the implanted ions are P, the implantation energy is in the range of 3KeV to 10KeV, and the implantation dose is 1.0E15atom/cm2To 5.0E15atom/cm2Within the range.
In other embodiments of the present invention, when the formed semiconductor structure is a P-type transistor, in the step of performing source/drain implantation on the cause treatment, the implanted ions are B, the implantation energy is in the range of 1KeV to 5KeV, and the implantation dose is 1.0E15atom/cm2To 5.0E15atom/cm2Within the range.
As shown in fig. 9, after performing source-drain implantation 182 on the stress layer 181, the forming method further includes: and carrying out second annealing treatment 183 to activate the doped ions in the source and drain doped regions.
The second annealing treatment 183 is used to relax the dopant ions in the source/drain doped region to the lattice position, so as to activate the dopant ions in the source/drain doped region.
Because the electrostatic discharge injection 150 (as shown in fig. 5) is performed before the formation of the stress layer 181 and the source-drain doped region, the electrostatic discharge injection 150 does not cause lattice damage to the stress layer 181 and the source-drain doped region, so that the quality of the formed stress layer 181 can be effectively improved, the stress release of the stress layer 181 during the second annealing treatment 183 is reduced, the performance of the formed stress layer 181 is improved, and the performance of the formed semiconductor structure is improved.
Specifically, the step of performing the second annealing 183 includes: the second annealing treatment 183 is performed by means of spike annealing.
In the step of performing the second annealing treatment 183, the annealing temperature is not preferably too high or too low, and the annealing time is not preferably too long or too short.
In the step of performing the second annealing treatment 183, if the annealing temperature is too low and the annealing time is too short, activation of doped ions in the source/drain doped region is affected, so that the performance of the formed source/drain doped region is affected, and the performance of the formed semiconductor structure is degraded; if the annealing temperature is too high, and if the annealing time is too long, the process risk is increased, unnecessary damage may be caused, and the yield of forming the semiconductor structure may be affected. Therefore, in the present embodiment, in the step of performing the second annealing treatment 183 by spike annealing, the annealing temperature is in the range of 1000 ℃ to 1100 ℃.
In addition, in another embodiment of the present invention, the step of performing the second annealing includes: and carrying out second annealing treatment in a laser annealing mode. Specifically, in the step of performing the second annealing treatment by means of laser annealing, the annealing temperature is in the range of 1200 ℃ to 1300 ℃.
Correspondingly, the invention also provides a semiconductor structure.
Referring to fig. 5, a cross-sectional structure diagram of an embodiment of a semiconductor structure of the invention is shown.
The semiconductor structure includes: a substrate 100, wherein the substrate 100 is provided with a fin part 101; a gate structure 110 located on the fin 101, wherein the gate structure 110 crosses over the fin 101 and covers part of the top and part of the sidewall of the fin 101; openings 130 in the fin 101 at two sides of the gate structure 110; an ESD doped region 160 in the fin 101 below the opening 130, the ESD doped region 160 having a first type of ions therein.
It should be noted that the semiconductor structure in this embodiment has two non-adjacent N-type transistors. In other embodiments of the present invention, the semiconductor structure may also be used to form other semiconductor structures such as a P-type transistor, or may also be used to form an adjacent semiconductor structure, which should not be construed as limiting the present invention.
The substrate 100 is used to provide a process platform.
In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for process requirements or easy to integrate.
The fin 101 is used to provide a channel of the finfet.
In this embodiment, the material of the fin 101 is the same as that of the substrate 100, and is also monocrystalline silicon. In other embodiments of the present invention, the material of the fin may be different from the material of the substrate, and may be selected from materials suitable for forming a fin, such as germanium, silicon carbon, or gallium arsenide.
In this embodiment, the semiconductor structure further includes: an isolation layer (not shown) on the substrate 100 is exposed by the fin 101, and the top of the isolation layer is lower than the top of the fin 101 and covers a portion of the surface of the sidewall of the fin 101.
The isolation layer is used to achieve electrical isolation between adjacent fins 101 and between adjacent semiconductor structures. In this embodiment, the isolation layer is made of silicon oxide. In other embodiments of the present invention, the material of the isolation layer may also be silicon nitride or silicon oxynitride.
The gate structure 110 is used for shielding part of the fin portion to prevent the source-drain doped regions from being in direct contact.
In this embodiment, the gate structure 110 is a dummy gate structure, and therefore the gate structure 110 is also used to occupy a space for the gate structure of the semiconductor structure. In other embodiments of the present invention, the gate structure may also be an actual gate structure of the formed semiconductor structure, and therefore, the gate structure 110 is also used for controlling the conduction and the cut-off of the channel in the formed semiconductor structure.
In the present embodiment, the gate structure 110 is a single-layer structure and includes a dummy gate (not shown) made of polysilicon material. In other embodiments of the present invention, the dummy gate may be made of other materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In other embodiments of the present invention, the dummy gate structure may also be a stacked structure, and includes a dummy gate and a dummy oxide layer located on the dummy gate, where the dummy oxide layer may be made of silicon oxide and silicon oxynitride.
In addition, the semiconductor structure further includes: and a sidewall spacer (not shown) on the sidewall of the gate structure 110. The side wall can be made of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and can be of a single-layer structure or a laminated structure. In this embodiment, the sidewall is of a single-layer structure, and the material of the sidewall is silicon nitride.
The opening 130 is used for filling a semiconductor material to form a source-drain doped region of the semiconductor structure.
In addition, the height of the fin 101 at the opening 130 can be reduced due to the existence of the opening 130. The reduction of the height of the fin portion 101 can effectively reduce the damage to the fin portion 101 in the formation process of the electrostatic discharge doping region 160, and is beneficial to improving the performance of the formed semiconductor structure.
In this embodiment, the semiconductor structure is used to form an N-type transistor, so the opening 130 is a "U" shaped opening. In other embodiments of the present invention, the semiconductor structure may be used to form a P-type transistor, and the shape of the opening may be a sigma shape.
It should be noted that the depth of the opening 130 should not be too large or too small.
If the depth of the opening 130 is too small, the height of the remaining fin 101 is too large, which is not favorable for reducing the damage to the fin 101 in the process of forming the electrostatic discharge doping region 160; if the depth of the opening 130 is too large, the height of the remaining fin 101 is too small, which may result in too shallow depth of the esd doped region 160, which may affect the performance of the source/drain doped region in the semiconductor structure, and degrade the performance of the semiconductor structure. Therefore, in the present embodiment, the depth of the opening 130 is in the range of 15nm to 40 nm.
The electrostatic discharge doped region 160 is used for forming a PN junction with the source-drain doped region of the semiconductor structure, so as to achieve the purpose of adjusting junction breakdown voltage and adjusting trigger voltage of an electrostatic discharge device.
The esd doped region 160 is located in the fin below the opening 130, so that the height of the fin 101 is lower during the formation of the esd doped region 160. The reduction of the height of the fin portion 101 can effectively reduce the damage to the fin portion 101 caused by the formation process of the electrostatic discharge doping region 160.
And because the electrostatic discharge doping region 160 is formed before the formation of the stress layer and the source-drain doping region of the semiconductor structure, the formation process of the electrostatic discharge doping region 160 does not cause lattice damage to the stress layer and the source-drain doping region, so that the quality of the formed stress layer can be effectively improved, the stress released by the stress layer in the formation process of the source-drain doping region is reduced, the performance of the stress layer is favorably improved, and the performance of the semiconductor structure is favorably improved.
Specifically, when the semiconductor structure is an NMOS device, the doped ions in the electrostatic discharge doped region are B, and the concentration of the doped ions is 1.0E18atom/cm3To 5.0E19atom/cm3Within the range; when the semiconductor structure is a PMOS device, the doped ions in the electrostatic discharge doped region are P, and the concentration of the doped ions is 1.0E18atom/cm3To 5.0E19atom/cm3Within the range.
It should be noted that, in order to suppress the short channel effect in the semiconductor structure, the semiconductor structure further includes: and the lightly doped region 120 is located in the fin 101 at two sides of the gate structure 110, the lightly doped region 120 has the second type of ions therein, and the lightly doped region 120 is located on the electrostatic discharge doping region 160.
The lightly doped region 120 is used to form a shallow junction in the semiconductor structure to suppress a short channel effect and suppress a channel leakage current effect.
In this embodiment, the formed semiconductor structure is used to form an N-type transistor, so the lightly doped region 120 has N-type doped ions therein; in other embodiments of the present invention, the semiconductor structure is used to form a P-type transistor, and the lightly doped region 120 has P-type doped ions therein.
Since the lightly doped region 120 is used to form a shallow junction, the lightly doped region 120 is located near the channel region of the semiconductor structure, and therefore the lightly doped region 120 is located on the esd doped region 160.
It should be noted that the semiconductor structure is used to form an N-type transistor, so that the opening 130 in the semiconductor structure is filled with a semiconductor material to form a source/drain doped region of the N-type transistor. In the detailed technical solution, reference is made to the aforementioned embodiments of the semiconductor structure forming method of the present invention, and the detailed description of the invention is omitted here.
In summary, in the technical solution of the present invention, after the opening is formed in the fin portion at the two sides of the gate structure; performing electrostatic discharge injection on the fin part with the opening, and forming an electrostatic discharge doping region with first type ions in the fin part; and after the electrostatic discharge doped region is formed, forming a stress layer and a source drain doped region in the opening. Because the electrostatic discharge injection is carried out before the formation of the stress layer and the source-drain doped region, the electrostatic discharge injection does not cause lattice damage to the stress layer and the source-drain doped region, the quality of the formed stress layer can be effectively improved, the stress released by the stress layer in the formation process of the source-drain doped region is reduced, the performance of the formed stress layer is favorably improved, and the performance of the formed semiconductor structure is favorably improved. In addition, in the alternative of the present invention, after the gate structure is formed on the fin portion, before the opening is formed in the fin portion on both sides of the gate structure, the lightly doped drain implantation is performed on the fin portion on both sides of the gate structure, and a lightly doped region is formed in the fin portion; and after performing electrostatic discharge injection on the fin part with the opening and before forming a stress layer in the opening, performing annealing treatment on the fin part with the lightly doped region and the electrostatic discharge doped region. The annealing treatment is used for activating the doping ions in the lightly doped region, repairing the damage to the fin part after the electrostatic discharge injection and the light doping injection, and providing a good growth surface for the formation of the subsequent stress layer; the method can effectively improve the quality of the formed stress layer, can reduce the times of heating process in the semiconductor forming method, and is beneficial to improving the performance of the formed semiconductor structure. In addition, in an alternative aspect of the present invention, the forming method further includes: and after annealing treatment is carried out on the fin part formed with the lightly doped region and the electrostatic discharge doped region, second etching treatment is carried out before a stress layer is formed in the opening, and partial materials on the side wall and the bottom of the opening are removed. The second etching is used for removing materials which are not repaired on the side wall and the bottom of the opening in the annealing treatment, so that the quality of the bottom and the side wall of the opening in the process of forming the stress layer is improved, a good growth surface is improved for the formation of the stress layer, the quality of the formed stress layer is improved, and the performance of the semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin part;
forming a grid electrode structure on the fin part, wherein the grid electrode structure stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part;
performing light doping and drain injection on fin parts on two sides of the grid structure, and forming a light doping area in the fin parts, wherein the light doping area is provided with second type ions;
after the lightly doped drain is injected, performing first etching treatment, and forming openings in the fin parts on two sides of the grid structure, wherein the depth of each opening is in the range of 15nm to 40 nm;
performing electrostatic discharge injection on the fin part with the opening, wherein the injection energy is in the range of 3KeV to 15KeV, and an electrostatic discharge doping area is formed in the fin part under the lightly doped area and is internally provided with first type ions;
forming a stress layer in the opening to form a source drain doped region on the electrostatic discharge doped region, wherein the source drain doped region is internally provided with second type ions and is separated from the electrostatic discharge doped region;
after performing electrostatic discharge injection on the fin portion with the opening, and before forming a stress layer in the opening, the forming method further includes: carrying out first annealing treatment on the fin part formed with the electrostatic discharge doping area and the light doping area so as to activate doping ions in the light doping area and the electrostatic discharge doping area; and after the first annealing treatment, performing second etching treatment to remove the material with the thickness of 10nm to 20nm on the side wall and the bottom of the opening.
2. The method of forming as claimed in claim 1, wherein the step of performing a first etching process comprises: the first etching treatment is performed by a dry method.
3. The method of claim 1, wherein the forming the fin with the opening is performedIn the step of electrostatic discharge injection, when the semiconductor structure is an NMOS device, the process parameters are as follows: the implanted ions are B, and the implantation dose is 1.0E12atom/cm2To 2.0E15atom/cm2Within the range;
when the semiconductor structure is a PMOS device, the process parameters are as follows: the implanted ions are P, and the implantation dose is 1.0E12atom/cm2To 2.0E15atom/cm2Within the range.
4. The method of claim 1, wherein the step of performing the first annealing process on the fin having the lightly doped region and the ESD doped region comprises: and carrying out first annealing treatment on the fin part formed with the lightly doped region and the electrostatic discharge doped region in a spike annealing mode.
5. The method of claim 1 or 4, wherein the first annealing is performed at a temperature in a range of 950 ℃ to 1100 ℃ for the fin portion having the lightly doped region and the ESD doped region.
6. The method of forming of claim 1, wherein the step of second etching the opening sidewalls and bottom comprises: and carrying out the second etching treatment in a dry method.
7. The method of claim 1, wherein forming source and drain doped regions over the esd doped region comprises:
filling a semiconductor material into the opening, and forming a stress layer in the opening;
and performing source-drain injection on the stress layer to form a source-drain doped region on the electrostatic discharge doped region.
8. The method of forming of claim 7, wherein filling the opening with a semiconductor material comprises: and filling the semiconductor material into the opening in an epitaxial growth mode.
9. The method of forming of claim 7, wherein during the step of source drain implant into the stress layer,
when the semiconductor structure is a PMOS device, the process parameters are as follows: the implanted ions are B, the implantation energy is in the range of 1KeV to 5KeV, and the implantation dose is 1.0E15atom/cm2To 5.0E15atom/cm2Within the range;
when the semiconductor structure is an NMOS device, the implanted ions are P, the implantation energy is in the range of 3KeV to 10KeV, and the implantation dosage is 1.0E15atom/cm2To 5.0E15atom/cm2Within the range.
10. The method of forming of claim 7, wherein after performing source drain implant on the stress layer, the method further comprises: and carrying out second annealing treatment to activate the doped ions in the source-drain doped region.
11. The method of forming as claimed in claim 10, wherein the step of performing the second annealing process includes: the second annealing treatment is performed by means of spike annealing or laser annealing.
12. The forming method of claim 11, wherein in the step of performing the second annealing treatment by spike annealing, the annealing temperature is in a range of 1000 ℃ to 1100 ℃;
in the step of performing the second annealing treatment by means of laser annealing, the annealing temperature is in the range of 1200 ℃ to 1300 ℃.
13. A semiconductor structure, wherein the forming method is formed by the forming method of any one of claims 1 to 12, comprising:
a substrate having a fin portion thereon;
the grid electrode structure is positioned on the fin part and stretches across the fin part and covers the partial top of the fin part and the surface of partial side wall of the fin part;
the openings are positioned in the fin parts on two sides of the grid electrode structure, and the depth of the openings is within the range of 15nm to 40 nm;
the electrostatic discharge doping region is positioned in the fin part below the opening and is internally provided with first type ions;
and the lightly doped region is positioned in the fin parts at two sides of the grid structure, the lightly doped region is internally provided with second type ions, and the lightly doped region is positioned on the electrostatic discharge doping region.
14. The semiconductor structure of claim 13, wherein when the semiconductor structure is an NMOS device, the doped ion in the esd doped region is B, and the concentration of the doped ion is 1.0E18atom/cm3To 5.0E19atom/cm3Within the range;
when the semiconductor structure is a PMOS device, the doped ions in the electrostatic discharge doped region are P, and the concentration of the doped ions is 1.0E18atom/cm3To 5.0E19atom/cm3Within the range.
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| US20080132019A1 (en) * | 2006-12-05 | 2008-06-05 | Keh-Chiang Ku | Short channel effect engineering in MOS device using epitaxially carbon-doped silicon |
| CN104078360A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Method for producing MOS transistor |
| CN105529266A (en) * | 2014-10-21 | 2016-04-27 | 上海华力微电子有限公司 | Improvement method for dislocation defects of embedded silicon-germanium epitaxy |
| CN106206315A (en) * | 2016-07-18 | 2016-12-07 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof and include the electronic equipment of this device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20080132019A1 (en) * | 2006-12-05 | 2008-06-05 | Keh-Chiang Ku | Short channel effect engineering in MOS device using epitaxially carbon-doped silicon |
| CN104078360A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | Method for producing MOS transistor |
| CN105529266A (en) * | 2014-10-21 | 2016-04-27 | 上海华力微电子有限公司 | Improvement method for dislocation defects of embedded silicon-germanium epitaxy |
| CN106206315A (en) * | 2016-07-18 | 2016-12-07 | 中国科学院微电子研究所 | Semiconductor device and manufacture method thereof and include the electronic equipment of this device |
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