CN106206315A - Semiconductor device and manufacture method thereof and include the electronic equipment of this device - Google Patents
Semiconductor device and manufacture method thereof and include the electronic equipment of this device Download PDFInfo
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- CN106206315A CN106206315A CN201610565083.8A CN201610565083A CN106206315A CN 106206315 A CN106206315 A CN 106206315A CN 201610565083 A CN201610565083 A CN 201610565083A CN 106206315 A CN106206315 A CN 106206315A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000009826 distribution Methods 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
- 230000002265 prevention Effects 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000007423 decrease Effects 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 16
- 239000002019 doping agent Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000001629 suppression Effects 0.000 description 5
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- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
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- 230000001276 controlling effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
Disclose a kind of semiconductor device and manufacture method thereof and include the electronic equipment of this device.According to embodiment, semiconductor device may include that substrate；The fin extended in a first direction formed on substrate, fin includes the first side and the second side being positioned at its opposite two ends in a first direction；The source region layer formed on first side and the second side of fin respectively and drain region layer；The grid stacking extended along the second direction intersected with first direction formed on substrate, grid stacking intersects with fin thus limits channel region in fin；And the break-through formed in the substrate bottom channel region stops (PTS) layer, wherein, below fin, PTS layer has doping concentration distribution low between both sides senior middle school in the first direction.
Description
Technical field
It relates to semiconductor applications, stop (PTS) layer can suppress in PTS in particular it relates to have break-through simultaneously
Adulterant enters the semiconductor device in channel region and manufacture method thereof and includes the electronic equipment of this semiconductor device.
Background technology
Along with the size of planar-type semiconductor device is more and more less, short-channel effect is the most obvious.It is proposed to this end that it is three-dimensional
Type semiconductor device such as fin formula field effect transistor (FinFET).It is said that in general, FinFET is included in and is vertically formed on substrate
Fin and the grid intersected with fin.
Particularly, (that is, the FinFET in body Semiconductor substrate it is formed at, more specifically, fin is partly led by body at body FinFET
Body substrate is formed and therefore connects with body Semiconductor substrate) in, there may be between source-drain area via fin lower substrate portion
Leakage, this is also referred to as break-through (punch-through).Generally, it is possible to use ion implanting and/or thermal diffusion come (at fin
Lower section) form break-through prevention (PTS) layer.Preferably PTS layer should at channel region non-impurity-doped below fin channel region in other words
Lower section keeps completely depleted.But, use ion implanting or the thermal diffusion method of routine, it is difficult to stop the adulterant in PTS layer
Enter in channel region.
Summary of the invention
In view of this, the purpose of the disclosure is that providing one to have break-through stops (PTS) layer energy simultaneously at least in part
Adulterant in suppression PTS enters semiconductor device and the manufacture method thereof in channel region and includes this semiconductor device
Electronic equipment.
According to an aspect of this disclosure, it is provided that a kind of semiconductor device, including: substrate；The edge formed on substrate
The fin that first direction extends, fin includes the first side and the second side being positioned at its opposite two ends in a first direction；Point
The source region layer not formed on first side and the second side of fin and drain region layer；Edge and the first direction phase formed on substrate
The grid stacking that the second direction handed over extends, grid stacking intersects with fin thus limits channel region in fin；And bottom channel region
The break-through that formed in the substrate stops (PTS) layer, and wherein, below fin, PTS layer has low between the senior middle school of both sides in the first direction
Doping concentration distribution.
According to another aspect of the present disclosure, it is provided that a kind of method manufacturing semiconductor device, including: formed on substrate
The ridge extended in a first direction；The second direction that formation edge and first direction intersect on substrate extends thus and ridge
The sacrificial gate stacking intersected；Ridge is carried out selective etch, makes the part serving as the fin of semiconductor device in ridge real
Stay in matter below sacrificial gate stacks；Carry out ion implanting, to form break-through prevention (PTS) layer below fin in the substrate；?
Source region layer and drain region layer is formed on the side of ridge；And replace sacrificial gate stacking to form real grid stacking.
According to another aspect of the present disclosure, it is provided that a kind of method manufacturing semiconductor device, including: formed on substrate
The ridge extended in a first direction；The second direction that formation edge and first direction intersect on substrate extends thus and ridge
The sacrificial gate stacking intersected；Carry out ion implanting, to form break-through prevention (PTS) layer at certain position in the substrate；To carinate
Thing carries out selective etch, makes the part serving as the fin of semiconductor device in ridge substantially stay below sacrificial gate stacks；
The side of ridge is formed source region layer and drain region layer；And replace sacrificial gate stacking to form real grid stacking.
According to another aspect of the present disclosure, it is provided that a kind of electronic equipment, including the collection formed by above-mentioned semiconductor device
Become circuit.
According to embodiment of the disclosure, after forming sacrificial gate stacking, carry out the ion implanting for PTS again.Due to sacrificial
The existence of domestic animal grid stacking, is possible to prevent ion to be directly entered in fin.Further, it is also possible to carry out source/drain region etching, to suppress ion
Enter channel region from source/drain region.This source/drain region etching can be before or after for the ion implanting of PTS.Then,
Can be with channel region PTS formed below layer, suppression adulterant the most significantly enters in channel region.
Accompanying drawing explanation
By description to disclosure embodiment referring to the drawings, above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1～11 (c) show the flow chart manufacturing semiconductor device according to disclosure embodiment；
Figure 12～14 shows the flow chart of the part stage manufacturing semiconductor device according to another embodiment of the disclosure；
Figure 15 (a) and 15 (b) show according to disclosure embodiment under different Implantation Energies in fin short transverse
Doping concentration distribution, Figure 15 (c) shows comparative examples.
Running through accompanying drawing, identical reference represents identical parts.
Detailed description of the invention
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are the most exemplary
, and it is not intended to limit the scope of the present disclosure.Additionally, in the following description, eliminate the description to known features and technology, with
Avoid unnecessarily obscuring the concept of the disclosure.
Various structural representations according to disclosure embodiment shown in the drawings.These figures are not drawn to scale
, wherein in order to understand the purpose of expression, it is exaggerated some details, and some details may be eliminated.Shown in figure
Various regions, the shape of layer and the relative size between them, position relationship are only exemplary, are likely to be due to system in reality
Make tolerance or technical limitations and deviation, and those skilled in the art have difference according to actually required can additionally design
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as positioned at another layer/element " on " time, this layer/element can
To be located immediately on this another layer/element, or intermediate layer/element between them, can be there is.If it addition, one towards
In one layer/element be positioned at another layer/element " on ", then when turn towards time, this layer/element may be located at this another layer/unit
Part D score.
When manufacturing fin formula field effect transistor (FinFET), the most first formed on substrate in a certain direction (hereinafter referred to as
Make " first direction ") fin that extends.For example, it is possible to by substrate is performed etching with formed extend in a first direction carinate
Thing, and formation sealing coat is to expose a part for ridge on substrate, this part is usually defined as fin.Based on fin,
(on sealing coat) grid extended thus intersect with fin can be formed along the second direction intersecting (such as, vertical) with first direction
Stacking, thus in fin, limit channel region.Fin is positioned at the opposed end of grid stacking both sides can each act as source region and drain region.Grid
The formation of stacking can utilize replacement gate process.
In order to prevent via the leakage below fin i.e. break-through between source region and drain region, can be come under fin by ion implanting
Form break-through bottom side's channel region in other words and stop (PTS) layer.According to routine techniques, generally formed after ridge or
Ion implanting is carried out after forming sealing coat and before forming grid stacking.Unlike this, according to embodiment of the disclosure, first shape
Become the sacrificial gate stacking intersected with fin, then carry out PTS ion implanting.Due to the existence of sacrificial gate stacking, doping can be avoided
Agent is directly entered in channel region.Then, adulterant by the opposite sides on first direction (that is, corresponding to source region and drain region
Position) and enter into below channel region, the PTS layer being consequently formed can have doping low between both sides senior middle school in the first direction
Concentration is distributed.Below source region and drain region, owing to can directly accept injection, therefore PTS layer can have real in the first direction
Uniform doping concentration distribution in matter.
Additionally, in order to prevent adulterant from entering channel region from source region and/or drain region, it is also possible to carry out source/drain region etching,
That is, remove ridge or fin is positioned at grid and stacks the part (corresponding to source region and the position in drain region) of both sides.This etching can be
Carry out before ion implanting or carry out after ion implantation.When carrying out before source/drain region is etched in ion implanting, due to
Fin is only located at below grid stacking and therefore adulterant not directly enters wherein, thus only below fin in other words at the bottom of channel region
Portion, the adulterant of injection can enter wherein from both sides as mentioned above thus form PTS layer.Therefore, in channel region the most not
There is any doping having a mind to.When source/drain region etching is carried out after ion implantation, although element dopants may be had to be dissipated
Inject in channel region, but be removed, hence into raceway groove owing to ridge or fin subsequently are positioned at the part of grid stacking both sides
The quantity of the adulterant in district is relatively fewer.
Afterwards, on the opposite flank of fin, such as source region layer and drain region layer can be formed by epitaxial growth.This source
Region layer can include the semi-conducting material different from fin with drain region layer, such that it is able to apply stress to fin channel region in other words, with
Strengthen device performance.
The disclosure can present in a variety of manners, some of them example explained below.
Fig. 1～11 (c) show the flow chart manufacturing semiconductor device according to disclosure embodiment.
As shown in Figure 1, it is provided that substrate 1001.This substrate 1001 can be various forms of substrate, includes but not limited to body
Semiconductive material substrate such as body Si substrate, semiconductor-on-insulator (SOI) substrate, compound semiconductor substrate such as SiGe substrate
Deng.In the following description, for convenience of description, it is described as a example by body Si substrate.
In substrate 1001, well region 1001w can be formed.Specifically, N-shaped well region can be formed, for the most wherein
Form p-type device；Or, p-type well region can be formed, for forming n-type device the most wherein.Such as, N-shaped well region can lead to
Crossing implant n-type impurity such as P or As in substrate 1001 to be formed, p-type well region can be by implanted with p-type impurity in substrate 1001
As B or In is formed.If it is required, can also anneal after injection it.Those skilled in the art are it is conceivable that multiple side
Formula forms N-shaped trap, p-type trap, does not repeats them here.
Subsequently, substrate 1001 can be patterned, to form ridge.Such as, this can be carried out as follows.Specifically,
Can form mask layer 1003 such as photoresist on substrate 1001, this mask layer 1003 is patterned to and the ridge that will be formed
Corresponding shape, such as strip (being perpendicular to paper direction extend).Then, as in figure 2 it is shown, can be with mask layer 1003 for covering
Mould, selective etch such as reactive ion etching (RIE) substrate 1001, thus form ridge F1.Ridge F1 obtained
Width (dimension in horizontal direction in figure) can be between about 2～25nm.As described below, the top of this ridge F1 is (concrete
Ground, is isolated the part that layer exposes) will act as the fin of device.Well region 1001w can be entered here, etch, thus ridge F1
The well region of a part can be comprised.Afterwards, mask layer 1003 can be removed.
Then, as it is shown on figure 3, sealing coat 1005 can be formed in the structure shown in Fig. 2.Such as, this can pass through
Deposit dielectric material such as oxide (such as, silicon oxide) be etched back it in structure shown in Fig. 2, obtains sealing coat
1005.Before eat-back, the dielectric substance of deposit can be carried out planarization and process such as chemically mechanical polishing (CMP) or spatter
Penetrate.In etch back process, control etch-back depths so that the end face of the sealing coat 1005 after eat-back is relative to the end face of ridge F1
Recessed.So, ridge F1 may then act as the fin F of device relative to the prominent part of sealing coat 1008.
It is to be herein pointed out serving as the part below the part of fin F and fin F in ridge F1 is drawing functionally
Point (specifically, fin is at its sidewall and forms raceway groove the most on its top face, and part below fin be formed without ditch
Road), they form as one physically.In figure 3, show in phantom this division, but this is only used to make reading
Person better understood when the technology of the disclosure when reading the disclosure, and is not intended to limit the disclosure.
PTS layer owing to will be subsequently formed can suppress the leakage between source and drain via fin section below, thus sealing coat
End face can be higher than the end face of well region 1001w.That is, the dopant profiles of well region 1001w can be with the bottom of fin F ditch in other words
The bottom in road district keeps certain distance, such that it is able to random doping agent fluctuation (RDF) reduced in fin F channel region in other words, and
Therefore threshold voltage (Vt) change is reduced.
It is then possible to form the sacrificial gate stacking intersected with fin on sealing coat 1005.Such as, this can be carried out as follows.
Specifically, as shown in Figure 4, such as by deposit, sacrificial gate dielectric layer 1007 is formed.Such as, sacrificial gate dielectric layer 1007 is permissible
Including oxide, nitrogen oxides or oxide/nitride lamination, thickness is about 0.8～5nm.In the example depicted in fig. 4,
Illustrate only the sacrificial gate dielectric layer 1007 of " ∏ " shape.But, sacrificial gate dielectric layer 1007 can also be included in sealing coat 1005
End face on extend part.Then, such as by deposit, form sacrificial gate conductor layer 1009.Such as, sacrificial gate conductor layer
1009 can include polysilicon.Sacrificial gate conductor layer 1009 can be completely covered fin F, it is possible to carries out planarization process and such as changes
Learn mechanical polishing (CMP).Afterwards, sacrificial gate conductor layer 1009 is patterned, to form sacrificial gate stacking.Such as bowing in Fig. 5
Shown in view (sectional view shown in Fig. 1～4 is the cross section that AA ' line is obtained along Fig. 5), in this example, sacrificial gate is led
Body layer 1009 is patterned into the bar shaped intersecting (such as, vertical) with fin F.Can be with the sacrificial gate conductor layer 1009 after composition for covering
Mould, is patterned sacrificial gate dielectric layer 1007 further.Fig. 5 shows sacrificial gate dielectric layer 1007 patterned after feelings
Condition.
It follows that as shown in Fig. 6 (a) and 6 (b) (Fig. 6 (a) is top view, Fig. 6 (b) be along Fig. 6 (a) BB ' line section
Face figure) shown in, side wall 1011 can be formed on the sidewall of sacrificial gate stacking.It is about for example, it is possible to form thickness by deposit
The nitride of 5-20nm, then carries out RIE to nitride, forms side wall 1011.Those skilled in the art will know that various ways
Form this side wall, do not repeat them here.By controlling the height of sacrificial gate stacking (such as, by sacrificial gate conductor 1009 shape
Become comparison high), side wall 1011 can substantially be not formed on the sidewall of fin F.
Subsequently, as shown in Figure 7 shown in (sectional view of BB ' line along Fig. 6 (a)), (such as, fin F is carried out selective etch
Pass through TMAH solution) so that the part that fin F exposes can be selectively removed.This etching can be directivity, mainly
Downwards, then fin F is sacrificed grid stacking and the part exposed of side wall 1011 can be removed.So, fin F can substantially be only left at
Below sacrificial gate stacking.It addition, this etching can also have certain lateral etching so that fin F can be relative to side wall 1011
Periphery inwardly concave (it is desirable that relative to sacrificial gate stacking periphery not recessed), this recessed can suppress further with
During in rear ion implantation process, adulterant enters fin F.During selective removal fin F (such as, Si), sacrificial gate conductor layer
1009 (such as, polysilicons) are likely to be partially removed.
Preferably, after etching, the end face of ridge part in addition to being positioned at the fin F below sacrificial gate stacking can be with
The end face of sealing coat 1005 is substantially flush.If this end face is higher than the end face of sealing coat 1005, then the part exceeded subsequently from
Adulterant may be scattered or be diffused in fin F channel region in other words by sub-injection process；And this end face is less than sealing coat 1005
End face, then the PTS layer subsequently formed may away from the bottom surface certain distance of fin F channel region in other words, thus suppress leakage effect
Fruit deterioration.
Then, as shown in Figure 8 shown in (sectional view of BB ' line along Fig. 6 (a)), ion implanting can be passed through, formed
PTS layer 1013.Such as, for p-type device, can be with implant n-type adulterant such as As or P；For n-type device, can mix with implanted with p-type
Miscellaneous dose such as BF2Or B.Implantation dosage can be about 3E13～2E14cm-2.The direction that can be substantially perpendicular to substrate surface is carried out
Ion implanting.So, sacrificial gate stacking and side wall can effectively stop the adulterant of injection.Implantation Energy can be chosen as less
(such as, about 10～80KeV) makes it be unlikely to through sacrificial gate stacking, and in fin F both sides near the table of Semiconductor substrate 1001
Peak value is formed, to form doped region 1013 at face.The adulterant injected can enter into fin F due to reasons such as scattering or diffusions
Lower section, thus form PTS layer.Therefore, below fin, horizontal direction (that is, first direction) both sides senior middle school along figure can be there is
Between low doping concentration distribution.It addition, in source region and drain region (seeing 1015 in Fig. 9) lower section, PTS layer 1013 can have edge
The substantially uniform doping concentration distribution of first direction.
(Fig. 8 is perpendicular to along second direction from the two lateral middle degree entered in view of adulterant under normal circumstances
The direction of paper) generally uniform, therefore below fin, PTS layer 1013 has the most substantially uniform distribution.
It is to be herein pointed out in fig. 8, being shown in by PTS layer 1013 below the middle part of fin F discontinuous, this is only
It is only illustrative.PTS layer 1013 can be continuous print below fin.
Further, since there is sacrificial gate stacking at the top of fin F, such that it is able to suppression adulterant significantly is directly entered fin F
In.And, in the surrounding of fin F, the most there is not any material layer, therefore, be such as perpendicular to substrate surface in ion implanting
In the case of, can significantly suppress adulterant to enter fin F from the side-walls of fin F.Therefore, in this case, can be real in fin F
There is no in matter and adulterate intentionally.
It addition, in fin F both sides, be formed with high-doped zone 1013 in the surface of ridge, these high-doped zones are unfavorable for
Suppression leakage.According to embodiment of the disclosure, can selective etch ridge further so that these surfaces of ridge are entered
One step is recessed, to remove high-doped zone 1013 at least in part.This etching can be directivity, such as main downward, from
And high-doped zone 1013 is positioned at the part below fin F and may be retained and serve as PTS.
Afterwards, as shown in Fig. 9 (sectional view of BB ' line along Fig. 6 (a)), can on fin F selective epitaxial semiconductor layer
1015.During grown semiconductor layer 1015, can carry out adulterating in situ to it, such as, p-type be carried out for p-type device
Doping, carries out N-shaped doping for n-type device, thus serves as source region and the drain region of this device.The material of semiconductor layer 1015 is permissible
It is different from the material of fin F, such that it is able to apply stress to fin F (raceway groove particularly, formed in fin).Such as, semiconductor layer
1015 can include Si:C (atomic percent of C is about 0.2～2%) to apply tension (for n-type device), or can
To include SiGe (atomic percent of Ge is about 15～75%) to apply compressive stress (for p-type device).Semiconductor layer
1015 are likely on the end face of sacrificial gate conductor 1009 (polysilicon) growth.Certainly, the material of semiconductor layer 1015 can also
Identical with the material of fin F.
Then, as shown in Figure 10, interlevel dielectric layer can be formed such as by deposit in the structure shown in Fig. 9
1017.This interlevel dielectric layer 1017 such as can include oxide.Subsequently, this interlevel dielectric layer 1017 is planarized
Process such as CMP.This CMP can stop at side wall 1011, thus exposes sacrificial gate conductor layer 1009.Subsequently, example can be passed through
Such as TMAH solution, selective removal sacrificial gate conductor layer 1009, it is possible to removal sacrificial gate dielectric layer 1007 further, thus
Space (not shown) is defined inside side wall 1011.
Subsequently, such as Figure 11 (a)～11 (c), (Figure 11 (a) is top view, and Figure 11 (b) shows AA ' line along Figure 11 (a)
Sectional view, Figure 11 (c) shows the sectional view of BB ' line along Figure 11 (a)) shown in, by forming gate dielectric layer in space
1019 and grid conductor layer 1021, form final grid stacking.Gate dielectric layer 1019 can include high-K gate dielectric such as HfO2, thick
Degree is about 1-5nm.Grid conductor layer 1021 can include metal gate conductor.Between gate dielectric layer 1019 and grid conductor layer 1021 also
Work function regulating course (not shown) can be formed.
So, the semiconductor device according to this embodiment has just been obtained.As shown in Figure 11 (a)～11 (c), this semiconductor device
Part is included on substrate 1001 ridge formed.As it has been described above, ridge is defined as fin F and position by sealing coat 1005
Part below fin F.The opposite flank of fin F defines source region layer and drain region layer 1015.Grid stacking (1019/1021) with
Fin F intersects, and therefore defines channel region in fin F (specifically, fin F stacks the side and end face intersected with grid).At raceway groove
Bottom district, define PTS layer 1013.As it has been described above, below fin F, PTS layer 1013 has in the first direction that (that is, fin F prolongs
Stretch direction) doping concentration distribution low between the senior middle school of both sides, there is in a second direction (that is, the bearing of trend of grid stacking) generally uniform
Doping concentration distribution；And below source region and drain region 1015, it is dense that PTS layer 1013 has the most substantially uniform doping
Degree distribution.
Figure 12～14 shows the flow chart of the part stage manufacturing semiconductor device according to another embodiment of the disclosure.
Following, the main difference described with above-described embodiment.
As shown in figure 12, after the operation by describing above in association with Fig. 1～5 forms fin F, ion note can be carried out
Enter, to form PTS layer 1013.About the condition of ion implanting, it is referred to the description above in association with Fig. 8.In this example, note
The adulterant entered needs to arrive below fin through fin F.It is as noted previously, as sacrificial gate conductor 1009 of a relatively high, thus can
To prevent adulterant from entering in fin F directly through sacrificial gate conductor 1009.Certainly, in injection process, may there is a little portion
Adulterant is divided to be positioned at the part (corresponding to source, the position in drain region) of grid stacking both sides from fin F and enter (such as, scattering) fin F position
In part below grid stacking.As above example, below channel region, PTS layer 1013 can have along first
Doping concentration distribution low between direction (that is, the bearing of trend of fin F) both sides senior middle school, have in a second direction (that is, grid stacking prolong
Stretch direction) substantially uniform doping concentration distribution；And below source region and drain region, PTS layer 1013 can have in the first direction
Substantially uniform doping concentration distribution.It is with above example difference, in channel region, it is understood that there may be some doping are dense
Degree distribution.
Then, as shown in 13 (a) and 13 (b) (Figure 13 (a) is top view, Figure 13 (b) be along Figure 13 (a) BB ' line section
Face figure) shown in, side wall 1011 can be formed on the sidewall of sacrificial gate stacking.To this, it is referred to above in association with Fig. 6 (a) and 6
The description of (b).Afterwards, as shown in figure 14, fin F can be carried out selective etch so that the part that fin F exposes can be chosen
Property remove.To this, it is referred to the description above in association with Fig. 7.Certainly, in this embodiment it is possible to make fin F both sides ridge
Surface is the most recessed, to remove high-doped zone 1013 at least in part, as mentioned above.This way it is possible to avoid adulterant is from fin F
Be positioned at sacrificial gate stacking both sides part in travel further into fin F be positioned at grid stacking below part exist.
Ensuing process is same with the above-mentioned embodiment, is not described in detail in this, it is possible to obtain the semiconductor device being similar to
Part.
Figure 15 (a) shows according to the technique that describes above in association with Fig. 1～11 (c), different Implantation Energies (10Kev,
20Kev, 30Kev, 40Kev, 60Kev) under, imitative along fin short transverse (in other words, " degree of depth ", at the end face of fin, the degree of depth is 0)
True doping concentration distribution.It will be seen that according to this embodiment, at region (Hfin) place of fin, substantially free of dopant profiles.
Figure 15 (b) shows under the simulated conditions identical with Figure 15 (a), for the work described above in association with Figure 12～14
Simulated dopant concentration distribution obtained by skill.It will be seen that at region (Hfin) place of fin, there are some little distribution peaks.
Example as a comparison, Figure 15 (c) shows under the simulated conditions identical with Figure 15 (a) and 15 (b), for routine
The simulated dopant concentration distribution that technique obtains.It will be seen that at region (Hfin) place of fin, there is bigger distribution peaks.
Therefore, according to embodiment of the disclosure, can significantly suppress even to avoid adulterant to enter fin channel region in other words
In.According to simulation result, the technique described above in association with Fig. 1～11 (c) can realize, relative to common process, the Vt that RDF causes
Change is decreased to about 2.04mV (in the case of 60KeV Implantation Energy) from about 7.76mV, or is decreased to about from about 37.5mV
2.5mV (in the case of 10KeV Implantation Energy).
Semiconductor device according to disclosure embodiment can apply to various electronic equipment.Such as, by integrated multiple
Such semiconductor device and other devices (such as, the transistor etc. of other forms), can form integrated circuit (IC), and
Thus build electronic equipment.Therefore, the disclosure additionally provides a kind of electronic equipment including above-mentioned transistor.Electronic equipment also may be used
To include the parts such as the display screen coordinated with integrated circuit and the wireless transceiver that coordinates with integrated circuit.This electronics sets
Standby such as smart phone, panel computer (PC), personal digital assistant (PDA) etc..
According to embodiment of the disclosure, additionally provide the manufacture method of a kind of chip system (SoC).The method can include
The method of above-mentioned manufacture semiconductor device.Specifically, can on chip integrated multiple device, at least some of which be according to this
Disclosed method manufactures.
In the above description, the ins and outs such as the composition of each layer, etching are not described in detail.But
It will be appreciated by those skilled in the art that and can form the layer of required form, region etc. by various technological means.It addition, be
Formation same structure, those skilled in the art can be devised by method the most identical with process as described above.
Although it addition, respectively describing each embodiment above, but it is not intended that the measure in each embodiment can not be favourable
Be used in combination.
Embodiment the most of this disclosure is described.But, the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by claims and equivalent thereof.Without departing from these public affairs
The scope opened, those skilled in the art can make multiple replacement and amendment, and these substitute and amendment all should fall in the disclosure
Within the scope of.
Claims (20)
1. a semiconductor device, including:
Substrate；
The fin extended in a first direction formed on substrate, fin includes being positioned at the of its opposite two ends in a first direction
One side and the second side；
The source region layer formed on first side and the second side of fin respectively and drain region layer；
The grid stacking extended along the second direction that intersects with first direction formed on substrate, grid stack intersect with fin thus
Fin limits channel region；And
The break-through formed in the substrate bottom channel region stops (PTS) layer, and wherein, below fin, PTS layer has along first party
Doping concentration distribution low between the senior middle school of both sides.
Semiconductor device the most according to claim 1, wherein, below source region layer and drain region layer, PTS layer has along first
The substantially uniform doping concentration distribution in direction.
Semiconductor device the most according to claim 1, wherein, below fin, PTS layer has the most equal
Even doping concentration distribution.
Semiconductor device the most according to claim 1, wherein, substrate is body Semiconductor substrate, and fin is by this body quasiconductor
A part for the ridge that substrate is formed,
This semiconductor device also includes: the sealing coat formed on substrate, wherein ridge is positioned at the part structure above sealing coat
Become fin.
Semiconductor device the most according to claim 4, also includes: the well region formed in the substrate below fin.
Semiconductor device the most according to claim 5, wherein, the end face of sealing coat is higher than the end face of well region.
Semiconductor device the most according to claim 1, wherein, source region layer includes the quasiconductor material different from fin with drain region layer
Material.
Semiconductor device the most according to claim 1, wherein, fin expanded range in a first direction and grid are stacked on the
Expanded range on one direction is substantially the same.
Semiconductor device the most according to claim 1, wherein, substantially non-impurity-doped in fin.
10. the method manufacturing semiconductor device, including:
Substrate is formed the ridge extended in a first direction；
Substrate is formed the sacrificial gate stacking extended along the second direction intersected with first direction thus intersect with ridge；
Ridge is carried out selective etch, makes the part serving as the fin of semiconductor device in ridge substantially stay in sacrificial gate
Below stacking；
Carry out ion implanting, to form break-through prevention (PTS) layer below fin in the substrate；
The side of ridge is formed source region layer and drain region layer；And
Replace sacrificial gate stacking to form real grid stacking.
11. methods according to claim 10, wherein, and are selecting ridge after forming sacrificial gate stacking
Property etching before, the method also includes:
The sidewall of sacrificial gate stacking is formed side wall, wherein, makes to serve as the part of fin not to the selective etch of ridge
Periphery beyond side wall.
12. methods according to claim 10, wherein, after selective etch ridge, ridge is except being positioned at sacrifice
The end face of the remainder outside part below grid stacking is substantially flush with the bottom surface of fin.
13. methods according to claim 12, wherein, after ion implantation and formed source region layer and drain region layer it
Before, the method also includes:
Selective etch ridge, makes the end face of described remainder decline further.
14. 1 kinds of methods manufacturing semiconductor device, including:
Substrate is formed the ridge extended in a first direction；
Substrate is formed the sacrificial gate stacking extended along the second direction intersected with first direction thus intersect with ridge；
Carry out ion implanting, to form break-through prevention (PTS) layer at certain position in the substrate；
Ridge is carried out selective etch, makes the part serving as the fin of semiconductor device in ridge substantially stay in sacrificial gate
Below stacking；
The side of ridge is formed source region layer and drain region layer；And
Replace sacrificial gate stacking to form real grid stacking.
15. methods according to claim 14, wherein, after ion implantation and are carrying out selective etch to ridge
Before, the method also includes:
The sidewall of sacrificial gate stacking is formed side wall, wherein, makes to serve as the part of fin not to the selective etch of ridge
Periphery beyond side wall.
16. according to the method described in claim 10 or 14, wherein, by epitaxial growth, forms quasiconductors different from ridge
The source region layer of material and drain region layer.
17. according to the method described in claim 10 or 14, and wherein, substrate is body Semiconductor substrate, after forming ridge
And before forming sacrificial gate stacking, the method also includes:
Forming sealing coat on substrate, the part that wherein ridge is positioned at above sealing coat serves as fin.
18. methods according to claim 17, also include:
Forming well region in the substrate, wherein the end face of sealing coat is higher than the end face of well region.
19. 1 kinds of electronic equipments, including the integrated electricity formed by the semiconductor device as according to any one of claim 1～9
Road.
20. electronic equipments according to claim 19, also include: the display that coordinates with described integrated circuit and with institute
State the wireless transceiver that integrated circuit coordinates.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281482A (en) * | 2017-01-06 | 2018-07-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111106111A (en) * | 2019-11-29 | 2020-05-05 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| CN111916448A (en) * | 2020-07-01 | 2020-11-10 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method thereof and electronic equipment |
| WO2021103910A1 (en) * | 2019-11-29 | 2021-06-03 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor, and electronic device comprising semiconductor device |
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| US9087860B1 (en) * | 2014-04-29 | 2015-07-21 | Globalfoundries Inc. | Fabricating fin-type field effect transistor with punch-through stop region |
| CN105304716A (en) * | 2012-11-30 | 2016-02-03 | 中国科学院微电子研究所 | Finfet and manufacturing method thereof |
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| CN105304716A (en) * | 2012-11-30 | 2016-02-03 | 中国科学院微电子研究所 | Finfet and manufacturing method thereof |
| US9087860B1 (en) * | 2014-04-29 | 2015-07-21 | Globalfoundries Inc. | Fabricating fin-type field effect transistor with punch-through stop region |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108281482A (en) * | 2017-01-06 | 2018-07-13 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108281482B (en) * | 2017-01-06 | 2022-04-15 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111106111A (en) * | 2019-11-29 | 2020-05-05 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| WO2021103910A1 (en) * | 2019-11-29 | 2021-06-03 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method therefor, and electronic device comprising semiconductor device |
| CN111106111B (en) * | 2019-11-29 | 2021-11-16 | 中国科学院微电子研究所 | Semiconductor device, method of manufacturing the same, and electronic apparatus including the same |
| CN111916448A (en) * | 2020-07-01 | 2020-11-10 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method thereof and electronic equipment |
| CN111916448B (en) * | 2020-07-01 | 2023-10-13 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method thereof and electronic equipment |
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