CN108281482A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN108281482A
CN108281482A CN201710011818.7A CN201710011818A CN108281482A CN 108281482 A CN108281482 A CN 108281482A CN 201710011818 A CN201710011818 A CN 201710011818A CN 108281482 A CN108281482 A CN 108281482A
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fin
static discharge
opening
annealing
doped region
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CN108281482B (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A kind of semiconductor structure and forming method thereof, the forming method includes：Substrate is provided, there is fin on the substrate；Gate structure is formed on the fin, the gate structure is across the surface of the fin and covering the fin atop part and partial sidewall；The first etching processing is carried out, forms opening in the fin of the gate structure both sides；Static discharge injection is carried out to the fin for being formed with opening, static discharge doped region is formed in the fin, there is first kind ion in the static discharge doped region；Stressor layers are formed in the opening, and to form the source and drain doping area being located on the static discharge doped region, there is Second Type ion in the source and drain doping area.Technical solution of the present invention effectively improves the quality of formed stressor layers, reduces the stress that stressor layers discharge in source and drain doping area forming process, is conducive to the performance for improving formed stressor layers, is conducive to the performance for improving formed semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
As integrated circuit develops to super large-scale integration, the current densities of IC interior are increasing, institute Including component number it is also more and more, the size of component also reduces therewith.With the reduction of MOS device size, MOS devices The raceway groove of part shortens therewith.Due to channel shortening, the gradual channel approximation of MOS device is no longer set up, and highlight it is various unfavorable Physical effect (especially short-channel effect), this makes device performance and reliability degenerate, and limits device size It further reduces.
In order to further reduce the size of MOS device, people have developed multi-panel grid field effect transistor structure, to improve The control ability of MOS device grid inhibits short-channel effect.Wherein fin formula field effect transistor is exactly a kind of common multi-panel grid Structure transistor.
Fin formula field effect transistor is stereochemical structure, including substrate, and one or more protrusions are formed on the substrate Fin is provided between fin and is dielectrically separated from component；Grid is across on fin and covers top and the side wall of the fin.Due to this vertical Body structure and the transistor of conventional planar structure have larger difference, if some processes misoperation may be to forming device Electric property makes a big impact.
In addition, with the continuous improvement of semiconductor process technique ability, the size of semiconductor devices constantly reduces.Electrostatic is put Electric (Electrostatic Discharge, ESD) becomes original more notable to the harm of semiconductor integrated circuit.And with The extensive utilization of semiconductor chip causes semiconductor chip also more and more by the factor of electrostatic damage.According to statistics, electricity is integrated 35% is caused by electrostatic discharge problem in the product of road failure.So in order to adjust junction breakdown voltage (the Junction breakdown voltage), the trigger voltage (trigger voltage) of electro-static discharging device is adjusted, in shape During at semiconductor structure, need to carry out static discharge injection.
But the semiconductor structure of static discharge injection is introduced, often there is a problem of that electric property is bad.
Invention content
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, to improve the electricity of semiconductor structure Learn performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, there is fin on the substrate；Form gate structure on the fin, the gate structure across The surface of the fin and covering the fin atop part and partial sidewall；The first etching processing is carried out, in the grid knot Opening is formed in the fin of structure both sides；Static discharge injection, the shape in the fin are carried out to the fin for being formed with opening At static discharge doped region, there is first kind ion in the static discharge doped region；Stressor layers are formed in the opening, To form the source and drain doping area being located on the static discharge doped region, there is Second Type ion in the source and drain doping area.
Optionally, the step of the first etching processing of progress includes：The first etching processing is carried out, in the gate structure both sides Fin in form opening of the depth in 15nm to 40nm ranges.
Optionally, the step of the first etching processing of progress includes：First etching processing is carried out by dry method mode.
Optionally, in the step of carrying out static discharge injection to the fin for being formed with opening, the semiconductor structure For NMOS device when, technological parameter is：Injection ion is B, and in 3KeV to 15KeV ranges, implantation dosage exists Implantation Energy 1.0E12atom/cm2To 2.0E15atom/cm2In range；When the semiconductor structure is PMOS device, technological parameter is：Note It is P to enter ion, and Implantation Energy is in 5KeV to 30KeV ranges, and implantation dosage is in 1.0E12atom/cm2To 2.0E15atom/cm2 In range.
Optionally, the forming method further includes：It is formed after gate structure on the fin, in the gate structure It is formed before opening in the fin of both sides, lightly doped drain injection is carried out to the fin of the gate structure both sides, in the fin Interior formation lightly doped district, the lightly doped district is interior to have Second Type ion；Electrostatic is carried out to the fin for being formed with opening Electric discharge injection the step of include：Static discharge injection is carried out to the fin for being formed with opening, under the lightly doped district The static discharge doped region is formed in fin；After carrying out static discharge injection to the fin for being formed with opening, in institute It states in opening and is formed before stressor layers, the fin to being formed with lightly doped district and static discharge doped region carries out at the first annealing Reason.
Optionally, the step of carrying out the first annealing to the fin for being formed with lightly doped district and static discharge doped region is wrapped It includes：The first annealing is carried out to the fin for being formed with lightly doped district and static discharge doped region by way of spike annealing.
Optionally, the step of the first annealing being carried out to the fin for being formed with lightly doped district and static discharge doped region In, annealing temperature is within the scope of 950 DEG C to 1100 DEG C.
Optionally, the forming method further includes：Fin to being formed with lightly doped district and static discharge doped region carries out It after first annealing, is formed before stressor layers in the opening, carries out the second etching processing, remove the opening sidewalls With some materials of bottom.
Optionally, the step of the second etching processing of progress includes：Carry out the second etching processing, remove the opening sidewalls and The material of bottom 10nm to 20nm thickness.
Optionally, include to the step of opening sidewalls and bottom the second etching of progress：Institute is carried out by dry method mode State the second etching processing.
Optionally, formed be located at the static discharge doped region on source and drain doping area the step of include：To the opening Interior filling semiconductor material, forms stressor layers in the opening；Source and drain injection is carried out to the stressor layers, in the electrostatic The source and drain doping area is formed on electric discharge doped region.
Optionally, include the step of filling semiconductor material into the opening：To described by way of epitaxial growth Filling semiconductor material in opening.
Optionally, in the step of carrying out source and drain injection to the stressor layers, when the semiconductor structure is PMOS device, work Skill parameter is：Injection ion is B, and Implantation Energy is in 1KeV to 5KeV ranges, and implantation dosage is in 1.0E15atom/cm2It arrives 5.0E15atom/cm2In range；When the semiconductor structure is NMOS device, injection ion is P, and Implantation Energy is arrived in 3KeV Within the scope of 10KeV, implantation dosage is in 1.0E15atom/cm2To 5.0E15atom/cm2In range.
Optionally, after carrying out source and drain injection to the stressor layers, the forming method further includes：It carries out at the second annealing Reason, to activate the Doped ions in the source and drain doping area.
Optionally, the step of the second annealing of progress includes：Is carried out by way of spike annealing or laser annealing Two annealings.
Optionally, in the step of carrying out the second annealing by spike annealing, annealing temperature is at 1000 DEG C to 1100 DEG C In range；In the step of carrying out the second annealing by way of laser annealing, annealing temperature is in 1200 DEG C to 1300 DEG C models In enclosing.
Correspondingly, the present invention also provides a kind of semiconductor structures, including：
Substrate has fin on the substrate；Gate structure on the fin, the gate structure is across described The surface of fin and covering the fin atop part and partial sidewall；Opening in the fin of the gate structure both sides； Static discharge doped region in fin below the opening, the static discharge doped region is interior to have first kind ion.
Optionally, the depth of the opening is in 15nm to 40nm ranges.
Optionally, when the semiconductor structure is NMOS device, Doped ions are B in the static discharge doped region, are mixed Heteroion concentration is in 1.0E18atom/cm3To 5.0E19atom/cm3In range；When the semiconductor structure is PMOS device, institute It is P to state Doped ions in static discharge doped region, and Doped ions concentration is in 1.0E18atom/cm3To 5.0E19atom/cm3Range It is interior.
Optionally, the semiconductor structure further includes：Lightly doped district in the fin of gate structure both sides, it is described gently to mix There is Second Type ion, the lightly doped district to be located in miscellaneous area on the static discharge doped region.
Compared with prior art, technical scheme of the present invention has the following advantages：
In technical solution of the present invention, formed after opening in the fin of gate structure both sides；To being formed with the fin of opening Portion carries out static discharge injection, and the static discharge doped region with first kind ion is formed in the fin；It is quiet being formed After discharge of electricity doped region, stressor layers and source and drain doping area are formed in the opening.Since static discharge is infused in described answer Power floor and source and drain doping area carry out before being formed, therefore static discharge injection will not be to the stressor layers and source and drain doping area Lattice damage is caused, the quality of formed stressor layers can be effectively improved, stressor layers in source and drain doping area forming process is reduced and releases The stress put is conducive to the performance for improving formed stressor layers, is conducive to the performance for improving formed semiconductor structure.
In alternative of the present invention, formed after gate structure on the fin, the fin in the gate structure both sides It is formed before opening in portion, lightly doped drain injection is carried out to the fin of the gate structure both sides, is formed in the fin light Doped region；And after carrying out static discharge injection to the fin for being formed with opening, stress is formed in the opening Before layer, the fin to being formed with lightly doped district and static discharge doped region makes annealing treatment.The annealing was both used for Activate the Doped ions in the lightly doped district, be additionally operable to repair static discharge injection and be lightly doped injection after the fin by The damage arrived, the formation for the follow-up stressor layers provide good growing surface；This way can either effectively improve institute The quality of stressor layers is formed, and the number that heating process carries out in the semiconductor forming method can be reduced, is conducive to improve The performance of formed semiconductor structure.
In alternative of the present invention, the forming method further includes：To being formed with lightly doped district and static discharge doped region Fin made annealing treatment after, formed before stressor layers in the opening, carry out the second etching processing, opened described in removal The some materials of mouth side wall and bottom.Second etching repairs opening sidewalls and bottom for removing not completing in annealing Material, to improve the quality for forming the open bottom and side wall during stressor layers, be stressor layers formation improve it is good Good growing surface, is conducive to the quality for improving formed stressor layers, is conducive to the performance for improving the semiconductor structure.
Description of the drawings
Fig. 1 is a kind of corresponding cross-sectional view of method for forming semiconductor structure corresponding steps；
Fig. 2 to Figure 10 is the corresponding cross-section structure signal of each step of one embodiment of method for forming semiconductor structure of the present invention Figure.
Specific implementation mode
By background technology, it is found that introducing the semiconductor structure of static discharge injection in the prior art, that there are electric properties is bad The problem of.The original of the bad problem of its electric property is analyzed in conjunction with a kind of introducing static discharge injection method for forming semiconductor structure Cause：
With reference to figure 1, a kind of corresponding cross-sectional view of method for forming semiconductor structure corresponding steps is shown.
As shown in Figure 1, the forming method of the semiconductor structure includes：
Substrate 10 is provided, there is fin 11 on the substrate；Gate structure 13, the grid are formed on the fin 11 Structure 13 is across the surface of the fin 11 and covering fin 11 atop part and partial sidewall；In the gate structure 13 Stressor layers 14 are formed in the fins 11 of both sides, and the stressor layers 14 are doped and are made annealing treatment with activate doping from Son forms source and drain doping area.
In order to adjust junction breakdown voltage, the trigger voltage of electro-static discharging device is adjusted；In addition in order to reduce heating process It uses, reduces the heat budget (thermal budget) for forming the semiconductor structure, be doped to the stressor layers 14 Later, before being made annealing treatment, the forming method further includes：The fin 11 of 13 both sides of the gate structure is carried out quiet Discharge of electricity injection 15, forms static discharge doped region 16 under the source and drain doping area.
Since formed static discharge doped region 16 is located under the source and drain doping area, so the static discharge doped region 16 depth is larger, therefore the Implantation Energy of static discharge injection 15 is larger.And in the step for carrying out static discharge injection 15 When rapid, stressor layers 14 are formed in the fin 11 of 13 both sides of gate structure, so the injection ion of static discharge injection 15 It can be across the stressor layers 14.
The static discharge injection 15 of large energy can cause larger lattice damage in the stressor layers 14.Therefore, quiet Annealing after discharge of electricity injection 15 is applied not only to activation Doped ions and forms source and drain doping area, is additionally operable to repair stress Lattice damage in layer 14.But the process that annealing repairs lattice damage in stressor layers 14 can cause stressor layers 14 to be answered The problem of power discharges.14 stress release of stressor layers is excessive, can influence stressor layers 14 and apply to the semiconductor structure channel region The effect of stress influences the performance of formed stressor layers 14, to cause formed semiconductor structure performance degradation, causes partly to lead The bad problem of body structure electric property.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：
Substrate is provided, there is fin on the substrate；Form gate structure on the fin, the gate structure across The surface of the fin and covering the fin atop part and partial sidewall；The first etching processing is carried out, in the grid knot Opening is formed in the fin of structure both sides；Static discharge injection, the shape in the fin are carried out to the fin for being formed with opening At static discharge doped region, there is first kind ion in the static discharge doped region；Stressor layers are formed in the opening, To form the source and drain doping area being located on the static discharge doped region, there is Second Type ion in the source and drain doping area.
In technical solution of the present invention, formed after opening in the fin of gate structure both sides；To forming the fin of opening again Portion carries out static discharge injection, and the static discharge doped region with first kind ion is formed in the fin；It is quiet being formed After discharge of electricity doped region, stressor layers and source and drain doping area are formed in the opening.Since static discharge is infused in described answer Power floor and source and drain doping area carry out before being formed, therefore static discharge injection will not be to the stressor layers and source and drain doping area Lattice damage is caused, the quality of formed stressor layers can be effectively improved, stressor layers in source and drain doping area forming process is reduced and releases The stress put is conducive to the performance for improving formed stressor layers, is conducive to the performance for improving formed semiconductor structure.
To make the above purposes, features and advantages of the invention more obvious and understandable, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.
Referring to figs. 2 to Figure 10, shows that each step of one embodiment of method for forming semiconductor structure of the present invention is corresponding and cut open Face structural schematic diagram.
It should be noted that the present embodiment for forming the process of two non-conterminous N-type transistors to illustrate.This In invention other embodiment, the method for forming semiconductor structure can be also used for being formed other semiconductor junctions such as P-type transistor Structure, or can be also used for forming adjacent semiconductor structure, the present invention should not be limited with this.
With reference to figure 2, substrate 100 is provided, there is fin 101 on the substrate 100.
The substrate 100 is for providing technological operation platform.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also Be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator, Glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate can To choose the material for being suitable for process requirements or being easily integrated.
The fin 101 is used to provide the raceway groove of the fin formula field effect transistor.
In the present embodiment, the material identical of the material of the fin 101 and the substrate 100 is all monocrystalline silicon.The present invention In other embodiment, the material of the fin can also be different from the material of the substrate, can be selected from germanium, germanium silicon, carbon silicon or GaAs etc. is suitable for forming the material of fin.
Specifically, the substrate 100 and the fin 101 can be formed simultaneously.Form the substrate 100 and the fin 101 the step of includes：Initial substrate is provided；Fin mask layer (not shown) is formed in the initial substrate surface；With institute It is initial substrate described in mask etching to state fin mask layer, forms the substrate 100 and the fin on the substrate 100 101。
The fin mask layer is used to define size and the position of the fin 101.
The step of forming the fin mask layer include：Mask layer is formed in the initial substrate；It is covered described Graph layer is formed in membrane layers；Using the graph layer as mask, the mask layer is etched, exposes the initial substrate, To form the fin mask layer.
The graph layer is for being patterned the mask layer, to define size and the position of the fin.
In the present embodiment, the graph layer is patterned photoresist layer, can pass through coating process and photoetching process shape At.In other embodiments of the invention, the graph layer can also be that multiple graphical masking process is formed by mask, to reduce The distance between the characteristic size of fin and adjacent fin improve the integrated level of formed semiconductor structure.Wherein multigraph Shape masking process includes：Self-alignment duplex pattern (Self-aligned Double Patterned, SaDP) technique, from It is directed at triple graphical (Self-aligned Triple Patterned) techniques or the graphical (Self- of autoregistration quadruple Aligned Double Double Patterned, SaDDP) technique.
It should be noted that in the present embodiment, is formed after the substrate 100 and the fin 101, retain the fin The fin mask layer at 101 tops.The material of the fin mask layer is silicon nitride, for defining flat chemical industry in the subsequent process The stop-layer position of skill, and play the role of protecting fin 101.
In the present embodiment, after forming the substrate 100 and the fin 101, the forming method further includes：Described Separation layer (not indicated in figure) is formed on the substrate 100 that fin 101 exposes, and is less than the fin 101 at the top of the separation layer The part surface of top and covering 101 side wall of fin.
The separation layer is for realizing the electric isolution between adjacent fin 101 and between adjacent semiconductor constructs.
In the present embodiment, the material of the separation layer is silica.In other embodiments of the invention, the material of the separation layer Material can also be the materials such as silicon nitride or silicon oxynitride.
The step of forming the separation layer include：By chemical vapor deposition (such as：Fluid chemistry be vapor-deposited) etc. side Method is not being formed spacer material layer on substrate 100 that the fin 101 covers, and the spacer material layer covers the fin and covers Film layer；The spacer material layer higher than the fin mask layer is removed by modes such as chemical mechanical grindings；By way of returning and carving The segment thickness of the remaining spacer material layer of removal is to form separation layer.
It should be noted that being formed after the separation layer, the forming method further includes：Remove the fin mask Layer, exposes the top surface of the fin 101.
With continued reference to Fig. 2, gate structure 110 is formed on the fin 101, the gate structure 110 is across the fin Portion 101 and the surface of covering fin 101 atop part and partial sidewall.
The gate structure 110 is used for the shield portions fin 101 during being subsequently formed source and drain doping area, avoids institute Source and drain doping area is formed to be in direct contact.In the present embodiment, the gate structure 110 is pseudo- grid structure, therefore the gate structure 110 are additionally operable to take up space position by the follow-up gate structure that formed.In other embodiments of the invention, the gate structure may be used also Think the actual gate structure of formed semiconductor structure, therefore the gate structure 110 is additionally operable to the formed semiconductor of control In structure the conducting of raceway groove with block.
In the present embodiment, the gate structure 110 is single layer structure, including the dummy grid of polycrystalline silicon material (do not mark in figure Show).In other embodiments of the invention, the material of the dummy grid can also be silica, silicon nitride, silicon oxynitride, silicon carbide, The other materials such as carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In other of the invention embodiments, dummy gate structure can be with For laminated construction, including dummy grid and the pseudo- oxide layer on the dummy grid, the material of the puppet oxide layer can be Silica and silicon oxynitride.
The step of forming the gate structure 110 include：Gate material layers are formed on the substrate 100；In the grid Gate mask layer (not indicated in figure) is formed in the material layer of pole etches the grid material using the gate mask layer as mask Layer, forms the gate structure 110.
It should be noted that after forming the gate structure 110, also side is formed on the side wall of the gate structure 110 Wall (does not indicate) in figure.The material of the side wall can be silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, Silicon oxynitride, boron nitride or boron carbonitrides, the side wall can be single layer structure or laminated construction.In the present embodiment, the side Wall is single layer structure, and the material of the side wall is silicon nitride.
Referring to figs. 2 to Fig. 4, the first etching processing 131 is carried out, is formed in the fin 101 of 110 both sides of the gate structure Opening 130.Wherein Fig. 4 is in Fig. 3 along the cross-sectional view of AA lines.
The opening 130 for the formation of follow-up stressor layers for providing Process ba- sis.In addition, first etching processing 131 some materials for removing 110 both sides fin 101 of the gate structure, to reduce the height of fin 101 at opening 130. The reduction of 101 height of fin can effectively reduce the Implantation Energy in follow-up static discharge injection step, advantageously reduce quiet Discharge of electricity injects the damage to fin 101, is conducive to the performance for improving formed semiconductor structure.
It in the present embodiment, is illustrated for forming N-type transistor, so the opening 130 is open for " u "-shaped.Institute To include the step of carrying out the first etching processing 131：First etching processing 131 is carried out by way of dry method, with removal The some materials of 110 both sides fin 101 of gate structure, to form the opening 130.In other embodiments of the invention, formed When semiconductor structure is P-type transistor, the shape of the opening may be " ∑ " shape.
Specifically, in the step of carrying out the first etching processing 131, process gas includes：CF4, flow 10sccm Into 80sccm；H2, flow is in 50sccm to 210sccm ranges；O2, in 50sccm to 215sccm ranges；Process warm Degree is within the scope of 60 DEG C to 80 DEG C；Process time is in 5s to 20s ranges.
In other embodiments of the invention, carry out first etching processing the step of in, process gas includes：CH3F, stream Amount is in 50sccm to 800sccm ranges；He, flow are in 80sccm to 500sccm ranges；Technological temperature is at 50 DEG C to 350 Within the scope of DEG C；Process time is in 8s to 100s ranges.
It should be noted that in the step of carrying out the first etching processing 131, the depth of the opening 130 should not mistake Also unsuitable too small greatly.
In the step of carrying out the first etching processing 131, if the depth of the opening 130 is too small, remaining fin 101 height is excessive, is unfavorable for the reduction of Implantation Energy in follow-up static discharge injection step, is unfavorable for static discharge injection pair The reduction that fin 101 damages；In the step of carrying out the first etching processing 131, if the depth of the opening 130 is too big, Then the height of remaining fin 101 is too small, can cause follow-up distance mistake between formed static discharge doped region and source and drain doping area Small, the presence of static discharge doped region can influence the performance in source and drain doping area, cause the degeneration of formed semiconductor structure performance. So in the present embodiment, the step of carrying out the first etching processing 131, includes：The first etching processing 131 is carried out, in the grid knot Opening 130 of the depth in 15nm to 40nm ranges is formed in the fin 101 of 110 both sides of structure.
It should be noted that as shown in Figures 2 and 3, in order to inhibit the short-channel effect in formed semiconductor structure, It is formed after gate structure 110 on the fin 101, forms opening 130 in the fin 101 of 110 both sides of the gate structure Before, the forming method further includes：Lightly doped drain injection 121 is carried out to the fin 101 of 110 both sides of the gate structure, Lightly doped district 120 is formed in the fin 101, and there is Second Type ion in the lightly doped district 120.
The lightly doped district 120 is used to be formed shallow junction in semiconductor structure to inhibit short-channel effect, and inhibits raceway groove Leakage current effects.
In the present embodiment, formed semiconductor structure is N-type transistor, so 121 injection of lightly doped drain injection Second Type ion is N-type ion, such as P ion.In other embodiments of the invention, formed semiconductor structure is P-type crystal Pipe, so the Second Type ion of lightly doped drain injection is p-type ion, such as B ions.
With reference to figure 5, static discharge injection 150 is carried out to the fin 101 for being formed with opening 130, in the fin 101 Interior formation static discharge doped region 160, the static discharge doped region 160 is interior to have first kind ion.
The step of static discharge injection 150, in the fin 101 for forming static discharge doped region 160.Institute State the conduction type when conduction type of Doped ions is connected with formed semiconductor structure raceway groove in static discharge doped region 160 Difference, i.e., the conduction of the conduction type of Doped ions and follow-up formed source and drain doping area in the described static discharge doped region 160 Type is different.Therefore PN junction can be formed between the static discharge doped region 160 and follow-up formed source and drain doping area, to It can realize the purpose for adjusting junction breakdown voltage, adjusting electro-static discharging device trigger voltage.
Due to being formed with opening 130 in the fin 101 of 110 both sides of the gate structure, static discharge note is being carried out In the step of entering 150, the height of the fin 101 is relatively low.The reduction of 101 height of fin can effectively reduce the electrostatic The Implantation Energy of electric discharge injection 150 advantageously reduces the damage that the fin 101 is subject in the process of static discharge injection 150.
Specifically, in the step of carrying out static discharge injection 150 to the fin 101 for being formed with opening 130, described half When conductor structure is NMOS device, technological parameter is：Injection ion is B, and Implantation Energy is in 3KeV to 15KeV ranges, injection Dosage is in 1.0E12atom/cm2To 2.0E15atom/cm2In range；When the semiconductor structure is PMOS device, technological parameter For：Injection ion is P, and Implantation Energy is in 5KeV to 30KeV ranges, and implantation dosage is in 1.0E12atom/cm2It arrives 2.0E15atom/cm2In range.
It should be noted that in the present embodiment, there is the lightly doped district 120 for being used to form shallow junction in the fin 101, because This carries out the step of static discharge injects 150 to the fin 101 for being formed with opening 130：It is formed with opening to described 130 fin 101 carries out static discharge injection 150, and forming the electrostatic in the fin 101 under the lightly doped district 120 puts Electrically doped area 160, that is to say, that the static discharge doped region 160 is located under the lightly doped district 120.
With reference to figure 6 to Figure 10, stressor layers 181 are formed in the opening 130, are adulterated positioned at the static discharge with being formed Source and drain doping area in area 160 has Second Type ion in the source and drain doping area.Wherein, Figure 10 is in Fig. 9 along BB lines Cross-sectional view.
The stressor layers 181 are used to form the source and drain doping area of semiconductor structure.
Formed be located at the static discharge doped region 160 on source and drain doping area the step of include：To the opening 130 (as shown in Figure 7) interior filling semiconductor material forms stressor layers 181 (as shown in Figure 8) in the opening 130；It answers described Power layer 181 carries out source and drain and injects 182 (as shown in Figure 8), to form the source and drain doping being located on the static discharge doped region 180 Area.
In the present embodiment, the semiconductor structure is N-type transistor, so the semi-conducting material is SiC, that is, It says, the material of the stressor layers 181 is SiC.The stressor layers 181 of SiC can apply into the raceway groove of formed semiconductor structure Tensile stress improves the performance of formed semiconductor structure to be conducive to improve the mobility of raceway groove carriers.
In other embodiments of the invention, when the semiconductor structure is P-type transistor, the semi-conducting material is SiGe, That is, the material of the stressor layers is SiGe.The stressor layers of SiGe can be applied into the raceway groove of formed semiconductor structure Pressurize stress, to be conducive to improve the mobility of raceway groove carriers, improves the performance of formed semiconductor structure.
Specifically, including the step of filling semiconductor material into the opening 130：To institute by way of epitaxial growth State filling semiconductor material in opening 130.
It is described to answer since the stressor layers 181 are formed in by way of epitaxial growth in the opening 130 The quality of power layer 181 is related to the opening lattice quality on 130 bottom and side wall surfaces.The static discharge injection 150 is (such as Shown in Fig. 5) lattice damage can be caused in fin 101, to influence the matter of 130 bottom and side wall lattice surfaces of the opening Amount, impacts the quality of formed stressor layers 181.So as shown in fig. 6, to the fin 101 for being formed with opening 130 After carrying out static discharge injection 150, before forming stressor layers 181 in the opening 130, to being formed with lightly doped district 120 The first annealing 170 is carried out with the fin 101 of static discharge doped region 160.
The step of first annealing 170 lattice damage for repairing in the fin 101, described in improving Be open the lattice quality on 139 bottom and side wall surfaces, and preferable growing surface is provided for the formation of the stressor layers 181；In addition, After lightly doped drain injects 121 (as shown in Figure 2) and static discharge injects 150 (as shown in Figure 5), first annealing is carried out Processing 170, first annealing 170 are additionally operable to activate in the lightly doped district 120 and the static discharge doped region 160 Doped ions.
The step of carrying out the first annealing 170 after static discharge injection 150, can be in the first annealing In 170 steps, while the purpose for activating the lightly doped district 120 and repairing fin 101 is realized, to reduce making for heating process With advantageously reducing the heat budget to form the semiconductor structure, be conducive to the performance for improving formed semiconductor structure.
Specifically, being carried out at the first annealing to the fin 101 for being formed with lightly doped district 120 and static discharge doped region 160 The step of managing 170 include：To being formed with the fin of lightly doped district 120 and static discharge doped region 160 by way of spike annealing Portion 101 carries out the first annealing 170.
It should be noted that carry out it is described first annealing 170 the step of in, annealing temperature should not it is too high also should not be too It is low, annealing time it is unsuitable it is too long also should not be too short.
In the step of carrying out first annealing 170, if annealing temperature is too low, if annealing time is too short, meeting The activation of Doped ions in the lightly doped district 120 and static discharge doped region 160 is influenced, can also be influenced at first annealing Manage the repair of 170 pairs of 101 lattice damages of the fin, it is difficult to effectively improve 130 bottom and side wall surfaces of the opening Lattice quality, to cause 181 performance degradation of formed stressor layers；If annealing temperature is too high, if annealing time is too long, meeting Cause Doped ions diffusion in lightly doped district 120 and static discharge doped region 160 excessively violent, due to lightly doped district 120 Close to the channel region of formed semiconductor structure, therefore Doped ions diffusion excessively can acutely draw in lightly doped district 120 The deterioration for playing short-channel effect, influences the performance of formed semiconductor structure, due to Doped ions in static discharge doped region 160 Type and Doped ions in follow-up formed source and drain doping area type also on the contrary, therefore being mixed in static discharge doped region 160 Heteroion diffusion excessively can acutely make the transoid ion in static discharge doped region 160 influence formed source and drain doping area Performance, to cause formed semiconductor structure performance degradation.
So in the present embodiment, the fin 101 to being formed with lightly doped district 120 and static discharge doped region 160 carries out the In the step of one annealing 170, annealing temperature is within the scope of 950 DEG C to 1100 DEG C.
In addition, being carried out at the first annealing to the fin 101 for being formed with lightly doped district 120 and static discharge doped region 160 After reason 170, before forming stressor layers 181 in the opening 130, in the present embodiment, as shown in fig. 7, the forming method Further include：The second etching processing 132 is carried out, some materials of opening 130 side walls and bottom are removed.
With the reduction of device size, the size of fin 101 also reduces therewith.The reduction of 101 size of fin, can influence institute The repair of 170 pairs of 101 lattice damages of the fin of the first annealing is stated, therefore, second etching processing 132 is used for The some materials for removing opening 130 side walls and bottom, with removal, there are the materials of lattice damage, to be the stressor layers 181 formation provides the growing surface of high quality.
Specifically, in order to reduce second etching processing 132 to damage caused by the fin 101, to the opening 130 side walls and bottom carry out the step of the second etching 132 and include：Second etching processing 132 is carried out by dry method mode.
It should be noted that in the step of carrying out second etching 132,130 side walls of the opening and bottom material are removed The thickness of material should not it is too big also should not be too small.
In the step of carrying out second etching 132, if removal 130 side walls of the opening and the thickness of base material are too It is small, then 132 removal of the second etching can be influenced there are the effect of lattice damage, and 130 bottom and side wall surfaces of opening can remain There is more lattice damage, provides good growing surface to be formed for stressor layers 181, influence the stressor layers 181 Quality；If the thickness for removing 130 side walls of the opening and base material is too big, it will cause waste of material, increase technique Difficulty, but also can make subsequently to be formed by the reduction of the distance between source and drain doping area and the static discharge doped region 160, shadow The performance for ringing formed source and drain doping area, to cause formed semiconductor structure performance degradation.Specifically, in the present embodiment, The step of carrying out the second etching processing 132 include：The second etching processing 132 is carried out, 130 side walls of the opening and bottom are removed The material of 10nm to 20nm thickness.
It with reference to figure 8, is formed after stressor layers 181, carrying out source and drain injection 182 to the stressor layers 181 forms the source and drain Doped region.
The effect of the source and drain injection 182 is to inject Doped ions into the stressor layers 181, is mixed with forming the source and drain Miscellaneous area；The source and drain doping area is used to form source region or the drain region of semiconductor structure.
Specifically, in the present embodiment, formed semiconductor structure is N-type transistor, therefore is carried out to the stressor layers 181 In the step of source and drain injection 182, injection ion is P, and in 3KeV to 10KeV ranges, implantation dosage exists Implantation Energy 1.0E15atom/cm2To 5.0E15atom/cm2In range.
In other embodiments of the invention, when formed semiconductor structure is P-type transistor, to described because processing carries out source and drain In the step of injection, injection ion is B, and Implantation Energy is in 1KeV to 5KeV ranges, and implantation dosage is in 1.0E15atom/cm2 To 5.0E15atom/cm2In range.
As shown in figure 9, after carrying out source and drain injection 182 to the stressor layers 181, the forming method further includes：Into The annealing of row second 183, to activate the Doped ions in the source and drain doping area.
Second annealing 183 for making Doped ions relaxation in the source and drain doping area to the position of lattice, To activate the Doped ions in the source and drain doping area.
Since static discharge injects advance of 150 (as shown in Figure 5) in the stressor layers 181 and the formation of source and drain doping area Row, therefore static discharge injection 150 will not cause lattice damage, Neng Gouyou to the stressor layers 181 and source and drain doping area Effect improves the quality of formed stressor layers 181, reduces the stress release of stressor layers 181 during second annealing 183, The performance for being conducive to improve formed stressor layers 181, is conducive to the performance for improving formed semiconductor structure.
Specifically, the step of carrying out the second annealing 183 includes：It is carried out at the second annealing by way of spike annealing Reason 183.
It should be noted that carry out it is described second annealing 183 the step of in, annealing temperature should not it is too high also should not be too It is low, annealing time it is unsuitable it is too long also should not be too short.
In the step of carrying out second annealing 183, if annealing temperature is too low, if annealing time is too short, meeting The activation for influencing Doped ions in the source and drain doping area causes to be formed to influence the performance in formed source and drain doping area The degeneration of semiconductor structure performance；If annealing temperature is too high, if annealing time is too long, process risk, Ke Nengzao will increase At unnecessary damage, to influence to form the yield of the semiconductor structure.So in the present embodiment, pass through spike annealing In the step of carrying out the second annealing 183, annealing temperature is within the scope of 1000 DEG C to 1100 DEG C.
In addition, in other embodiments of the invention, the step of carrying out the second annealing, includes：By way of laser annealing Carry out the second annealing.Specifically, in the step of carrying out the second annealing by way of laser annealing, annealing temperature exists Within the scope of 1200 DEG C to 1300 DEG C
Correspondingly, the present invention also provides a kind of semiconductor structures.
With reference to figure 5, the cross-sectional view of one embodiment of semiconductor structure of the present invention is shown.
The semiconductor structure includes：Substrate 100 has fin 101 on the substrate 100；On the fin 101 Gate structure 110, the gate structure 110 is across the fin 101 and covering 101 atop part of fin and part side The surface of wall；Opening 130 in 110 both sides fin 101 of the gate structure；Positioned at 130 lower section fins 101 of the opening Interior static discharge doped region 160, the static discharge doped region 160 is interior to have first kind ion.
It should be noted that there are two non-conterminous N-type transistors for the tool of semiconductor structure described in the present embodiment.The present invention In other embodiment, the semiconductor structure can be also used for being formed other semiconductor structures such as P-type transistor, or can be with It is used to form adjacent semiconductor structure, the present invention should not be limited with this.
The substrate 100 is for providing technological operation platform.
In the present embodiment, the material of the substrate 100 is monocrystalline silicon.In other embodiments of the invention, the substrate may be used also Be multicrystalline silicon substrate, amorphous silicon substrate or germanium silicon substrate, carbon silicon substrate, silicon-on-insulator substrate, germanium substrate on insulator, Glass substrate or III-V compound substrate, such as gallium nitride substrate or gallium arsenide substrate etc..The material of the substrate can To choose the material for being suitable for process requirements or being easily integrated.
The fin 101 is used to provide the raceway groove of the fin formula field effect transistor.
In the present embodiment, the material identical of the material of the fin 101 and the substrate 100 is all monocrystalline silicon.The present invention In other embodiment, the material of the fin can also be different from the material of the substrate, can be selected from germanium, germanium silicon, carbon silicon or GaAs etc. is suitable for forming the material of fin.
In the present embodiment, the semiconductor structure further includes：Expose the separation layer on substrate 100 positioned at the fin 101 (not indicated in figure), the separation layer top is less than the top of the fin 101 and the part table of covering 101 side wall of fin Face.
The separation layer is for realizing the electric isolution between adjacent fin 101 and between adjacent semiconductor constructs.This reality It applies in example, the material of the separation layer is silica.In other embodiments of the invention, the material of the separation layer can also be nitrogen The materials such as SiClx or silicon oxynitride.
The gate structure 110 is used for shield portions fin, and the source and drain doping area is avoided to be in direct contact.
In the present embodiment, the gate structure 110 is pseudo- grid structure, therefore the gate structure 110 is additionally operable to be described The gate structure of semiconductor structure takes up space position.In other embodiments of the invention, the gate structure can also be institute's shape At the actual gate structure of semiconductor structure, therefore the gate structure 110 is additionally operable to ditch in the formed semiconductor structure of control The conducting in road with block.
In the present embodiment, the gate structure 110 is single layer structure, including the dummy grid of polycrystalline silicon material (do not mark in figure Show).In other embodiments of the invention, the material of the dummy grid can also be silica, silicon nitride, silicon oxynitride, silicon carbide, The other materials such as carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.In other of the invention embodiments, dummy gate structure can be with For laminated construction, including dummy grid and the pseudo- oxide layer on the dummy grid, the material of the puppet oxide layer can be Silica and silicon oxynitride.
It should be noted that the semiconductor structure further includes：Side wall (figure on 110 side wall of the gate structure In do not indicate).The material of the side wall can be silica, silicon nitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride, nitrogen oxidation Silicon, boron nitride or boron carbonitrides, the side wall can be single layer structure or laminated construction.In the present embodiment, the side wall is single The material of layer structure, the side wall is silicon nitride.
The opening 130 is for filling semiconductor material to form the source and drain doping area of the semiconductor structure.
In addition, the presence of the opening 130, additionally it is possible to reduce the height of fin 101 at opening 130.101 height of fin Reduce, can damage of effective minimizing electrostatic electric discharge 160 forming process of doped region to fin 101, be conducive to improve and formed The performance of semiconductor structure.
In the present embodiment, the semiconductor structure is used to form N-type transistor, so the opening 130 is opened for " u "-shaped Mouthful.In other embodiments of the invention, the semiconductor structure can be also used for forming P-type transistor, the shape of the opening It can be " ∑ " shape.
It should be noted that the depth of the opening 130 should not be too large it is also unsuitable too small.
If the depth of the opening 130 is too small, the height of remaining fin 101 is excessive, is unfavorable for minimizing electrostatic electric discharge Damage of 160 forming process of doped region to fin 101；If the depth of the opening 130 is too big, the height of remaining fin 101 It spends small, 160 depth of static discharge doped region can be caused excessively shallow, and influence source and drain doping area property in the semiconductor structure Can, cause the degeneration of the semiconductor structure performance.So in the present embodiment, the depth of the opening 130 is in 15nm to 40nm In range.
The static discharge doped region 160 is used to form PN junction between the source and drain doping area of the semiconductor structure, from And the purpose realized and adjust junction breakdown voltage, adjust electro-static discharging device trigger voltage.
The static discharge doped region 160 is located in the fin of 130 lower section of the opening, therefore the static discharge adulterates In 160 forming process of area, the height of the fin 101 is relatively low.The reduction of 101 height of fin can effectively reduce described quiet The formation process of discharge of electricity doped region 160 is to damage caused by the fin 101.
And since the static discharge doped region 160 is formed in the stressor layers of the semiconductor structure and source and drain doping area It is formed before, therefore the formation process of the static discharge doped region 160 will not cause the stressor layers and source and drain doping area Lattice damage can effectively improve the quality of formed stressor layers, reduce what stressor layers in source and drain doping area forming process discharged Stress is conducive to the performance for improving stressor layers, is conducive to the performance for improving semiconductor structure.
Specifically, when the semiconductor structure is NMOS device, Doped ions are B in the static discharge doped region, are mixed Heteroion concentration is in 1.0E18atom/cm3To 5.0E19atom/cm3In range；When the semiconductor structure is PMOS device, institute It is P to state Doped ions in static discharge doped region, and Doped ions concentration is in 1.0E18atom/cm3To 5.0E19atom/cm3Range It is interior.
It should be noted that in order to inhibit the short-channel effect in the semiconductor structure, the semiconductor structure also to wrap It includes：Lightly doped district 120 in 110 both sides fin 101 of gate structure, have in the lightly doped district 120 Second Type from Son, the lightly doped district 120 are located on the static discharge doped region 160.
The lightly doped district 120 is used to be formed shallow junction in semiconductor structure to inhibit short-channel effect, and inhibits raceway groove Leakage current effects.
In the present embodiment, formed semiconductor structure is used to form N-type transistor, so tool in the lightly doped district 120 There is n-type doping ion；In other embodiments of the invention, the semiconductor structure is used to form P-type transistor, the lightly doped district There are p-type Doped ions in 120.
Since the lightly doped district 120 is used to form shallow junction, the lightly doped district 120 is located at close to the semiconductor The position of structure channel region, so the lightly doped district 120 is located on the static discharge doped region 160.
It should be noted that the semiconductor structure is used to form N-type transistor, so in the follow-up semiconductor structure Opening 130 can be filled semi-conducting material to form the source and drain doping area of the N-type transistor.Before specific technical solution reference The embodiment of method for forming semiconductor structure of the present invention is stated, details are not described herein by the present invention.
To sum up, it in technical solution of the present invention, is formed after opening in the fin of gate structure both sides；To being formed with opening Fin carry out static discharge injection, in the fin formed with first kind ion static discharge doped region；In shape After static discharge doped region, stressor layers and source and drain doping area are formed in the opening.Since static discharge is infused in institute It states stressor layers and source and drain doping area forms and carries out before, therefore static discharge injection will not mix the stressor layers and source and drain Miscellaneous area causes lattice damage, can effectively improve the quality of formed stressor layers, reduces stress in source and drain doping area forming process The stress of layer release, is conducive to the performance for improving formed stressor layers, is conducive to the performance for improving formed semiconductor structure.And And in alternative of the present invention, formed after gate structure on the fin, the shape in the fin of the gate structure both sides Before opening, lightly doped drain injection is carried out to the fin of the gate structure both sides, lightly doped district is formed in the fin； And after carrying out static discharge injection to the fin for being formed with opening, formed before stressor layers in the opening, Fin to being formed with lightly doped district and static discharge doped region makes annealing treatment.The annealing is both used to activate described Doped ions in lightly doped district are additionally operable to the damage that the fin is subject to after repairing static discharge injection and injection being lightly doped Wound, the formation for the follow-up stressor layers provide good growing surface；This way effectively can either be improved to be formed and be answered The quality of power layer, and the number that heating process carries out in the semiconductor forming method can be reduced, be conducive to improve being formed The performance of semiconductor structure.In addition, in alternative of the present invention, the forming method further includes：To be formed with lightly doped district and It after the fin of static discharge doped region is made annealing treatment, is formed before stressor layers in the opening, carries out the second etching Processing, removes some materials of the opening sidewalls and bottom.Second etching is repaiied for removing not completing in annealing The material of multiple opening sidewalls and bottom, to which raising forms the quality of the open bottom and side wall during stressor layers, to answer The formation of power layer improves good growing surface, is conducive to the quality for improving formed stressor layers, is conducive to improve and described partly lead The performance of body structure.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the range of restriction.

Claims (20)

1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, there is fin on the substrate；
Form gate structure on the fin, the gate structure across the fin and the covering fin atop part and The surface of partial sidewall；
The first etching processing is carried out, forms opening in the fin of the gate structure both sides；
Static discharge injection is carried out to the fin for being formed with opening, forms static discharge doped region, institute in the fin Stating has first kind ion in static discharge doped region；
Stressor layers are formed in the opening, to form the source and drain doping area being located on the static discharge doped region, the source Leaking has Second Type ion in doped region.
2. forming method as described in claim 1, which is characterized in that carry out the first etching processing the step of include：Carry out the One etching processing forms opening of the depth in 15nm to 40nm ranges in the fin of the gate structure both sides.
3. forming method as described in claim 1, which is characterized in that carry out the first etching processing the step of include：By dry Method mode carries out first etching processing.
4. forming method as described in claim 1, which is characterized in that carry out static discharge to the fin for being formed with opening In the step of injection, when the semiconductor structure is NMOS device, technological parameter is：Injection ion is B, and Implantation Energy is in 3KeV Into 15KeV, implantation dosage is in 1.0E12atom/cm2To 2.0E15atom/cm2In range；
When the semiconductor structure is PMOS device, technological parameter is：Injection ion is P, and Implantation Energy is in 5KeV to 30KeV models In enclosing, implantation dosage is in 1.0E12atom/cm2To 2.0E15atom/cm2In range.
5. forming method as described in claim 1, which is characterized in that the forming method further includes：
It is formed after gate structure, is formed before opening in the fin of the gate structure both sides, to institute on the fin The fin for stating gate structure both sides carries out lightly doped drain injection, forms lightly doped district in the fin, in the lightly doped district With Second Type ion；
Include to the step of fin progress static discharge injection for being formed with opening：To the fin for being formed with opening into Row static discharge injects, and the static discharge doped region is formed in the fin under the lightly doped district；
After carrying out static discharge injection to the fin for being formed with opening, formed before stressor layers in the opening, it is right The fin for being formed with lightly doped district and static discharge doped region carries out the first annealing.
6. forming method as claimed in claim 5, which is characterized in that being formed with lightly doped district and static discharge doped region Fin carry out first annealing the step of include：It is mixed by way of spike annealing being formed with lightly doped district and static discharge The fin in miscellaneous area carries out the first annealing.
7. such as forming method described in claim 5 or 6, which is characterized in that adulterated to being formed with lightly doped district and static discharge The fin in area carried out in the step of the first annealing, and annealing temperature is within the scope of 950 DEG C to 1100 DEG C.
8. forming method as claimed in claim 5, which is characterized in that the forming method further includes：It is lightly doped to being formed with It after the fin of area and static discharge doped region carries out the first annealing, is formed before stressor layers, is carried out in the opening Second etching processing removes some materials of the opening sidewalls and bottom.
9. forming method as claimed in claim 8, which is characterized in that carry out the second etching processing the step of include：Carry out the Two etching processings remove the material of the opening sidewalls and bottom 10nm to 20nm thickness.
10. forming method as claimed in claim 8, which is characterized in that carry out the second etching to the opening sidewalls and bottom The step of include：Second etching processing is carried out by dry method mode.
11. forming method as described in claim 1, which is characterized in that form the source being located on the static discharge doped region Leak doped region the step of include：
Into the opening, filling semiconductor material, forms stressor layers in the opening；
Source and drain injection is carried out to the stressor layers, to form the source and drain doping area on the static discharge doped region.
12. forming method as claimed in claim 11, which is characterized in that into the opening the step of filling semiconductor material Including：By way of epitaxial growth into the opening filling semiconductor material.
13. forming method as claimed in claim 11, which is characterized in that the step of carrying out source and drain injection to the stressor layers In,
When the semiconductor structure is PMOS device, technological parameter is：Injection ion is B, and Implantation Energy is in 1KeV to 5KeV models In enclosing, implantation dosage is in 1.0E15atom/cm2To 5.0E15atom/cm2In range；
When the semiconductor structure is NMOS device, injection ion is P, and Implantation Energy is in 3KeV to 10KeV ranges, injectant Amount is in 1.0E15atom/cm2To 5.0E15atom/cm2In range.
14. forming method as claimed in claim 11, which is characterized in that after carrying out source and drain injection to the stressor layers, institute Stating forming method further includes：The second annealing is carried out, to activate the Doped ions in the source and drain doping area.
15. forming method as claimed in claim 14, which is characterized in that carry out second annealing the step of include：Pass through Spike annealing or the mode of laser annealing carry out the second annealing.
16. forming method as claimed in claim 15, which is characterized in that carry out the step of the second annealing by spike annealing In rapid, annealing temperature is within the scope of 1000 DEG C to 1100 DEG C；
In the step of carrying out the second annealing by way of laser annealing, annealing temperature is in 1200 DEG C to 1300 DEG C ranges It is interior.
17. a kind of semiconductor structure, which is characterized in that including：
Substrate has fin on the substrate；
Gate structure on the fin, the gate structure across the fin and the covering fin atop part and The surface of partial sidewall；
Opening in the fin of the gate structure both sides；
Static discharge doped region below the opening in fin, have in the static discharge doped region first kind from Son.
18. semiconductor structure as claimed in claim 17, which is characterized in that the depth of the opening is in 15nm to 40nm ranges It is interior.
19. semiconductor structure as claimed in claim 17, which is characterized in that when the semiconductor structure is NMOS device, institute It is B to state Doped ions in static discharge doped region, and Doped ions concentration is in 1.0E18atom/cm3To 5.0E19atom/cm3Range It is interior；
When the semiconductor structure is PMOS device, Doped ions are P in the static discharge doped region, and Doped ions concentration exists 1.0E18atom/cm3To 5.0E19atom/cm3In range.
20. semiconductor structure as claimed in claim 17, which is characterized in that the semiconductor structure further includes：Positioned at grid Lightly doped district in the fin of structure both sides, the lightly doped district is interior, and there is Second Type ion, the lightly doped district to be located at described On static discharge doped region.
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CN104078360A (en) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 Method for producing MOS transistor
CN105529266A (en) * 2014-10-21 2016-04-27 上海华力微电子有限公司 Improvement method for dislocation defects of embedded silicon-germanium epitaxy
CN106206315A (en) * 2016-07-18 2016-12-07 中国科学院微电子研究所 Semiconductor device and manufacture method thereof and include the electronic equipment of this device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080132019A1 (en) * 2006-12-05 2008-06-05 Keh-Chiang Ku Short channel effect engineering in MOS device using epitaxially carbon-doped silicon
CN104078360A (en) * 2013-03-28 2014-10-01 中芯国际集成电路制造(上海)有限公司 Method for producing MOS transistor
CN105529266A (en) * 2014-10-21 2016-04-27 上海华力微电子有限公司 Improvement method for dislocation defects of embedded silicon-germanium epitaxy
CN106206315A (en) * 2016-07-18 2016-12-07 中国科学院微电子研究所 Semiconductor device and manufacture method thereof and include the electronic equipment of this device

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