CN109087859A - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN109087859A CN109087859A CN201710444292.1A CN201710444292A CN109087859A CN 109087859 A CN109087859 A CN 109087859A CN 201710444292 A CN201710444292 A CN 201710444292A CN 109087859 A CN109087859 A CN 109087859A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 124
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 238000000034 method Methods 0.000 claims abstract description 56
- 238000009792 diffusion process Methods 0.000 claims abstract description 54
- 230000003139 buffering effect Effects 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims description 37
- 239000007924 injection Substances 0.000 claims description 37
- 238000005468 ion implantation Methods 0.000 claims description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 22
- 238000010884 ion-beam technique Methods 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000008859 change Effects 0.000 claims description 3
- 229940090044 injection Drugs 0.000 claims 5
- 239000012535 impurity Substances 0.000 abstract description 32
- 230000000694 effects Effects 0.000 abstract description 21
- 238000009826 distribution Methods 0.000 abstract description 19
- 238000000137 annealing Methods 0.000 abstract description 14
- 230000008569 process Effects 0.000 abstract description 14
- 230000035755 proliferation Effects 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 description 79
- 239000000463 material Substances 0.000 description 22
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 10
- 239000003292 glue Substances 0.000 description 10
- 230000003287 optical effect Effects 0.000 description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 239000000470 constituent Substances 0.000 description 8
- 239000012212 insulator Substances 0.000 description 8
- 229910044991 metal oxide Inorganic materials 0.000 description 7
- 150000004706 metal oxides Chemical class 0.000 description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 230000007547 defect Effects 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 6
- -1 one of nitrogen (N) Chemical class 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
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- 238000010586 diagram Methods 0.000 description 3
- 125000005843 halogen group Chemical group 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
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- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical group [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000010416 ion conductor Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 238000003801 milling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, which comprises provides semiconductor substrate, is formed with gate stack structure on semiconductor substrate surface；Semiconductor substrate is performed etching using gate stack structure as exposure mask, to form groove in the semiconductor substrate of gate stack structure two sides；The buffering diffusion layer for surrounding groove is formed in at least side of gate stack structure；Source electrode and drain electrode is formed in groove.Using method of the invention, buffering diffusion layer is formed before forming source electrode and drain electrode, the diffusion that impurity in diffusion layer is buffered in subsequent annealing process drives the impurity diffusion in source electrode and drain electrode region, keep the Impurity Distribution in source electrode and drain electrode region more uniform, reduce the field distribution gradient of the PN junction in source electrode and drain electrode region, the horizontal proliferation of impurity can also be avoided simultaneously, while controlling lateral short-channel effect, the junction capacity and junction leakage for reducing source electrode and drain electrode region, improve semiconductor devices yield and performance.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacturing method of semiconductor devices.
Background technique
With Metal-oxide-semicondutor (metal oxide semiconductor, MOS) FET device
The continuous reduction of characteristic size the control of the channel length effective enough of MOS device is become in its manufacturing process
It is more challenging.For this purpose, core devices can be improved using the method for forming ultra-shallow junctions and abrupt junction in MOS device
Short-channel effect.However, how to inhibit short-channel effect (Short during forming ultra-shallow junctions and abrupt junction
Channel Effect, SCE) and promote between the performance of MOS device that find more reasonable equilibrium point be also extremely negative challenge
Task.
In order to further enhance the performance of MOS device, those skilled in the art are dedicated to developing the higher semiconductor of performance
Device, fin formula field effect transistor (Fin Field-Effect Transistor, FinFET) is exactly one such.
FinFET is the advanced semiconductor device for 22nm and following process node, can effectively control semiconductor devices in proportion
The short-channel effect for being difficult to overcome caused by reducing.However, even for FinFET, the performance and control short channel effect of device
It is balanced also as increasing challenge between answering.In order to overcome this problem, the prior art is infused by pre-amorphous ion
Enter, stress technique etc. comes so that (LDD) is lightly doped and halo (Halo) injection forms more shallow ultra-shallow junctions, to improve the property of device
Energy.However, these methods can bring the increase of junction leakage while improving short-channel effect, and then lead to semiconductor device
The reduction of part performance.
The purpose of the present invention is to provide a kind of manufacturing methods of semiconductor devices, to solve the above technical problems.
Summary of the invention
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.Summary of the invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection scope for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, which comprises mentions
For semiconductor substrate, gate stack structure is formed on the semiconductor substrate surface；Using the gate stack structure as exposure mask
The semiconductor substrate is performed etching, to form groove in the semiconductor substrate of the gate stack structure two sides；Institute
At least side for stating gate stack structure forms the buffering diffusion layer for surrounding the groove；Source electrode and leakage are formed in the groove
Pole.
Further, the buffering diffusion layer includes the symmetrical buffering diffusion formed in the gate stack structure two sides
Layer.
Further, the method for forming the symmetrical buffering diffusion layer includes: to execute the first ion implantation technology, in institute
It states in the semiconductor substrate of the bottom portion of groove of gate stack structure two sides and forms the first ion implanted region；Execute the second ion
Injection technology, in the semiconductor substrate at first ion implanted region surface and the recess sidewall formed second from
Sub- injection region.
Further, the buffering diffusion layer includes only expanding in the asymmetric buffering that the gate stack structure side is formed
Dissipate layer.
Further, the method for forming the asymmetric buffering diffusion layer includes: in the gate stack structure side
The semiconductor substrate and part the gate stack structure surface form patterned photoresist layer；It is with the photoresist layer
Exposure mask executes the first ion implantation technology, in the semiconductor substrate of the bottom portion of groove of the gate stack structure side
The first ion implanted region of middle formation；The second ion implantation technology is executed, on first ion implanted region surface and described
The second ion implanted region is formed in semiconductor substrate at recess sidewall；Remove the photoresist layer.
Further, first ion implantation technology is vertical ion injection.
Further, the injection ion of first ion implantation technology includes silicon.
Further, in first ion implantation technology, the energy of injection ion silicon is 1KeV-5KeV, and dosage is
1e13-5e13/cm2。
Further, second ion implantation technology is angle-tilt ion injection.
Further, in second ion implantation technology, the direction of ion beam and semiconductor substrate surface normal direction
In 0-45 ° of angle, the angle between the direction of ion beam and the semiconductor substrate surface normal direction the angle ranging from.
Further, the injection ion of second ion implantation technology includes nitrogen.
Further, the injection ion of second ion implantation technology further includes carbon.
Further, in second ion implantation technology, the energy for injecting ionic nitrogen is 1KeV-5KeV, and dosage is
1e14-8e14/cm2。
Further, in second ion implantation technology, the energy of injection ion carbon is 1KeV-5KeV, and dosage is
1e14-8e14/cm2。
Further, the semiconductor devices includes FinFET.
In conclusion according to the method for the present invention, buffering diffusion layer is formed before forming source electrode and drain electrode, subsequent
The diffusion that impurity in diffusion layer is buffered in annealing process drives the impurity diffusion in source electrode and drain electrode region, makes source electrode and drain electrode region
Impurity Distribution it is more uniform, reduce the field distribution gradient of the PN junction in source electrode and drain electrode region, while impurity can also be avoided
Horizontal proliferation reduce the junction capacity and junction leakage in source electrode and drain electrode region while controlling lateral short-channel effect,
Improve semiconductor devices yield and performance.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 is the technical process schematic diagram of the semiconductor devices of the embodiment of the present invention；
Fig. 2A -2E is the semiconductor devices obtained respectively the step of successively implementation according to the method for the embodiment of the present invention one
Schematic cross sectional view；
Fig. 3 A-3F is the semiconductor devices obtained respectively the step of successively implementation according to the method for the embodiment of the present invention two
Schematic cross sectional view.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Semiconductor devices manufacturing method.Obviously, the technical staff that execution of the invention is not limited to semiconductor field is familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can be with
With other embodiments.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or their combination.
The prior art optimizes lightly doped district and halo doping characteristic by pre-amorphous ion implanting, stress technique etc.,
To improve the performance of device.However, these methods can bring the increase of junction leakage while improving short-channel effect, into
And lead to the reduction of performance of semiconductor device.
Exemplary embodiment
Presence in view of the above problems, the invention proposes a kind of manufacturing methods of semiconductor devices, as shown in Figure 1, its
Including following key step:
In step s101, semiconductor substrate is provided, is formed with gate stack structure on the semiconductor substrate surface；
In step s 102, the semiconductor substrate is performed etching using the gate stack structure as exposure mask, in institute
It states in the semiconductor substrate of gate stack structure two sides and forms groove；
In step s 103, the buffering diffusion of the encirclement groove is formed in at least side of the gate stack structure
Layer；
In step S104, source electrode and drain electrode is formed in the groove.
According to the method for the present invention, buffering diffusion layer is formed before forming source electrode and drain electrode, in subsequent annealing process
The diffusion of impurity drives the impurity diffusion in source electrode and drain electrode region in middle buffering diffusion layer, makes the impurity point in source electrode and drain electrode region
Cloth is more uniform, reduces the field distribution gradient of the PN junction in source electrode and drain electrode region, while the lateral of impurity can also be avoided to expand
It dissipates, while controlling lateral short-channel effect, reduces the junction capacity and junction leakage in source electrode and drain electrode region, improve half
Conductor device yield and performance.
Embodiment one
With p-type Metal-Oxide Semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-
Effect Transistor, MOSFET) for, referring to Fig. 2A-Fig. 2 E, according to embodiments of the present invention one side is shown
The schematic cross sectional view for the semiconductor devices that the step of method is successively implemented obtains respectively.
Firstly, as shown in Figure 2 A, providing semiconductor substrate 201, being formed with grid pile on 201 surface of semiconductor substrate
Stack structure 202, then using lightly doped technique (Lightly Doped Drain, LDD) to facing in the semiconductor substrate 201
The region of the nearly gate stack structure 202 carries out ion implanting and anneals, to close on the grid in semiconductor substrate 201
Lightly doped drain (LDD) ion implanted region (not shown) is formed in the region of stacked structure 202.
Further, the constituent material of the semiconductor substrate 201 can use undoped monocrystalline silicon, doped with impurity
Silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator for monocrystalline silicon, silicon-on-insulator (SOI)
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body can also use gallium nitride (GaN), aluminium nitride (AlN), nitrogen
Change indium (InN), GaAs (GaAS), zinc oxide (ZnO), silicon carbide (SiC) etc., in the present embodiment, the semiconductor substrate
Single crystal silicon material is selected to constitute.Further, 201 two sides of semiconductor substrate are formed with fleet plough groove isolation structure (STI) 203, in institute
Buried layer, well structure etc. can also be formed with by stating in semiconductor substrate, to put it more simply, being omitted in diagram.
As an example, the gate stack structure 202 includes gate dielectric 202a, the grid being laminated from bottom to top
Material layer 202b, and the side wall 202c ' of covering the gate dielectric 202a and gate material layers 202b side wall.The grid
Dielectric layer 202a includes oxide skin(coating), such as silica (SiO2) layer.Gate material layers 202b includes polysilicon layer, metal
One of layer, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer are a variety of, wherein metal
The constituent material of layer can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes titanium nitride (TiN) layer；It leads
Conductive metal oxide skin(coating) includes yttrium oxide (IrO2) layer；Metal silicide layer includes titanium silicide (TiSi) layer.Side wall 202c ''s
The preferred silicon nitride of constituent material.Specific formation process is referring to the prior art, and details are not described herein.
Optionally, the semiconductor devices includes FinFET.201 surface of semiconductor substrate is formed with fin (Fin),
The gate stack structure 202 is centered around the two sides and top of fin.Specifically, fin is formed by Patternized technique, shape
At process are as follows: deposition mask layer on a semiconductor substrate first, after coating optical resistance glue layer on mask layer, using with fin-shaped ditch
Develop after the light shield exposure coating optical resistance glue layer of road structure, forms the optical resistance glue layer of fin-shaped channel pattern in optical resistance glue layer, so
Afterwards using the optical resistance glue layer with fin-shaped channel pattern as exposure mask, etching mask layer obtains the mask layer with fin-shaped channel pattern；
Then to be to block with the mask layer of fin-shaped channel pattern, etch semiconductor substrates obtain the lining with fin-shaped channel pattern
Bottom removes remaining mask layer；The fin-shaped channel is performed etching using gate stack structure as exposure mask, to expose semiconductor lining
Bottom.
Illustratively, the ionic type of the LDD injection is determined according to by the electrical property of semiconductor devices to be formed, at this
In embodiment, the device of formation is PMOSFET device, and the foreign ion of injection is boron.According to the concentration of required foreign ion,
Ion implantation technology can be completed with one or more steps.If the device formed is NMOSFET device, mixed in LDD injection technology
The foreign ion entered is one of phosphorus, arsenic, antimony, bismuth or combination.
Further, after completing the ion implanting, on the incident ion and semiconductor lattice in order to eliminate high-energy
Atomic collision, lattice atoms are subjected to displacement and cause a large amount of vacancy, and the device is annealed at a certain temperature, with
Restore the structure of crystal and eliminates defect.
Next, as shown in Figure 2 B, widening the side wall 202c ', to form side wall 202c, then with the grid
Pole stacked structure 202 is that exposure mask performs etching the semiconductor substrate 201, in 202 two sides of gate stack structure
Groove 204 is formed in semiconductor substrate 201.
Further, the purpose widened the side wall is further strengthened between source/drain and gate stack structure
Buffer action.The processing step for widening the side wall 202c ' include: formed in semiconductor substrate 201 be completely covered it is described
Then the spacer material layer of gate stack structure 202, the preferred silicon nitride of constituent material etch side wall using sidewall etch technique
Material layer, to form side wall 202c.Concrete technology is referring to the prior art, and details are not described herein.
The semiconductor substrate 201 is performed etching using isotropic dry method etch technology, dry method etch technology packet
Include but be not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting carry out, concrete technology
Referring to the prior art, details are not described herein.
Then, as shown in Figure 2 C, the first ion implantation technology is executed, in the institute of 202 two sides of gate stack structure
It states and forms the first ion implanted region 205 in the semiconductor substrate 201 of bottom portion of groove.
Wherein, the injection ion of the first ion implanting includes silicon (Si), and the defect that ion implanting is formed can be in postorder
Annealing process in be repaired.Further, first ion implanting is the ion implanting perpendicular to semiconductor substrate, and energy is
1KeV-5KeV, dosage 1e13-5e13/cm2, injection depth is 1nm-20nm.Further, the injection of first ion implanting
Number can be primary, or repeatedly.
Further, the first ion implanted region of formation can be such that the diffusion junction depth in source electrode and drain electrode region adds to a certain extent
Deep, the annealing process after forming source electrode and drain electrode region can repair the first ion implanting and be formed by defect, and these are miscellaneous
The diffusion of matter ion will drive the diffusion of source electrode and drain electrode region impurity, to make the Impurity Distribution in source electrode and drain electrode region more
Uniformly, the field distribution gradient of the PN junction in source electrode and drain electrode region is advantageously reduced, and then reduces junction capacity and junction leakage.
Then, as shown in Figure 2 D, execute the second ion implantation technology, with 205 surface of the first ion implanted region with
And the second ion implanted region 206 is formed in the semiconductor substrate 201 at the recess sidewall.
Wherein, the injection ion of the second ion implanting is lightweight ion, such as one of nitrogen (N), carbon (N), boron (B) or group
It closes, the preferably combination of nitrogen and carbon.Further, the energy of the Nitrogen ion of injection is 1KeV-5KeV, dosage 1e14-8e14/cm2；
The energy of the carbon ion of injection is 1KeV-5KeV, dosage 1e14-8e14/cm2。
Further, the second ion implanting is angle-tilt ion injection, the direction and semiconductor substrate surface normal side of ion beam
It is the angle between the direction and the semiconductor substrate surface normal direction of ion beam, i.e. ion beam can to being in 0-45 ° of angle
To be injected centered on semiconductor substrate surface normal direction to the inclined direction in two sides.Optionally, a kind of angled manner be to
Left and right sides inclination, another angled manner are the inclination of two sides forwards, backwards, and preferably two sides tilt forwards, backwards, to put it more simply, Fig. 2 D
In the case where being tilted to the left centered on semiconductor substrate surface normal direction, is only shown.Further, the second ion note
The injection number entered can be primary, or repeatedly.
Further, the impurity that the second ion implanted region 206 of formation can prevent the first ion implantation technology from being injected exists
Horizontal proliferation occurs along recess sidewall when annealing, leads to Punchthrough and short-channel effect.
First ion implanted region 205 and the second ion implanted region 206 constitute buffering diffusion layer, buffer diffusion layer in annealing
In the diffusion of foreign ion will drive the diffusion of source electrode and drain electrode region impurity so that the Impurity Distribution in source electrode and drain electrode region
It is more uniform, the field distribution gradient of the PN junction in source electrode and drain electrode region is reduced, while controlling lateral short-channel effect, drop
The low junction capacity and junction leakage in source electrode and drain electrode region.
Finally, as shown in Figure 2 E, buffering diffusion layer surface in the groove is epitaxially-formed source electrode 207 and drain electrode
208, then anneal.
Wherein, the source electrode and drain electrode is served as a contrast as heavy-doped source drain region, the surface of the source electrode and drain electrode higher than semiconductor
Bottom surface.For PMOSFET, the material as source electrode and drain electrode is germanium silicon layer (SiGe), further, it is also possible in germanium silicon
Suitable boron element (such as B or BF2) is adulterated, to improve performance of semiconductor device, further, the germanium silicon layer is embedded germanium silicon
Layer.For NMOSFET, the material as source electrode and drain electrode is carbon silicon layer (SiC).Channel application is answered using the epitaxial layer
Power, to improve the mobility of carrier.
It can produce more trench edges regions for effectively inhibiting shallowly laterally to tie since source electrode and drain electrode covers, this can be with
More powerful driving current is generated, while improving short-channel effect and inverse short-channel effect.Additionally, due in the gate stack
Symmetrical buffering diffusion layer, the expansion of the foreign ion in annealing in buffering diffusion layer are formed in the semiconductor substrate of structure two sides
Breaking up drives the diffusion of source electrode and drain electrode region impurity, so that the Impurity Distribution in source electrode and drain electrode region is more uniform, reduces source
The field distribution gradient of the PN junction of pole and drain region reduces source electrode and drain electrode while controlling lateral short-channel effect
The junction capacity and junction leakage in region, improve semiconductor devices yield and performance.
Embodiment two
With p-type Metal-Oxide Semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-
Effect Transistor, MOSFET) for, referring to Fig. 3 A- Fig. 3 F, according to embodiments of the present invention two side is shown
The schematic cross sectional view for the semiconductor devices that the step of method is successively implemented obtains respectively.
Firstly, as shown in Figure 3A, providing semiconductor substrate 301, being formed with grid pile on 301 surface of semiconductor substrate
Stack structure 302, then using lightly doped technique (Lightly Doped Drain, LDD) to facing in the semiconductor substrate 301
The region of the nearly gate stack structure 302 carries out ion implanting and anneals, to close on the grid in semiconductor substrate 301
Lightly doped drain (LDD) ion implanted region (not shown) is formed in the region of stacked structure 302.
Further, the constituent material of the semiconductor substrate 301 can use undoped monocrystalline silicon, doped with impurity
Silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI), insulation is laminated on insulator for monocrystalline silicon, silicon-on-insulator (SOI)
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body can also use gallium nitride (GaN), aluminium nitride (AlN), nitrogen
Change indium (InN), GaAs (GaAS), zinc oxide (ZnO), silicon carbide (SiC) etc., in the present embodiment, the semiconductor substrate
Single crystal silicon material is selected to constitute.Further, 301 two sides of semiconductor substrate are formed with fleet plough groove isolation structure (STI) 303, in institute
Buried layer, well structure etc. can also be formed with by stating in semiconductor substrate, to put it more simply, being omitted in diagram.
As an example, the gate stack structure 302 includes gate dielectric 302a, the grid being laminated from bottom to top
Material layer 302b, and the side wall 302c ' of covering the gate dielectric 302a and gate material layers 302b side wall.The grid
Dielectric layer 302a includes oxide skin(coating), such as silica (SiO2) layer.Gate material layers 302b includes polysilicon layer, metal
One of layer, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer are a variety of, wherein metal
The constituent material of layer can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal nitride layer includes titanium nitride (TiN) layer；It leads
Conductive metal oxide skin(coating) includes yttrium oxide (IrO2) layer；Metal silicide layer includes titanium silicide (TiSi) layer.Side wall 302c ''s
The preferred silicon nitride of constituent material.Specific formation process is referring to the prior art, and details are not described herein.
Optionally, the semiconductor devices includes FinFET.301 surface of semiconductor substrate is formed with fin (Fin),
The gate stack structure 302 is centered around the two sides and top of fin.Specifically, fin is formed by Patternized technique, shape
At process are as follows: deposition mask layer on a semiconductor substrate first, after coating optical resistance glue layer on mask layer, using with fin-shaped ditch
Develop after the light shield exposure coating optical resistance glue layer of road structure, forms the optical resistance glue layer of fin-shaped channel pattern in optical resistance glue layer, so
Afterwards using the optical resistance glue layer with fin-shaped channel pattern as exposure mask, etching mask layer obtains the mask layer with fin-shaped channel pattern；
Then to be to block with the mask layer of fin-shaped channel pattern, etch semiconductor substrates obtain the lining with fin-shaped channel pattern
Bottom removes remaining mask layer；The fin-shaped channel is performed etching using gate stack structure as exposure mask, to expose semiconductor lining
Bottom.
Illustratively, the ionic type of the LDD injection is determined according to by the electrical property of semiconductor devices to be formed, at this
In embodiment, the device of formation is PMOSFET device, and the foreign ion of injection is boron.According to the concentration of required foreign ion,
Ion implantation technology can be completed with one or more steps.If the device formed is NMOSFET device, mixed in LDD injection technology
The foreign ion entered is one of phosphorus, arsenic, antimony, bismuth or combination.
Further, after completing the ion implanting, on the incident ion and semiconductor lattice in order to eliminate high-energy
Atomic collision, lattice atoms are subjected to displacement and cause a large amount of vacancy, and the device is annealed at a certain temperature, with
Restore the structure of crystal and eliminates defect.
Next, as shown in Figure 3B, widening the side wall 302c ', to form side wall 302c, then with the grid
Pole stacked structure 302 is that exposure mask performs etching the semiconductor substrate 301, in 302 two sides of gate stack structure
Groove 304 is formed in semiconductor substrate 301.
Further, the purpose widened the side wall is further strengthened between source/drain and gate stack structure
Buffer action.The processing step for widening the side wall 302c ' include: formed in semiconductor substrate 301 be completely covered it is described
Then the spacer material layer of gate stack structure 302, the preferred silicon nitride of constituent material etch side wall using sidewall etch technique
Material layer, to form side wall 302c.Concrete technology is referring to the prior art, and details are not described herein.
The semiconductor substrate 301 is performed etching using isotropic dry method etch technology, dry method etch technology packet
Include but be not limited to: reactive ion etching (RIE), ion beam milling, plasma etching or laser cutting carry out, concrete technology
Referring to the prior art, details are not described herein.
Then, as shown in Figure 3 C, in the semiconductor substrate of the gate stack structure 302 source electrode side to be formed
301 and part 302 surface of gate stack structure form patterned photoresist layer 308.
Further, in subsequent first ion implantation technology and the second ion implantation technology, the photoresist layer 308 can
The semiconductor substrate formation of source electrode side is blocked, so that the first ion implanted region and the second ion implanted region are only in drain electrode side
It is formed.
It should be noted that can also be in semiconductor substrate and the part gate stack structure of drain electrode side to be formed
Surface forms patterned photoresist layer, and the first ion implanted region and the second ion implanted region are only formed in source electrode side at this time.
Then, as shown in Figure 3D, it is exposure mask with the photoresist layer 308, the first ion implantation technology is executed, described
The first ion implanting is formed in the semiconductor substrate 301 of the bottom portion of groove of the source electrode side to be formed of gate stack structure 302
Area 305.
Wherein, the injection ion of the first ion implanting includes silicon (Si), and the defect that ion implanting is formed can be in postorder
Annealing process in be repaired.Further, first ion implanting is the ion implanting perpendicular to semiconductor substrate, and energy is
1KeV-5KeV, dosage 1e13-5e13/cm2, injection depth is 1nm-20nm.Further, the injection of first ion implanting
Number can be primary, or repeatedly.
Further, the first ion implanted region of formation can be such that the diffusion junction depth in source electrode and drain electrode region adds to a certain extent
Deep, the annealing process after forming source electrode and drain electrode region can repair the first ion implanting and be formed by defect, and these are miscellaneous
The diffusion of matter ion will drive the diffusion of source electrode and drain electrode region impurity, to make the Impurity Distribution in source electrode and drain electrode region more
Uniformly, the field distribution gradient of the PN junction in source electrode and drain electrode region is advantageously reduced, and then reduces junction capacity and junction leakage.
Then, as shown in FIGURE 3 E, execute the second ion implantation technology, with 305 surface of the first ion implanted region with
And the second ion implanted region 306 is formed in the semiconductor substrate 301 at the recess sidewall.
Wherein, the injection ion of the second ion implanting is lightweight ion, such as one of nitrogen (N), carbon (N), boron (B) or group
It closes, the preferably combination of nitrogen and carbon.Further, the energy of the Nitrogen ion of injection is 1KeV-5KeV, dosage 1e14-8e14/cm2；
The energy of the carbon ion of injection is 1KeV-5KeV, dosage 1e14-8e14/cm2。
Further, the second ion implanting is angle-tilt ion injection, the direction and semiconductor substrate surface normal side of ion beam
It is the angle between the direction and the semiconductor substrate surface normal direction of ion beam, i.e. ion beam can to being in 0-45 ° of angle
To be injected centered on semiconductor substrate surface normal direction to the inclined direction in two sides.Optionally, a kind of angled manner be to
Left and right sides inclination, another angled manner are the inclination of two sides forwards, backwards, and preferably two sides tilt forwards, backwards, to put it more simply, Fig. 3 D
In the case where being tilted to the left centered on semiconductor substrate surface normal direction, is only shown.Further, the second ion note
The injection number entered can be primary, or repeatedly.
Further, the impurity that the second ion implanted region 306 of formation can prevent the first ion implantation technology from being injected exists
Horizontal proliferation occurs along recess sidewall when annealing, leads to Punchthrough and short-channel effect.
First ion implanted region 305 and the second ion implanted region 306 constitute buffering diffusion layer, buffer diffusion layer in annealing
In the diffusion of foreign ion will drive the diffusion of source electrode and drain electrode region impurity so that the Impurity Distribution in source electrode and drain electrode region
It is more uniform, the field distribution gradient of the PN junction in source electrode and drain electrode region is reduced, while controlling lateral short-channel effect, drop
The low junction capacity and junction leakage in source electrode and drain electrode region.
Finally, as illustrated in Figure 3 F, removing photoresist layer 308, then the epitaxial growth source electrode in the groove of source electrode side
307, then the buffering diffusion layer surface epitaxial growth drain electrode 308 in the groove of drain electrode side is annealed.
Wherein, the source electrode and drain electrode is served as a contrast as heavy-doped source drain region, the surface of the source electrode and drain electrode higher than semiconductor
Bottom surface.For PMOSFET, the material as source electrode and drain electrode is germanium silicon layer (SiGe), further, it is also possible in germanium silicon
Suitable boron element (such as B or BF2) is adulterated, to improve performance of semiconductor device, further, the germanium silicon layer is embedded germanium silicon
Layer.For PMOSFET, the material as source electrode and drain electrode is carbon silicon layer (SiC).Channel application is answered using the epitaxial layer
Power, to improve the mobility of carrier.
It can produce more trench edges regions for effectively inhibiting shallowly laterally to tie since source electrode and drain electrode covers, this can be with
More powerful driving current is generated, while improving short-channel effect and inverse short-channel effect.Additionally, due in the gate stack
Asymmetric buffering diffusion layer is formed in the semiconductor substrate of structure side, the foreign ion in annealing in buffering diffusion layer
Diffusion will drive the diffusion of source electrode and drain electrode region impurity, so that the Impurity Distribution in source electrode and drain electrode region is more uniform, reduce
The field distribution gradient of the PN junction in source electrode and drain electrode region reduces source electrode and leakage while controlling lateral short-channel effect
The junction capacity and junction leakage in polar region domain, improve semiconductor devices yield and performance.
In conclusion according to the method for the present invention, buffering diffusion layer is formed before forming source electrode and drain electrode, subsequent
The diffusion that impurity in diffusion layer is buffered in annealing process drives the impurity diffusion in source electrode and drain electrode region, makes source electrode and drain electrode region
Impurity Distribution it is more uniform, reduce the field distribution gradient of the PN junction in source electrode and drain electrode region, while impurity can also be avoided
Horizontal proliferation reduce the junction capacity and junction leakage in source electrode and drain electrode region while controlling lateral short-channel effect,
Improve semiconductor devices yield and performance.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (15)
1. a kind of manufacturing method of semiconductor devices, which comprises the following steps:
Semiconductor substrate is provided, is formed with gate stack structure on the semiconductor substrate surface；
The semiconductor substrate is performed etching using the gate stack structure as exposure mask, in the gate stack structure two sides
Semiconductor substrate in form groove；
The buffering diffusion layer for surrounding the groove is formed in at least side of the gate stack structure；
Source electrode and drain electrode is formed in the groove.
2. the method according to claim 1, wherein the buffering diffusion layer is included in the gate stack structure
The symmetrical buffering diffusion layer that two sides are formed.
3. according to the method described in claim 2, it is characterized in that, the method for forming the symmetrical buffering diffusion layer includes:
The first ion implantation technology is executed, in the semiconductor substrate of the bottom portion of groove of the gate stack structure two sides
Form the first ion implanted region；
The second ion implantation technology is executed, with the semiconductor at first ion implanted region surface and the recess sidewall
The second ion implanted region is formed in substrate.
4. the method according to claim 1, wherein the buffering diffusion layer includes only in the gate stack knot
The asymmetric buffering diffusion layer that structure side is formed.
5. according to the method described in claim 4, it is characterized in that, forming the method packet of the asymmetric buffering diffusion layer
It includes:
Pattern is formed on the semiconductor substrate of the gate stack structure side and part the gate stack structure surface
The photoresist layer of change；
Using the photoresist layer as exposure mask, the first ion implantation technology is executed, with described in the gate stack structure side
The first ion implanted region is formed in the semiconductor substrate of bottom portion of groove；
The second ion implantation technology is executed, with the semiconductor at first ion implanted region surface and the recess sidewall
The second ion implanted region is formed in substrate；
Remove the photoresist layer.
6. the method according to claim 3 or 5, which is characterized in that first ion implantation technology is vertical ion note
Enter.
7. according to the method described in claim 6, it is characterized in that, the injection ion of first ion implantation technology includes
Silicon.
8. the method according to the description of claim 7 is characterized in that injecting ion silicon in first ion implantation technology
Energy be 1KeV-5KeV, dosage 1e13-5e13/cm2。
9. the method according to claim 3 or 5, which is characterized in that second ion implantation technology is angle-tilt ion note
Enter.
10. according to the method described in claim 9, it is characterized in that, in second ion implantation technology, the side of ion beam
To with semiconductor substrate surface normal direction be in 0-45oAngle, the angle ranging from ion beam direction and the semiconductor substrate table
Angle between the normal direction of face.
11. according to the method described in claim 10, it is characterized in that, the injection ion of second ion implantation technology includes
Nitrogen.
12. according to the method for claim 11, which is characterized in that the injection ion of second ion implantation technology also wraps
Include carbon.
13. according to the method for claim 11, which is characterized in that in second ion implantation technology, inject ion
The energy of nitrogen is 1KeV-5KeV, dosage 1e14-8e14/cm2。
14. according to the method for claim 12, which is characterized in that in second ion implantation technology, inject ion
The energy of carbon is 1KeV-5KeV, dosage 1e14-8e14/cm2。
15. the method according to claim 1, wherein the semiconductor devices includes FinFET.
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| CN114068705A (en) * | 2020-07-31 | 2022-02-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| US20120091469A1 (en) * | 2010-10-13 | 2012-04-19 | Park Keum-Seok | Semiconductor Devices Having Shallow Junctions |
| CN103426769A (en) * | 2012-05-25 | 2013-12-04 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN104124167A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
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| US20120091469A1 (en) * | 2010-10-13 | 2012-04-19 | Park Keum-Seok | Semiconductor Devices Having Shallow Junctions |
| CN103426769A (en) * | 2012-05-25 | 2013-12-04 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
| CN104124167A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and forming method thereof |
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| CN111627816A (en) * | 2019-02-28 | 2020-09-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN111627816B (en) * | 2019-02-28 | 2023-07-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN114068705A (en) * | 2020-07-31 | 2022-02-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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