CN105529266A - Improvement method for dislocation defects of embedded silicon-germanium epitaxy - Google Patents

Abstract

The invention provides an improvement method for dislocation defects of an embedded silicon-germanium epitaxy. The improvement method comprises the steps as follows: before a reaction process of the silicon-germanium epitaxy, after wet cleaning, low-volume etching is carried out on the surface of a wafer on which a silicon substrate is located by adding and using a dry etching method, and a silicon nucleation layer with a same lattice structure as the silicon substrate grows out, so that the silicon substrate part with a lattice damage caused by plasmas in a front-end process is removed and replaced; and the roughness and the cleanliness of the inner wall surface of a to-be-extended groove in the silicon substrate are improved. According to the improvement method, the dislocation defects caused by an interface defect source in the growth process of the embedded silicon-germanium epitaxy can be reduced; the stress of silicon-germanium is improved; and the electrical property of a PMOS transistor is improved.

Description

Embedded baby germanium epitaxy method for improving the dislocation defects

FIELD

[0001] The present invention relates to the technical field of the preparation of the embedded SiGe epitaxial layer, particularly, the present invention relates to a method for improving an embedded SiGe epitaxial dislocation defects.

Background technique

[0002] is well known, performance of the CMOS circuit is largely restricted by the PMOS transistor. Thus, if any technique is possible to improve the performance of PMOS to NMOS levels are considered to be advantageous. In the PMOS 90nm, the Intel (Intel) engineers the source device, the drain is removed by etching, and then re-deposited SiGe layer, so that the source and drain will produce a compressive stress to the channel, thereby improving the transmission characteristics of the PMOS.

[0003] FIG. 1 is a prior art silicon germanium source / drain implant technique a PMOS structure induced strain. As shown, the silicon germanium source 1 shown in FIG / drain implant technique induced strain is embedded into the silicon germanium source / drain regions, resulting in compression set at the channel, to improve the carrier mobility of the PMOS transistor, and the carrier mobility can result in smell provide audible driving current of the transistor smell mention cartridge pan.

[0004] The silicon (Si) thin film grown on a silicon germanium substrate, i.e., an epitaxial growth process the strained layer process. Typically, if the trench surface defects, silicon germanium will not form a good single crystal structure, relaxation occurs during growth, the accumulation of strain in the film causes slip crystal surface, the interfacial atomic arrangement shifted, a sharp strain release, a large amount of defects in the film, leading to strain relaxation.

[0005] The conventional epitaxial process include: pre epitaxial wet cleaning; corrosion coating chamber; hydrogen baking before epitaxial growth; SiGe deposition. Using conventional epitaxial SiGe selectively in the process, wet cleaning can not be done on the surface of a wafer for fine processing, so that there are local residual, or the uneven surface of the wafer, the epitaxial growth results in after source interface defects, serious drawbacks may extend into the growth surface of silicon-germanium. In the process using a conventional epitaxial SiGe selectively using a scanning transmission electron microscope, there was found 100% SiGe epitaxial dislocation defects.

[0006] Thus, the present art need a new SiGe selective epitaxy process, to overcome the drawbacks of the prior art.

SUMMARY

[0007] The present invention solves the technical problem of providing an embedded SiGe epitaxial method for improving dislocation defects, decrease in the embedded SiGe epitaxial growth of dislocation defects due to interface defects caused by the source, to increase the germanium silicon stress, improved electrically PMOS transistor.

[0008] To solve the above problems, the present invention provides an embedded SiGe epitaxial improve dislocation defects of the method, said process comprising the reaction prior to the epitaxial silicon germanium, after the wet cleaning, dry etching increases the method of the surface of the silicon substrate wafer where the low and the amount of etching the silicon regrown with a lattice structure the same silicon substrate as a nucleation layer to remove and replace the front-end processes since portion of the silicon substrate lattice damage caused by the plasma, improving the surface roughness and cleanliness of the inner walls of the trench to be epitaxially on the silicon substrate.

[0009] Alternatively, the method for improving the wafer is placed under a low pressure, high-temperature environmental conditions, for less than 5 nanometers thickness of dry etching the surface thereof.

[0010] Alternatively, the low pressure means 50 Torr, the temperature is 600 to 800 degrees Celsius means.

[0011] Alternatively, the etching gas for dry etching of the wafer surface to hydrogen chloride gas.

[0012] Alternatively, the depth of the trench to be epitaxially on the silicon substrate 400 to 800 angstroms.

[0013] Alternatively, the improved method is applicable to 45 nm, 40 nm, 32 nm, 28 nm, or 22 nm technology node.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] The present invention prior to the reaction of silicon-germanium epitaxy, after the wet cleaning, the increased use of dry etching method of introducing the surface of the silicon substrate of low amounts of etching the regrown crystal silicon substrate, the same silicon lattice structure of a nucleation layer, is removed and replaced in the front-end processes lattice damage caused by the silicon substrate portion.

[0016] The present invention improves the cleanliness and roughness of the inner wall surfaces of the trench to be epitaxial, avoids the disadvantages of the SiGe epitaxial growth process due to interface defects such as dislocation due to the source, improved stress silicon-germanium, improved electrically PMOS transistor.

[0017] After application of the embedded SiGe improved selective epitaxial process, also using a scanning transmission electron microscope, it was found SiGe epitaxial defects generated in the interface is zero.

BRIEF DESCRIPTION

[0018] The above and other features, nature, and advantages of the invention will be described by the following example of embodiment become more apparent from the accompanying drawings and in which:

[0019] FIG. 1 is a prior art silicon germanium source / drain implant technique a PMOS structure induced strain;

Cross-sectional view [0020] FIG 2 test structure (test key) is formed as an embedded SiGe epitaxial process in a schematic view of the prior art;

[0021] FIG. 3 is a cross-sectional structure formed after a test method for improving bit embedded SiGe epitaxial embodiment of dislocation defects present embodiment schematic view of one embodiment of the invention;

[0022] FIG. 4 showing the results of the process (scanning electron microscopy) after the embedded SiGe epitaxial method for improving bit error embodiment of a defect embodiment of the invention.

Detailed ways

[0023] The following embodiments in conjunction with specific embodiments and drawings the present invention will be further described, more details are set forth in the following description in order to provide a thorough understanding of the present invention, it is clear that the present invention can be in various other ways than described herein be implemented, as those skilled in the art may be similar extensions, without departing from the interpretation of the connotation of the present invention depending on the application, in this example of the content should therefore not limit the scope of particular embodiments of the present invention.

Cross-sectional view [0024] FIG 2 test structure (test key) is formed as an embedded SiGe epitaxial process is not intended to prior art, the inner wall surface of the trench in the substrate baby still remains a surface damage layer; FIG. 3 a schematic cross-sectional structure formed after the test embodiment of the present invention to improve the method of one embodiment of an embedded SiGe epitaxial dislocation defects, the inner wall surface of the trench in the silicon substrate a nucleation layer instead of silicon has been damaged silicon substrate the bottom part. It should be noted that these and other subsequent drawings are only exemplary, which are not drawn according to the conditions of equal proportions, and as should not be construed to limit the scope of the present invention is actually required.

An inner wall surface of trench [0025] First, as shown in the prior embodiments of the present invention to improve the method, the prior art test structure (TestKey) 100 to be in an epitaxial silicon substrate 2 surface damage layer still remained 102 . After the silicon germanium source / drain 103 are epitaxially grown, in which 105 is easy to produce dislocation defects (lattice damage). Further, reference numeral 101 is a polysilicon gate.

[0026] As shown in FIG. 3, the content of the improved method of the present invention mainly comprises: prior to the epitaxial silicon germanium (also called selective epitaxy) during the reaction, after the wet cleaning, dry etching increases before the method 200 where the surface of a wafer of a silicon substrate stable low amount of etching, and the regrown silicon with a lattice structure the same as the nucleation layer 200 silicon substrate 202, to remove and replace channel process portion of the silicon substrate 200 due to the plasma due to lattice damage, and improving the roughness of the silicon substrate and the inner wall surfaces of the cleanliness of the trenches 200 to be on the extension, to avoid the reaction of the silicon germanium epitaxial process dislocations and other defects.

[0027] Specifically, the method for improving the wafer is placed in a low pressure, high temperature ambient conditions, such as the use of hydrogen chloride (HCL) gas as an etching gas, dry etching the surface thereof less than 5 nanometers thickness . Wherein the low pressure means 50 Torr, the temperature is 600 to 800 degrees Celsius means.

[0028] In the present embodiment, the depth of the trench to be epitaxially on the silicon substrate 200 is 400 to 800 angstroms.

[0029] FIG. 4 showing the results of the process (scanning electron microscopy) after the embedded SiGe epitaxial method for improving bit error embodiment of a defect embodiment of the invention. 4, after improving the method of the present invention embodiment, the present embodiment the trench structure of the inner wall surfaces of the test to be in an epitaxial silicon substrate 200 remains no surface damage layer 102, and replaced with the silicon lattice structure the same silicon substrate 200 as a nucleation layer 202. In the SiGe source / drain 203 is then epitaxially grown, in which there is no generation of dislocation defects 105 (lattice damage), silicon germanium source / drain clear and smooth interface 200 and the silicon substrate 203, no abnormal defects. Thus since the interface source of defects caused by dislocation defects conditions greatly improved, to avoid strain relaxation. Further, reference numeral 201 is a polysilicon gate.

[0030] In the present invention, the improved method may be applied to 45 nm, 40 nm, 32 nm, 28 nm, or 22 nm technology node.

[0031] In summary, the present invention prior to the reaction of the SiGe epitaxial layer, after the wet cleaning, the increased use of dry etching method of introducing the surface of the silicon substrate of low amounts of etching and regrown silicon lattice structure the same silicon substrate as a nucleation layer, is removed and replaced in the front-end processes lattice damage caused by the silicon substrate portion.

[0032] The present invention improves the cleanliness and roughness of the inner wall surfaces of the trench to be epitaxial, avoids the disadvantages of the SiGe epitaxial growth process due to interface defects such as dislocation due to the source, improved stress silicon-germanium, improved electrically PMOS transistor.

[0033] After application of the embedded SiGe improved selective epitaxial process, also using a scanning transmission electron microscope, it was found SiGe epitaxial defects generated in the interface is zero.

[0034] Although the preferred embodiments of the present invention disclosed in the above embodiments, but not intended to limit the present invention, anyone skilled in the art without departing from the spirit and scope of the invention, can be made possible variations and modifications. Thus, all without departing from the technical solutions of the present invention, any modification based on the technical essence of the present invention is made to the above embodiment of the embodiment, modifications and equivalent variations as fall within the scope of the claims of the invention as defined in the.

Claims (6)

1. A method for improving the embedded SiGe epitaxial dislocation defects, including prior to the reaction of the SiGe epitaxial, after the wet cleaning, increase dry etching method where a silicon substrate (200) the surface of a wafer is low and the amount of etching of the silicon substrate regrown with a lattice structure the same silicon nucleation layer (202) (200) to remove and replace the front-end processes due to the plasma surface roughness and cleanliness of the inner wall of the trench of the silicon substrate lattice damage caused by the body (200) portion of the silicon substrate to be improved on the epitaxial (200).

The improved method according to claim 1, characterized in that the method for improving the wafer is placed in a low pressure environment of high temperature, the surface thereof is less than 5 nm of thickness dry etching .

3. The improved method of claim 2, wherein said low pressure means less than 50 Torr, the temperature is 600 to 800 degrees Celsius means.

4. The improved method of claim 3, wherein the etching gas for dry etching the surface of the wafer is hydrogen chloride gas.

The improved method according to claim 4, characterized in that the depth of the trench to be epitaxially on the silicon substrate (200) of 400 to 800 angstroms.

6. The improved method of claim 5, wherein the improved method is applicable to 45 nm, 40 nm, 32 nm, 28 nm, or 22 nm technology node.