CN105529266A - Improvement method for dislocation defects of embedded silicon-germanium epitaxy - Google Patents

Improvement method for dislocation defects of embedded silicon-germanium epitaxy Download PDF

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CN105529266A
CN105529266A CN201410561809.1A CN201410561809A CN105529266A CN 105529266 A CN105529266 A CN 105529266A CN 201410561809 A CN201410561809 A CN 201410561809A CN 105529266 A CN105529266 A CN 105529266A
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silicon substrate
silicon
nm
improved
surface
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CN201410561809.1A
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周海锋
谭俊
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上海华力微电子有限公司
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Abstract

The invention provides an improvement method for dislocation defects of an embedded silicon-germanium epitaxy. The improvement method comprises the steps as follows: before a reaction process of the silicon-germanium epitaxy, after wet cleaning, low-volume etching is carried out on the surface of a wafer on which a silicon substrate is located by adding and using a dry etching method, and a silicon nucleation layer with a same lattice structure as the silicon substrate grows out, so that the silicon substrate part with a lattice damage caused by plasmas in a front-end process is removed and replaced; and the roughness and the cleanliness of the inner wall surface of a to-be-extended groove in the silicon substrate are improved. According to the improvement method, the dislocation defects caused by an interface defect source in the growth process of the embedded silicon-germanium epitaxy can be reduced; the stress of silicon-germanium is improved; and the electrical property of a PMOS transistor is improved.

Description

嵌入式锗娃外延位错缺陷的改善方法 Embedded baby germanium epitaxy method for improving the dislocation defects

技术领域 FIELD

[0001] 本发明涉及嵌入式锗硅外延的制备技术领域,具体来说,本发明涉及一种嵌入式锗硅外延位错缺陷的改善方法。 [0001] The present invention relates to the technical field of the preparation of the embedded SiGe epitaxial layer, particularly, the present invention relates to a method for improving an embedded SiGe epitaxial dislocation defects.

背景技术 Background technique

[0002] 众所周知,CMOS电路的性能在很大程度上受PMOS晶体管的制约。 [0002] is well known, performance of the CMOS circuit is largely restricted by the PMOS transistor. 因此,任何技术如果能够把PMOS的性能提高到NMOS的水平都被认为是有利的。 Thus, if any technique is possible to improve the performance of PMOS to NMOS levels are considered to be advantageous. 在90nm的PMOS中,英特尔(Intel)的工程师将器件的源、漏刻蚀去除,然后重新淀积锗硅层,这样源和漏就会对沟道产生一个压缩应力,从而提高PMOS的传输特性。 In the PMOS 90nm, the Intel (Intel) engineers the source device, the drain is removed by etching, and then re-deposited SiGe layer, so that the source and drain will produce a compressive stress to the channel, thereby improving the transmission characteristics of the PMOS.

[0003] 图1为现有技术中的一种锗硅源/漏植入致应变技术的PMOS结构。 [0003] FIG. 1 is a prior art silicon germanium source / drain implant technique a PMOS structure induced strain. 如图1所示,锗硅源/漏植入致应变技术是将锗硅镶嵌到源/漏区,从而在沟道处产生压缩形变,提高PMOS晶体管的载流子迁移率,而载流子迁移率的提闻可导致闻的驱动电流,提闻晶体管性倉泛。 As shown, the silicon germanium source 1 shown in FIG / drain implant technique induced strain is embedded into the silicon germanium source / drain regions, resulting in compression set at the channel, to improve the carrier mobility of the PMOS transistor, and the carrier mobility can result in smell provide audible driving current of the transistor smell mention cartridge pan.

[0004] 在硅(Si)衬底上生长锗硅薄膜,生长应变层的工艺即外延工艺过程。 [0004] The silicon (Si) thin film grown on a silicon germanium substrate, i.e., an epitaxial growth process the strained layer process. 通常如果沟槽表面存在缺陷,锗硅将不能形成很好的单晶结构,在生长过程中就会发生弛豫,薄膜中积累的应变会引起晶面滑移,使界面原子排列错开,应变急剧释放,在薄膜中产生大量缺陷,导致应变弛豫。 Typically, if the trench surface defects, silicon germanium will not form a good single crystal structure, relaxation occurs during growth, the accumulation of strain in the film causes slip crystal surface, the interfacial atomic arrangement shifted, a sharp strain release, a large amount of defects in the film, leading to strain relaxation.

[0005] 现有的该外延工艺流程主要包括:外延前进行湿法清洗;腔体腐蚀和覆膜;外延生长前的氢气烘烤;锗硅沉积。 [0005] The conventional epitaxial process include: pre epitaxial wet cleaning; corrosion coating chamber; hydrogen baking before epitaxial growth; SiGe deposition. 在使用传统的锗硅选择性外延的工艺流程中,湿法清洗不能做到对晶圆片表面进行细微的处理,致使在晶圆片表面有局部的残余,或是高低不平,导致在外延生长后,在界面产生缺陷源,严重的缺陷可能延续到锗硅的生长表面。 Using conventional epitaxial SiGe selectively in the process, wet cleaning can not be done on the surface of a wafer for fine processing, so that there are local residual, or the uneven surface of the wafer, the epitaxial growth results in after source interface defects, serious drawbacks may extend into the growth surface of silicon-germanium. 在使用现有的锗硅选择性外延的工艺流程中,使用透射电镜扫描,发现100%都有锗硅外延的位错缺陷。 In the process using a conventional epitaxial SiGe selectively using a scanning transmission electron microscope, there was found 100% SiGe epitaxial dislocation defects.

[0006] 因此,本领域中亟需一种新的锗硅选择性外延工艺,克服现有技术中存在的缺陷。 [0006] Thus, the present art need a new SiGe selective epitaxy process, to overcome the drawbacks of the prior art.

发明内容 SUMMARY

[0007] 本发明所要解决的技术问题是提供一种嵌入式锗硅外延位错缺陷的改善方法,减少在嵌入式锗硅外延的生长过程中由于界面缺陷源导致的位错缺陷,以提高锗硅的应力,改善PMOS晶体管的电性。 [0007] The present invention solves the technical problem of providing an embedded SiGe epitaxial method for improving dislocation defects, decrease in the embedded SiGe epitaxial growth of dislocation defects due to interface defects caused by the source, to increase the germanium silicon stress, improved electrically PMOS transistor.

[0008] 为解决上述技术问题,本发明提供一种嵌入式锗硅外延位错缺陷的改善方法,包括在所述锗硅外延的反应过程之前,在湿法清洗过后,增加使用干法刻蚀的方法对硅衬底所在的晶圆片的表面进行低量的刻蚀以及再生长出与所述硅衬底相同晶格结构的一硅成核层,以移除并替代前道工艺中由于等离子体造成的晶格损伤的所述硅衬底部分,改善所述硅衬底上待外延的沟槽内壁表面的粗糙度和清洁度。 [0008] To solve the above problems, the present invention provides an embedded SiGe epitaxial improve dislocation defects of the method, said process comprising the reaction prior to the epitaxial silicon germanium, after the wet cleaning, dry etching increases the method of the surface of the silicon substrate wafer where the low and the amount of etching the silicon regrown with a lattice structure the same silicon substrate as a nucleation layer to remove and replace the front-end processes since portion of the silicon substrate lattice damage caused by the plasma, improving the surface roughness and cleanliness of the inner walls of the trench to be epitaxially on the silicon substrate.

[0009] 可选地,所述改善方法是将所述晶圆片放在低压、高温的环境条件下,对其表面进行小于5纳米厚度的干法刻蚀。 [0009] Alternatively, the method for improving the wafer is placed under a low pressure, high-temperature environmental conditions, for less than 5 nanometers thickness of dry etching the surface thereof.

[0010] 可选地,所述低压是指50托以下,所述高温是指600至800摄氏度。 [0010] Alternatively, the low pressure means 50 Torr, the temperature is 600 to 800 degrees Celsius means.

[0011] 可选地,对所述晶圆片的表面进行干法刻蚀的刻蚀气体为氯化氢气体。 [0011] Alternatively, the etching gas for dry etching of the wafer surface to hydrogen chloride gas.

[0012] 可选地,所述硅衬底上待外延的所述沟槽的深度为400至800埃。 [0012] Alternatively, the depth of the trench to be epitaxially on the silicon substrate 400 to 800 angstroms.

[0013] 可选地,所述改善方法适用于45纳米、40纳米、32纳米、28纳米、22纳米或其以下技术节点。 [0013] Alternatively, the improved method is applicable to 45 nm, 40 nm, 32 nm, 28 nm, or 22 nm technology node.

[0014] 与现有技术相比,本发明具有以下优点: [0014] Compared with the prior art, the present invention has the following advantages:

[0015] 本发明在锗硅外延的反应过程之前,湿法清洗过后,增加引入使用干法刻蚀的方法对硅衬底的表面进行低量的刻蚀,再生长出与硅衬底相同晶格结构的硅成核层,移除并替代前道工艺中造成晶格损伤的硅衬底部分。 [0015] The present invention prior to the reaction of silicon-germanium epitaxy, after the wet cleaning, the increased use of dry etching method of introducing the surface of the silicon substrate of low amounts of etching the regrown crystal silicon substrate, the same silicon lattice structure of a nucleation layer, is removed and replaced in the front-end processes lattice damage caused by the silicon substrate portion.

[0016] 本发明改善了待外延的沟槽内壁表面的粗糙度和清洁度,避免了锗硅外延的生长过程中由于界面缺陷源导致的位错等缺陷,提高了锗硅的应力,改善了PMOS晶体管的电性。 [0016] The present invention improves the cleanliness and roughness of the inner wall surfaces of the trench to be epitaxial, avoids the disadvantages of the SiGe epitaxial growth process due to interface defects such as dislocation due to the source, improved stress silicon-germanium, improved electrically PMOS transistor.

[0017] 在应用了改进后的嵌入式锗硅选择性外延工艺流程后,同样使用透射电镜扫描,发现锗硅外延界面产生的缺陷已为零。 [0017] After application of the embedded SiGe improved selective epitaxial process, also using a scanning transmission electron microscope, it was found SiGe epitaxial defects generated in the interface is zero.

附图说明 BRIEF DESCRIPTION

[0018] 本发明的上述的以及其他的特征、性质和优势将通过下面结合附图和实施例的描述而变得更加明显,其中: [0018] The above and other features, nature, and advantages of the invention will be described by the following example of embodiment become more apparent from the accompanying drawings and in which:

[0019] 图1为现有技术中的一种锗硅源/漏植入致应变技术的PMOS结构; [0019] FIG. 1 is a prior art silicon germanium source / drain implant technique a PMOS structure induced strain;

[0020] 图2为现有技术中的一种嵌入式锗硅外延工艺形成的测试结构(test key)的剖面示意图; Cross-sectional view [0020] FIG 2 test structure (test key) is formed as an embedded SiGe epitaxial process in a schematic view of the prior art;

[0021] 图3为本发明一个实施例的嵌入式锗硅外延位错缺陷的改善方法实施之后形成的测试结构的剖面示意图; [0021] FIG. 3 is a cross-sectional structure formed after a test method for improving bit embedded SiGe epitaxial embodiment of dislocation defects present embodiment schematic view of one embodiment of the invention;

[0022] 图4为本发明一个实施例的嵌入式锗硅外延位错缺陷的改善方法实施之后的工艺结果示意图(透射电镜扫描)。 [0022] FIG. 4 showing the results of the process (scanning electron microscopy) after the embedded SiGe epitaxial method for improving bit error embodiment of a defect embodiment of the invention.

具体实施方式 Detailed ways

[0023] 下面结合具体实施例和附图对本发明作进一步说明,在以下的描述中阐述了更多的细节以便于充分理解本发明,但是本发明显然能够以多种不同于此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下根据实际应用情况作类似推广、演绎,因此不应以此具体实施例的内容限制本发明的保护范围。 [0023] The following embodiments in conjunction with specific embodiments and drawings the present invention will be further described, more details are set forth in the following description in order to provide a thorough understanding of the present invention, it is clear that the present invention can be in various other ways than described herein be implemented, as those skilled in the art may be similar extensions, without departing from the interpretation of the connotation of the present invention depending on the application, in this example of the content should therefore not limit the scope of particular embodiments of the present invention.

[0024] 图2为现有技术中的一种嵌入式锗硅外延工艺形成的测试结构(test key)的剖面不意图,其娃衬底中的沟槽内壁表面仍残留表面损伤层;图3为本发明一个实施例的嵌入式锗硅外延位错缺陷的改善方法实施之后形成的测试结构的剖面示意图,其硅衬底中的沟槽内壁表面已用硅成核层替代受损伤的硅衬底部分。 Cross-sectional view [0024] FIG 2 test structure (test key) is formed as an embedded SiGe epitaxial process is not intended to prior art, the inner wall surface of the trench in the substrate baby still remains a surface damage layer; FIG. 3 a schematic cross-sectional structure formed after the test embodiment of the present invention to improve the method of one embodiment of an embedded SiGe epitaxial dislocation defects, the inner wall surface of the trench in the silicon substrate a nucleation layer instead of silicon has been damaged silicon substrate the bottom part. 需要注意的是,这些以及后续其他的附图均仅作为示例,其并非是按照等比例的条件绘制的,并且不应该以此作为对本发明实际要求的保护范围构成限制。 It should be noted that these and other subsequent drawings are only exemplary, which are not drawn according to the conditions of equal proportions, and as should not be construed to limit the scope of the present invention is actually required.

[0025] 首先,如图2所示,在本发明的改善方法实施之前,现有技术中的测试结构(testkey)在硅衬底100中待外延的沟槽内壁表面仍残留着表面损伤层102。 An inner wall surface of trench [0025] First, as shown in the prior embodiments of the present invention to improve the method, the prior art test structure (TestKey) 100 to be in an epitaxial silicon substrate 2 surface damage layer still remained 102 . 在锗硅源/漏103被外延生长之后,在其中易产生位错缺陷105 (晶格损伤)。 After the silicon germanium source / drain 103 are epitaxially grown, in which 105 is easy to produce dislocation defects (lattice damage). 另外,附图标记101为多晶硅栅。 Further, reference numeral 101 is a polysilicon gate.

[0026] 如图3所示,本发明的该改善方法的内容主要包括:在该锗硅外延(又称为选择性外延)的反应过程之前,在湿法清洗过后,增加使用干法刻蚀的方法对硅衬底200所在的晶圆片的表面进行稳定低量的刻蚀,以及再生长出与该硅衬底200相同晶格结构的一硅成核层202,以移除并替代前道工艺中由于等离子体造成的晶格损伤的该硅衬底200部分,改善该硅衬底200上待外延的沟槽内壁表面的粗糙度和清洁度,避免在锗硅外延的反应过程中产生位错等缺陷。 [0026] As shown in FIG. 3, the content of the improved method of the present invention mainly comprises: prior to the epitaxial silicon germanium (also called selective epitaxy) during the reaction, after the wet cleaning, dry etching increases before the method 200 where the surface of a wafer of a silicon substrate stable low amount of etching, and the regrown silicon with a lattice structure the same as the nucleation layer 200 silicon substrate 202, to remove and replace channel process portion of the silicon substrate 200 due to the plasma due to lattice damage, and improving the roughness of the silicon substrate and the inner wall surfaces of the cleanliness of the trenches 200 to be on the extension, to avoid the reaction of the silicon germanium epitaxial process dislocations and other defects.

[0027] 具体地,该改善方法是将该晶圆片放在低压、高温的环境条件下,使用如氯化氢(HCL)气体作为刻蚀气体,对其表面进行小于5纳米厚度的干法刻蚀。 [0027] Specifically, the method for improving the wafer is placed in a low pressure, high temperature ambient conditions, such as the use of hydrogen chloride (HCL) gas as an etching gas, dry etching the surface thereof less than 5 nanometers thickness . 其中,该低压是指50托以下,该高温是指600至800摄氏度。 Wherein the low pressure means 50 Torr, the temperature is 600 to 800 degrees Celsius means.

[0028] 在本实施例中,该硅衬底200上待外延的该沟槽的深度为400至800埃。 [0028] In the present embodiment, the depth of the trench to be epitaxially on the silicon substrate 200 is 400 to 800 angstroms.

[0029] 图4为本发明一个实施例的嵌入式锗硅外延位错缺陷的改善方法实施之后的工艺结果示意图(透射电镜扫描)。 [0029] FIG. 4 showing the results of the process (scanning electron microscopy) after the embedded SiGe epitaxial method for improving bit error embodiment of a defect embodiment of the invention. 如图4所示,在本发明的改善方法实施之后,本实施例中的测试结构在硅衬底200中待外延的沟槽内壁表面不再残留有表面损伤层102,而代之以与该硅衬底200相同晶格结构的硅成核层202。 4, after improving the method of the present invention embodiment, the present embodiment the trench structure of the inner wall surfaces of the test to be in an epitaxial silicon substrate 200 remains no surface damage layer 102, and replaced with the silicon lattice structure the same silicon substrate 200 as a nucleation layer 202. 在锗硅源/漏203被外延生长之后,在其中不再产生有位错缺陷105 (晶格损伤),锗硅源/漏203与硅衬底200之间界面清晰光滑,没有异常缺陷产生。 In the SiGe source / drain 203 is then epitaxially grown, in which there is no generation of dislocation defects 105 (lattice damage), silicon germanium source / drain clear and smooth interface 200 and the silicon substrate 203, no abnormal defects. 因而由于界面缺陷源引发的位错缺陷状况得到极大的改善,避免了应变弛豫。 Thus since the interface source of defects caused by dislocation defects conditions greatly improved, to avoid strain relaxation. 另外,附图标记201为多晶硅栅。 Further, reference numeral 201 is a polysilicon gate.

[0030] 在本发明中,该改善方法可以适用于45纳米、40纳米、32纳米、28纳米、22纳米或其以下技术节点。 [0030] In the present invention, the improved method may be applied to 45 nm, 40 nm, 32 nm, 28 nm, or 22 nm technology node.

[0031] 综上所述,本发明在锗硅外延的反应过程之前,湿法清洗过后,增加引入使用干法刻蚀的方法对硅衬底的表面进行低量的刻蚀,再生长出与硅衬底相同晶格结构的硅成核层,移除并替代前道工艺中造成晶格损伤的硅衬底部分。 [0031] In summary, the present invention prior to the reaction of the SiGe epitaxial layer, after the wet cleaning, the increased use of dry etching method of introducing the surface of the silicon substrate of low amounts of etching and regrown silicon lattice structure the same silicon substrate as a nucleation layer, is removed and replaced in the front-end processes lattice damage caused by the silicon substrate portion.

[0032] 本发明改善了待外延的沟槽内壁表面的粗糙度和清洁度,避免了锗硅外延的生长过程中由于界面缺陷源导致的位错等缺陷,提高了锗硅的应力,改善了PMOS晶体管的电性。 [0032] The present invention improves the cleanliness and roughness of the inner wall surfaces of the trench to be epitaxial, avoids the disadvantages of the SiGe epitaxial growth process due to interface defects such as dislocation due to the source, improved stress silicon-germanium, improved electrically PMOS transistor.

[0033] 在应用了改进后的嵌入式锗硅选择性外延工艺流程后,同样使用透射电镜扫描,发现锗硅外延界面产生的缺陷已为零。 [0033] After application of the embedded SiGe improved selective epitaxial process, also using a scanning transmission electron microscope, it was found SiGe epitaxial defects generated in the interface is zero.

[0034] 本发明虽然以较佳实施例公开如上,但其并不是用来限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,都可以做出可能的变动和修改。 [0034] Although the preferred embodiments of the present invention disclosed in the above embodiments, but not intended to limit the present invention, anyone skilled in the art without departing from the spirit and scope of the invention, can be made possible variations and modifications. 因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何修改、等同变化及修饰,均落入本发明权利要求所界定的保护范围之内。 Thus, all without departing from the technical solutions of the present invention, any modification based on the technical essence of the present invention is made to the above embodiment of the embodiment, modifications and equivalent variations as fall within the scope of the claims of the invention as defined in the.

Claims (6)

1.一种嵌入式锗硅外延位错缺陷的改善方法,包括在所述锗硅外延的反应过程之前,在湿法清洗过后,增加使用干法刻蚀的方法对硅衬底(200)所在的晶圆片的表面进行低量的刻蚀以及再生长出与所述硅衬底(200)相同晶格结构的一硅成核层(202),以移除并替代前道工艺中由于等离子体造成的晶格损伤的所述硅衬底(200)部分,改善所述硅衬底(200)上待外延的沟槽内壁表面的粗糙度和清洁度。 1. A method for improving the embedded SiGe epitaxial dislocation defects, including prior to the reaction of the SiGe epitaxial, after the wet cleaning, increase dry etching method where a silicon substrate (200) the surface of a wafer is low and the amount of etching of the silicon substrate regrown with a lattice structure the same silicon nucleation layer (202) (200) to remove and replace the front-end processes due to the plasma surface roughness and cleanliness of the inner wall of the trench of the silicon substrate lattice damage caused by the body (200) portion of the silicon substrate to be improved on the epitaxial (200).
2.根据权利要求1所述的改善方法,其特征在于,所述改善方法是将所述晶圆片放在低压、高温的环境条件下,对其表面进行小于5纳米厚度的干法刻蚀。 The improved method according to claim 1, characterized in that the method for improving the wafer is placed in a low pressure environment of high temperature, the surface thereof is less than 5 nm of thickness dry etching .
3.根据权利要求2所述的改善方法,其特征在于,所述低压是指50托以下,所述高温是指600至800摄氏度。 3. The improved method of claim 2, wherein said low pressure means less than 50 Torr, the temperature is 600 to 800 degrees Celsius means.
4.根据权利要求3所述的改善方法,其特征在于,对所述晶圆片的表面进行干法刻蚀的刻蚀气体为氯化氢气体。 4. The improved method of claim 3, wherein the etching gas for dry etching the surface of the wafer is hydrogen chloride gas.
5.根据权利要求4所述的改善方法,其特征在于,所述硅衬底(200)上待外延的所述沟槽的深度为400至800埃。 The improved method according to claim 4, characterized in that the depth of the trench to be epitaxially on the silicon substrate (200) of 400 to 800 angstroms.
6.根据权利要求5所述的改善方法,其特征在于,所述改善方法适用于45纳米、40纳米、32纳米、28纳米、22纳米或其以下技术节点。 6. The improved method of claim 5, wherein the improved method is applicable to 45 nm, 40 nm, 32 nm, 28 nm, or 22 nm technology node.
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Publication number Priority date Publication date Assignee Title
US20070287272A1 (en) * 2006-06-07 2007-12-13 Asm America, Inc. Selective epitaxial formation of semiconductor films
CN102810482A (en) * 2011-06-02 2012-12-05 中芯国际集成电路制造(北京)有限公司 Method for manufacturing semiconductor devices
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