CN112017962A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112017962A
CN112017962A CN201910459875.0A CN201910459875A CN112017962A CN 112017962 A CN112017962 A CN 112017962A CN 201910459875 A CN201910459875 A CN 201910459875A CN 112017962 A CN112017962 A CN 112017962A
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substrate
ions
forming
source
semiconductor structure
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赵猛
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a grid structure on the substrate, wherein the substrate below the grid structure is used as a channel region; forming grooves in the substrate on two sides of the grid structure; forming a doped region at the bottom of the trench close to the channel region and in the substrate below the channel region, wherein the doped region contains second type ions, and the type of the second type ions is different from that of the first type transistor; and forming a source drain doping layer in the groove after forming the doping region. According to the embodiment of the invention, the doping region enables the doped ions in the source-drain doping layer to be difficult to diffuse to the lower part of the channel region, so that the source electrode and the drain electrode in the source-drain doping layer keep a far distance, and the doping region enables the depletion layer of the source-drain doping layer to be difficult to expand when the semiconductor structure works, so that the potential barrier introduced by the drain electrode in the source-drain doping layer is difficult to reduce, the sub-threshold swing amplitude is difficult to improve, the short channel effect is further reduced, and the electrical property of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that a sub-threshold leakage (SCE) phenomenon, which is a so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize electrical properties of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, for forming a first type transistor, including: providing a substrate; forming a gate structure on the substrate, wherein the substrate below the gate structure is used as a channel region; forming grooves in the substrate on two sides of the grid structure; forming a doped region at the position of the bottom of the groove close to the channel region and in the substrate below the channel region, wherein the doped region contains second type ions, and the type of the second type ions is different from that of the first type transistor; and forming a source drain doping layer in the groove after the doping region is formed.
Optionally, the second type ions are doped in the trench at a position close to the gate structure by ion implantation to form a doped region.
Optionally, when the semiconductor structure is used to form an NMOS, the process parameters of the second type ion implantation include: the second type of ions comprises: one or more of boron, gallium and indium; the implantation energy is 0.5Kev to 1.5 Kev; the implantation dosage of the second type ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees; when the semiconductor structure is used for forming PMOS, the process parameters of the second type ion implantation comprise: the second type of ions comprises: one or more of phosphorus, arsenic and antimony; the implantation energy is 1Kev to 3 Kev; the implantation dose of the second type of ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter; the injection direction forms an angle of 5 to 25 degrees with the normal of the substrate.
Optionally, the step of forming the doped region further includes: doping with C and F.
Optionally, doping C and F in the trench at a position close to the gate structure by ion implantation to form a doped region.
Optionally, the process parameters for doping C in the doped region include: the implantation energy is 1Kev to 3 Kev; the implantation dosage of the ions is 1E14 atoms per square centimeter to 5E14 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees; the process parameters for doping F in the doped region comprise: the implantation energy is 2Kev to 4 Kev; the implantation dosage of the ions is 3E14 atoms per square centimeter to 1E15 atoms per square centimeter, and the implantation direction forms an included angle of 5 degrees to 25 degrees with the normal line of the substrate.
Optionally, after the forming of the doped region, before forming the source-drain doped layer, the method further includes: and annealing the doped region.
Optionally, the annealing treatment includes a first annealing process and a second annealing process, and the temperature of the second annealing process is higher than that of the first annealing process; a first annealing process for repairing the lattice defect; and a second annealing process for activating the ions.
Optionally, the process parameters of the first annealing process include: the annealing temperature is 400 ℃ to 600 ℃; the annealing time is 10 minutes to 30 minutes.
Optionally, a spike anneal or a laser anneal is used to perform the second annealing process.
Optionally, the base includes a substrate and a fin portion located on the substrate; the step of forming the trench includes: forming the grooves in the fin parts on two sides of the grid structure; in the step of forming the doped region, the doped region is formed at a position of the bottom of the trench close to the channel region and in the fin portion under the channel region.
Optionally, in the step of forming the doped region, a distance between the top surface of the doped region and the top surface of the fin portion is greater than one quarter of the height of the fin portion and less than or equal to one half of the height of the fin portion.
Optionally, when the semiconductor structure is used for forming an NMOS, the material of the source-drain doping layer includes one or more of Si, SiP, and SiC; when the semiconductor structure is used for forming PMOS, the material of the source-drain doping layer comprises one or two of Si and SiGe.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, which is a first type transistor, including: a substrate; the grid structure is positioned on the substrate; the source-drain doping layers are positioned in the substrate on two sides of the grid structure; the channel region is positioned in the substrate below the grid structure and is positioned between the source-drain doped layers; and the doped region is positioned in the substrate below the channel region and the bottom of the source drain doped layer is close to the substrate of the grid structure, and the doped region contains second type ions which are different from the type of the doped ions of the first type transistor.
Optionally, when the first type transistor is an NMOS, the second type ions include: one or more of boron, gallium and indium; the second type ion concentration is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter; when the first type transistor is a PMOS, the second type ions comprise: one or more of phosphorus, arsenic and antimony; the second type of ion concentration is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.
Optionally, the doped region is further doped with C and F.
Optionally, the doping concentration of C is 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter; the doping concentration of F is 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.
Optionally, the base includes a substrate and a fin portion located on the substrate; the source-drain doped layers are positioned in the fin parts on two sides of the gate structure; the doped region is located in the fin part below the grid structure, the fin part at the bottom of the source-drain doped layer and the fin part close to the grid structure.
Optionally, a distance between the top surface of the doped region and the top surface of the fin portion is greater than one fourth of the height of the fin portion and less than or equal to one half of the height of the fin portion.
Optionally, when the semiconductor structure is an NMOS, the material of the source-drain doped layer includes one or more of Si, SiP, and SiC; when the semiconductor structure is PMOS, the material of the source-drain doped layer comprises one or two of Si and SiGe.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, a gate structure is formed on a substrate, the substrate below the gate structure is used as a channel region, and grooves are formed in the substrate at two sides of the gate structure; forming a doped region at the position of the bottom of the groove close to the channel region and in the substrate below the channel region, wherein the doped region contains second type ions, and the type of the second type ions is different from that of the first type transistor; and forming a source drain doping layer in the groove after the doping region is formed. Compared with the situation that a doped region is not formed, the doped region enables doped ions in the source and drain doped layers to be difficult to diffuse below the channel region, so that a source electrode and a drain electrode in the source and drain doped layers keep a far distance, and when the semiconductor structure works, the doped region enables a depletion layer of the source and drain doped layers to be difficult to expand, so that a potential barrier introduced by the drain electrode in the source and drain doped layers is difficult to reduce, a Subthreshold swing (Subthreshold swing) is difficult to improve, a short channel effect is further reduced, and the electrical performance of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to fig. 6 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.
Referring to fig. 1, the semiconductor structure includes: the structure comprises a substrate 1 and a fin part 2 positioned on the substrate 1; the gate structure 3 spans the fin portion 2, and the gate structure 3 covers part of the top wall and part of the side walls of the fin portion 2; and forming source drain doped regions 4 in the fin parts 2 at two sides of the grid structure 3.
With the development of a semiconductor process, the width of the gate structure 3 is smaller and smaller in a direction perpendicular to the extending direction of the gate structure 3, so that the distance between the source and drain doped regions 4 on the two sides of the gate structure 3 is smaller and smaller, and when the semiconductor structure works, the distance between channels is smaller and smaller, and the depletion layer of the source and drain doped region 4 is easy to expand, so that potential barrier introduced by a drain electrode in the source and drain doped region 4 is easy to reduce, the sub-threshold swing amplitude is easy to increase, the short channel effect is serious, and the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, for forming a first type transistor, including: providing a substrate; forming a gate structure on the substrate, wherein the substrate below the gate structure is used as a channel region; forming grooves in the substrate on two sides of the grid structure; forming a doped region at the position of the bottom of the groove close to the channel region and in the substrate below the channel region, wherein the doped region contains second type ions, and the type of the second type ions is different from that of the first type transistor; and forming a source drain doping layer in the groove after the doping region is formed.
According to the embodiment of the invention, a gate structure is formed on a substrate, the substrate below the gate structure is used as a channel region, and grooves are formed in the substrate at two sides of the gate structure; forming a doped region at the position of the bottom of the groove close to the channel region and in the substrate below the channel region, wherein the doped region contains second type ions, and the type of the second type ions is different from that of the first type transistor; and forming a source drain doping layer in the groove after the doping region is formed. Compared with the situation that a doped region is not formed, the doped region enables doped ions in the source and drain doped layers to be difficult to diffuse below the channel region, so that a source electrode and a drain electrode in the source and drain doped layers keep a far distance, and when the semiconductor structure works, the doped region enables a depletion layer of the source and drain doped layers to be difficult to expand, so that a potential barrier introduced by the drain electrode in the source and drain doped layers is difficult to reduce, the sub-threshold swing amplitude is difficult to improve, the short channel effect is reduced, and the electrical performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 2 to 6 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
A substrate (not shown) is provided.
The substrate provides a process platform for the subsequent formation of a semiconductor structure, the subsequently formed semiconductor structure is a first type transistor, the first type transistor comprises a source-drain doping layer, and first type ions are doped in the source-drain doping layer.
In the embodiment, the formed semiconductor structure is a fin field effect transistor (FinFET), and the base includes a substrate 100 and a fin 101 on the substrate 100. In other embodiments, the formed semiconductor structure may also be a planar structure.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
Fin 101 is used to subsequently provide a channel region of a finfet.
In this embodiment, the fin 101 and the substrate 100 are formed by etching the same semiconductor layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving the purpose of precisely controlling the height of the fin.
Therefore, in the present embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming the fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may also be different from that of the substrate.
As shown in fig. 3, a gate structure 102 is formed on the substrate, and the substrate under the gate structure 102 is used as a channel region 107.
The channel region 107 serves as a channel during operation of the semiconductor structure. The gate structure 102 is used to open or close a channel during operation of the semiconductor structure.
Specifically, the gate structure 102 crosses over the fin 101, and the gate structure 102 covers a portion of the top wall and a portion of the sidewall of the fin 101. The region of the fin 101 covered by the gate structure 102 in the fin 101 serves as a channel region 107.
In this embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide layer 1021 and a gate layer 1022 located on the gate oxide layer 1021. In other embodiments, the gate structure may also be a single layer structure, i.e., the gate structure includes only a gate layer.
In this embodiment, the gate oxide layer 1021 is made of silicon oxide. The silicon oxide is a dielectric material which is commonly used in the process and has lower cost, has higher process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the gate oxide layer 1021.
In this embodiment, the gate layer 1022 is polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
The step of forming the gate structure 102 includes: forming a gate oxide material layer (not shown) conformally covering the fin portion 101; forming a gate material layer (not shown in the figure) on the gate oxide material layer, wherein the top surface of the gate material layer is higher than the top surface of the fin portion 101; forming a mask layer 103 on the gate material layer; and etching the gate oxide material layer and the gate material layer by taking the mask layer 103 as a mask, wherein the rest gate oxide material layer and the rest gate material layer are taken as a gate structure 102.
The method for forming the semiconductor structure further comprises the following steps: after the gate structure 102 is formed, a sidewall layer 108 is formed on the sidewall of the gate structure 102.
During the subsequent formation of trenches in the substrate on both sides of the gate structure 102, the sidewall layer 108 protects the gate structure 102.
Referring to fig. 4, trenches 104 are formed in the substrate on both sides of the gate structure 102.
The trench 104 provides a space for the subsequent formation of a source-drain doped layer.
Specifically, the trenches 104 are formed in the fin 101 on two sides of the gate structure 102.
In this embodiment, the trench 104 is formed by a dry etching process. The dry etching process is an anisotropic etching process, has good etching profile controllability, is beneficial to reducing damage to other film layer structures, and enables the quality of the formed groove 104 to be high, and the removal efficiency of the fin part 101 material in the dry etching process enables the forming speed of the groove 104 to be high.
In other embodiments, the trench may be formed by a wet etching process. The wet etching process is isotropic etching, has high etching rate, and is simple to operate and low in process cost.
Referring to fig. 5, a doped region 105 is formed in the substrate at the bottom of the trench 104 near the channel region 107 and under the channel region 107, the doped region 105 contains a second type of ions, and the second type of ions is different from the type of ions doped in the first type of transistor.
In this embodiment, the fact that the second type ions are different from the type of the doping ions of the first type transistor means that the second type ions are different from the type of the doping ions of the source-drain doping layer formed in the trench 104 subsequently, therefore, the doping region 105 makes the doping ions in the source-drain doping layer not easily diffuse below the channel region 107, so that the source and the drain in the source-drain doping layer keep a longer interval, and when the semiconductor structure works, the depletion layer of the source-drain doping layer is not easily expanded by the doping region 105, so that the potential barrier introduced by the drain in the source-drain doping layer is not easily reduced, the sub-threshold swing is not easily increased, the short channel effect is reduced, and the electrical performance of the semiconductor structure is improved.
Specifically, the doped region 105 is formed at the bottom of the trench 104 near the channel region 107 and in the fin 101 below the channel region 107.
In this embodiment, the second type of ions are doped in the trench 104 near the gate structure 102 by ion implantation to form a doped region 105.
Specifically, after the second type ions are implanted, the second type ions are diffused in a direction perpendicular to the extending direction of the gate structure 102 to form the doped region 105.
It should be noted that, in a direction parallel to the normal of the surface of the substrate 100, the distance between the top surface of the doped region 105 and the top surface of the fin 101 is not too close or too far. If the distance is too close, the gate structure 102 may cover the doped region 105 too much, and carriers in the channel may be scattered easily during operation of the semiconductor structure, resulting in a low carrier mobility rate. If the distance is too far, in the extending direction perpendicular to the gate structure 102, the doped region 105 is not easy to block doped ions in a subsequently formed source-drain doped layer from diffusing below the channel region 107, so that the source and drain in the source-drain doped layer are not easy to keep a farther interval, and when the semiconductor structure works, the effect of the doped region 105 on inhibiting the depletion layer of the source-drain doped layer from expanding is not significant, so that the potential barrier introduced by the drain in the source-drain doped layer is obviously reduced, the subthreshold swing is obviously improved, the short channel effect is serious, and the electrical performance of the semiconductor structure is not improved. In this embodiment, in the step of forming the doped region 105, a distance between the top surface of the doped region 105 and the top surface of the fin 101 is greater than one fourth of the height of the fin 101 and less than or equal to one half of the height of the fin 101.
In this embodiment, when the first type transistor is an NMOS, the second type ions include: one or more of boron, gallium and indium.
It should be noted that the implantation dose of the second type of ions is not too large or too small. If the implantation dose of the second type ions is too large, the concentration of the second type ions in the formed doped region 105 is too large, the second type ions are easy to diffuse into the channel region 107, and when the semiconductor structure works, carriers in the channel are easy to scatter, so that the migration rate of the carriers is not high. If the implantation dose of the second type ions is too small, the concentration of the second type ions in the doped region 105 is easily caused to be too small, so that the formation quality of the doped region 105 is poor, the doped region 105 is not easy to block doped ions in a subsequently formed source-drain doped layer from diffusing to the lower side of the channel region 107, so that a source electrode and a drain electrode in the source-drain doped layer are not easy to keep a farther interval, and when the semiconductor structure works, the effect of the doped region 105 in inhibiting the expansion of a depletion layer of the source-drain doped layer is not significant, so that the potential barrier introduced by the drain electrode in the source-drain doped layer is obviously reduced, the subthreshold swing amplitude is obviously improved, the short channel effect is serious, and the electrical performance of the semiconductor structure. In this embodiment, the implantation dose of the second type of ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter.
It should be noted that the implantation energy of the second type of ions should not be too large or too small. If the injection energy of the second type ions is too large, the lattice damage of the fin portion 101 of the channel region 107 is large in the process of forming the doped region 105, when the semiconductor structure works, the carrier migration rate in the channel is not high, and if the injection energy is too large, the formed doped region 105 is easily far away from the channel region 107, when the semiconductor structure works, the effect of the doped region 105 in inhibiting the depletion layer of the source-drain doped layer 106 from expanding is not significant, so that the potential barrier introduced by the drain electrode in the source-drain doped layer is obviously reduced, the subthreshold swing amplitude is obviously improved, the short channel effect is further serious, and the electrical performance of the semiconductor structure is not improved. If the injection energy of the second type ions is too small, the second type ions are easily caused to be located on the surface of the trench 104, and further the second type doping concentration in the doping region 105 below the channel region 107 is too low, when the semiconductor structure works, the depletion layer of the source and drain doping layer is not easily expanded by the doping region 105, so that the potential barrier introduced by the drain electrode in the source and drain doping layer is obviously reduced, the sub-threshold swing amplitude is obviously improved, further the short channel effect is serious, and the electrical performance of the semiconductor structure is not favorably improved. In this embodiment, the implantation energy is 0.5Kev to 1.5 Kev.
It should be noted that the angle between the implantation direction of the second type ions and the normal of the substrate is not too large, specifically, the angle between the implantation direction of the second type ions and the normal of the substrate 100 is not too large. If the included angle is too large, the second type ions are likely to enter the channel region 107 too much, and when the semiconductor structure works, the problem of carrier scattering is likely to occur in the channel, so that the migration rate of carriers is not high. If the included angle is too small, the second type ions are prone to diffusing below the channel region 107, doped ions in a subsequently formed source-drain doped layer are prone to diffusing below the channel region 107, the doped region 105 is prone to enabling a source electrode and a drain electrode in the source-drain doped layer to keep a longer interval, when the semiconductor structure works, the effect that the doped region 105 inhibits the depletion layer of the source-drain doped layer 106 from expanding is not significant, and therefore the potential barrier introduced by the drain electrode in the source-drain doped layer is significantly reduced and the sub-threshold swing amplitude is significantly improved, the short channel effect is severe, and the electrical performance of the semiconductor structure is not improved. In this embodiment, the angle between the implantation direction of the second type ions and the normal of the substrate 100 is 5 to 25 degrees.
In other embodiments, when the semiconductor structure is used to form a PMOS, the process parameters of the second type ion implantation include: the second type of ions comprises: one or more of phosphorus, arsenic and antimony; the implantation energy is 1Kev to 3 Kev; the implantation dose of the second type of ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter; the injection direction forms an angle of 5 to 25 degrees with the normal of the substrate.
The method for forming the semiconductor structure further comprises the following steps: the step of forming the doped region 105 further comprises: after doping with ions of the second type, C and F are doped.
Lattice defects are generated in the process of forming the doped region 105, the C ions are formed at the lattice defects, so that the doped ions in the source and drain doped layers are not easy to diffuse in the direction perpendicular to the extension direction of the gate structure 102, when the semiconductor structure works, the depletion layer of the source and drain doped layers is not easy to expand by the doped region 105, the potential barrier introduced by the drain in the source and drain doped layers is not easy to reduce, the sub-threshold swing amplitude is not easy to improve, the short channel effect is reduced, and the electrical performance of the semiconductor structure is improved.
In this embodiment, C ions are doped in the trench 104 near the gate structure 102 by ion implantation.
It should be noted that the included angle between the C ion implantation direction and the normal of the substrate is not too large or too small, specifically, the included angle with the normal of the substrate 100. If the included angle is too large, too many C ions are likely to enter the channel region 107, and the mobility rate of carriers is not high when the semiconductor structure operates. If the included angle is too small, too many C ions are easily injected into the bottom of the trench 104, and too few C ions located on the side wall of the trench 104 cause too few C ions diffused into the bottom of the channel region 107, the formation quality of the doped region 105 is poor, the doped region 105 does not easily block doped ions in a subsequently formed source and drain doped layer from diffusing below the channel region 107, so that the distance between a source electrode and a drain electrode in the source and drain doped layer is relatively short, and when the semiconductor structure works, the effect of the doped region 105 on inhibiting the expansion of a depletion layer of the source and drain doped layer 106 is not significant, so that the potential barrier introduced by the drain electrode in the source and drain doped layer is significantly reduced, the subthreshold value is significantly improved, the short channel effect is severe, and the electrical performance of the semiconductor structure is not favorably improved. In this embodiment, an included angle between the implantation direction of the C ions and the normal line of the substrate is 5 to 25 degrees.
The injection energy of C ions should not be too large or too small. If the injection energy of the C ions is too large, the lattice damage of the fin 101 in the channel region 107 is large in the process of forming the doped region 105, and the subsequent annealing process is difficult to repair, so that the carrier migration rate in the channel is not high when the semiconductor structure works, and if the injection energy is too large, the C ions are likely to penetrate through the gate structure 102 and enter the channel region 107, and the carrier migration rate is not high when the semiconductor structure works, so that the electrical performance of the semiconductor structure is not good. If the injection energy of the C ions is too small, the C ions are easily translocated on the surface of the trench 104, and further the doping concentration of the C ions below the channel region 107 is too low, when the semiconductor structure works, the doping region 105 is not easy to block the doped ions in the source-drain doping layer from diffusing below the channel region 107, so that the distance between the source and the drain in the source-drain doping layer is relatively short, and when the semiconductor structure works, the depletion layer of the source-drain doping layer is easy to expand, so that the potential barrier introduced by the drain in the source-drain doping layer is significantly reduced, the sub-threshold swing amplitude is significantly increased, and further the short channel effect is relatively serious, and the improvement of the electrical performance of the semiconductor. In this embodiment, the implantation energy of C ions is 1Kev to 3 Kev.
It should be noted that the implantation dose of C ions is not too large or too small. If the implantation dose of the C ions is too large, the doping concentration of the C ions is easily too large, which may cause the C ions to diffuse into the channel region 107, and when the semiconductor works, the mobility rate of carriers is not high, and the leakage current of a junction (junction) formed by a source-drain doping layer and the doping region 105, which are formed subsequently, is also easily increased. If the implantation dose of the C ions is too small, the doping concentration of the C ions in the doping region 105 is easily too small, the doping region 105 is not easy to block doped ions in a subsequently formed source-drain doping layer from diffusing below the channel region 107, so that the distance between a source electrode and a drain electrode in the source-drain doping layer is relatively short, and thus when the semiconductor structure works, the effect of the doping region 105 on inhibiting the expansion of a depletion layer of the source-drain doping layer 106 is not significant, so that the potential barrier introduced by the drain electrode in the source-drain doping layer is significantly reduced, the sub-threshold swing amplitude is significantly improved, the short channel effect is relatively serious, and the improvement of the electrical performance of the semiconductor structure is not facilitated. In this embodiment, the implantation dose of C ions is 1E14 atoms per square centimeter to 5E14 atoms per square centimeter.
The F ions also occupy lattice defects generated in the process of forming the doped region 105, and block the doped ions in the source and drain doped layers from diffusing in the direction perpendicular to the extension direction of the gate structure 102, so that when the semiconductor structure works, the doped region 105 makes a depletion layer of the source and drain doped layers not easily expand, a potential barrier introduced by a drain in the source and drain doped layers not easily decrease, and a subthreshold swing not easily increase, thereby reducing a short channel effect and improving the electrical performance of the semiconductor structure.
It should be noted that the included angle between the F ion implantation direction and the substrate normal is not too large or too small. In this embodiment, an included angle between the F ion implantation direction and the normal line of the substrate is 5 to 25 degrees. Specifically, reference is made to the description of the implantation direction of C ions, which is not repeated herein.
It should be noted that the implantation energy of the F ions is not preferably too large or too small. In this embodiment, the implantation energy of the F ions is 2Kev to 4 Kev. Specifically, reference is made to the description of the implantation energy of C ions, which is not repeated herein.
It should be noted that the implantation dose of F ions is not too large or too small. In this embodiment, the implantation dose of the ions is 3E14 atoms per square centimeter to 1E15 atoms per square centimeter. Specifically, reference is made to the description of the implantation dose of C ions, which is not repeated herein.
It should be noted that, in the semiconductor process, hydrogen ions are the most common impurities, and the doped F ions can replace the hydrogen ions to form stable silicon-fluorine bonds, so that interface trap charges are not easily formed, thereby enhancing the stability of the interface structure, improving the negative bias temperature instability effect of the semiconductor device to the maximum extent, and further prolonging the service life of the semiconductor device.
In other embodiments, the method for forming the semiconductor structure may further include: doping C and F, and then doping the second type ions.
The method for forming the semiconductor structure further comprises the following steps: after the doped region 105 is formed, before forming a source-drain doped layer, the method further includes: the doped region 105 is annealed.
The annealing treatment comprises a first annealing process and a second annealing process, and the temperature of the second annealing process is higher than that of the first annealing process; a first annealing process for repairing the lattice defect; and a second annealing process for activating the ions.
The first annealing process is used to repair lattice defects, so that C, F and second type ions in the doped region 105 are not prone to Transient Enhanced Diffusion (TED) in the formed lattice defects, and the doped ions are not prone to diffuse into the channel region 107, thereby not prone to affect the mobility rate of carriers.
It should be noted that the annealing temperature of the first annealing process is not too high nor too low. If the annealing temperature is too high, the lattice defect generated in the ion implantation process cannot be well repaired, and the doped ions are easily diffused into the channel region 107 through the lattice defect, so that carriers in the channel are easily scattered when the semiconductor structure works. If the annealing temperature is too low, the rate of repairing the lattice defects is too slow, the process time is too long, and the process defects are difficult to control. In this embodiment, the annealing temperature of the first annealing process is 400 ℃ to 600 ℃.
It should be noted that the annealing time is not too long nor too short. If the annealing time is too long, thermal budget and process cost are easily increased, and doped ions are easily diffused into the channel region 107, so that the mobility rate of carriers is reduced when the semiconductor structure works, and the leakage current of a junction (junction) formed by a subsequently formed source/drain doped layer and the doped region 105 is increased. If the annealing time is too short, lattice defects generated in the ion implantation process are not completely repaired, so that the doped ions in the doped region 105 are easily diffused into the channel region 107, and the carrier migration rate in the channel is not high when the semiconductor structure works. In this example, the annealing time was 10 minutes to 30 minutes.
In this embodiment, the second annealing process is performed by spike annealing or laser annealing. Spike annealing processes and laser annealing processes are common annealing processes in the semiconductor field, and are beneficial to improving process compatibility.
The temperature of the second annealing process is high, so that the doped ions in the doped region 105 can be activated, and because the time of the second annealing process is short, the doped ions in the doped region 105 are not easy to diffuse into the fin 101 below the gate structure 102, so that the electric field intensity below the gate structure 102 is not easy to be too strong and the gate structure 102 is not easy to be damaged when the subsequent semiconductor structure works.
It should be noted that the second annealing process can also repair lattice defects.
Referring to fig. 6, after the doped region 105 is formed, a source-drain doped layer 106 is formed in the trench 104 (shown in fig. 4).
When the semiconductor structure works, the source-drain doping layer 106 provides stress for a channel, so that the migration rate of carriers is higher.
In this embodiment, when the semiconductor structure is used to form an nmos (negative channel Metal Oxide semiconductor), the material of the source-drain doping layer 106 includes one or more of Si, SiP, and SiC. Specifically, the source-drain doping layer 106 is further doped with N-type ions, the N-type ions replace positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. The N-type ions are phosphorus, arsenic or antimony.
In other embodiments, when the semiconductor structure is used to form a pmos (positive Channel Metal Oxide semiconductor), the material of the source-drain doping layer includes one or both of Si and SiGe. Specifically, the source-drain doping layer is further doped with P-type ions, the P-type ions replace positions of silicon atoms in the crystal lattice, the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. The P-type ions are boron, gallium or indium.
The step of forming the source-drain doping layer 106 includes: and epitaxially growing in the groove 104 to form an epitaxial layer, carrying out in-situ doping in the epitaxial growth process of the epitaxial layer, and forming a source-drain doping layer 106 in the groove 104. In other embodiments, an epitaxial layer is formed in the trench by an epitaxial growth process; and carrying out ion doping on the epitaxial layer to form the source-drain doping layer 106.
In this embodiment, an epitaxial layer is formed in the trench 104 by a selective epitaxial growth method. The film obtained by the selective epitaxial growth method has high purity and few defects, and is beneficial to improving the formation quality of an epitaxial layer, thereby being beneficial to optimizing the electrical performance of a semiconductor structure. In other embodiments, the epitaxial layer may be formed by Chemical Vapor Deposition (CVD).
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 6, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure is a first type transistor, the semiconductor structure comprising: a substrate; a gate structure 102 on the substrate; the source-drain doping layer 106 is positioned in the substrate on two sides of the gate structure 102; a channel region 107, located in the substrate below the gate structure 102, and the channel region 107 is located between the source-drain doping layers 106; the doped region 105 is located in the substrate below the channel region 107, and the bottom of the source-drain doped layer 106 is close to the substrate of the gate structure 102, the doped region 105 contains second type ions, and the type of the second type ions is different from that of the first type ions of the transistor.
In the embodiment of the present invention, the doped region 105 contains second type ions, and the second type ions are different from the doped ion type of the first type transistor, in other words, the second type ions are different from the doped ion type of the source drain doped layer 106. The doping region 105 enables doping ions in the source-drain doping layer 106 to be difficult to diffuse below the channel region 107, so that a source electrode and a drain electrode in the source-drain doping layer 106 keep a far distance, and when the semiconductor structure works, the depletion layer of the source-drain doping layer 106 is difficult to expand by the doping region 105, so that a potential barrier introduced by the drain electrode in the source-drain doping layer 106 is difficult to reduce, the sub-threshold swing amplitude is difficult to improve, the short channel effect is reduced, and the electrical performance of the semiconductor structure is improved.
The substrate provides a process platform for forming a semiconductor structure, the semiconductor structure is a first type transistor, the first type transistor comprises a source-drain doping layer 106, and first type ions are doped in the source-drain doping layer 106.
In this embodiment, the formed semiconductor structure is a finfet, and the substrate includes a substrate 100 and a fin 101 located on the substrate 100. In other embodiments, the formed semiconductor structure may also be a planar structure.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 101 and the substrate 100 are formed by etching the same semiconductor layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving the purpose of precisely controlling the height of the fin.
Therefore, in the present embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming the fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may also be different from that of the substrate.
The gate structure 102 is used to open or close a channel during operation of the semiconductor structure.
Specifically, the gate structure 102 crosses over the fin 101, and the gate structure 102 covers a portion of the top wall and a portion of the sidewall of the fin 101.
In this embodiment, the gate structure 102 is a stacked structure. Specifically, the gate structure 102 includes a gate oxide layer 1021 and a gate layer 1022 located on the gate oxide layer 1021. In other embodiments, the gate structure may also be a single layer structure, i.e., the gate structure includes only a gate layer.
In this embodiment, the gate oxide layer 1021 is made of silicon oxide. The silicon oxide is a dielectric material which is commonly used in the process and has lower cost, has higher process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the gate oxide layer 1021.
In this embodiment, the gate layer 1022 is polysilicon. In other embodiments, the material of the gate layer may also be amorphous carbon.
The semiconductor structure further includes: and a sidewall layer 108 located on a sidewall of the gate structure 102.
The source-drain doping layer 106 is formed in the recess 104 (as shown in fig. 5), and the sidewall layer 108 protects the gate structure 102 during the formation of the recess 104.
And the channel region 107 is positioned in the fin portion 101 below the gate structure 102, and the channel region 107 is positioned between the source-drain doping layers 106. The channel region 107 serves as a channel during operation of the semiconductor structure.
When the semiconductor structure works, the source-drain doping layer 106 provides stress for a channel, so that the migration rate of carriers is higher.
Specifically, the source-drain doping layer 106 is located in the fin portion 101 on two sides of the gate structure 102.
In this embodiment, when the semiconductor structure is an NMOS, the material of the source-drain doping layer 106 includes one or more of Si, SiP, and SiC. Specifically, N-type ions are further doped in the source-drain doped layer 106, the N-type ions replace positions of silicon atoms in the crystal lattice, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. The N-type ions are phosphorus, arsenic or antimony.
In other embodiments, when the semiconductor structure is a PMOS, the material of the source-drain doped layer includes one or both of Si and SiGe. Specifically, the source-drain doped layer is also doped with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice, the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. The P-type ions are boron, gallium or indium.
In this embodiment, when the first type transistor is an NMOS, the second type ions include: one or more of boron, gallium and indium.
It should be noted that the concentration of the second type ion should not be too high nor too low. If the concentration of the second type ions is too high, the second type ions are easily diffused into the channel region 107, and carriers in the channel are easily scattered when the semiconductor structure works, so that the migration rate of the carriers is not high. If the second type ion concentration is too low, the formation quality of the doped region 105 is poor, the doped region 105 does not easily block the doped ions in the source-drain doped layer 106 from diffusing to the lower side of the channel region 107, so that the source electrode and the drain electrode in the source-drain doped layer 106 are not easily kept at a longer interval, and when the semiconductor structure works, the effect of the doped region 105 on inhibiting the depletion layer expansion of the source-drain doped layer 106 is not significant, so that the potential barrier introduced by the drain electrode in the source-drain doped layer 106 is obviously reduced and the subthreshold swing amplitude is obviously improved, further the short channel effect is serious, and the electrical performance of the semiconductor structure is not improved. In this embodiment, the concentration of the second type of ions is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.
In other embodiments, when the first type transistor is a PMOS, the second type ions include: one or more of phosphorus, arsenic and antimony; the second type of ion concentration is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.
In this embodiment, the doped region is further doped with C and F.
Lattice defects are generated in the process of forming the doped region 105, the C ions are located at the lattice defects, so that the doped ions in the source-drain doped layer 106 are not easy to diffuse in the direction perpendicular to the extension direction of the gate structure 102, when the semiconductor structure works, the depletion layer of the source-drain doped layer 106 is not easy to expand due to the doped region 105, the potential barrier introduced by the drain electrode in the source-drain doped layer 106 is not easy to reduce, the sub-threshold swing amplitude is not easy to improve, the short channel effect is further reduced, and the electrical performance of the semiconductor structure is improved.
It should be noted that the doping concentration of C ions is not too large or too small. If the doping concentration of the C ions is too large, the C ions are likely to diffuse into the channel region 107, so that the mobility rate of carriers is not high when the semiconductor works, and the leakage current of the junction formed by the source/drain doping layer 106 and the doping region 105 is likely to increase. If the doping concentration of the C ions is too low, the doping region 105 does not easily block the diffusion of the doping ions in the source-drain doping layer 106 to the lower side of the channel region 107, so that the distance between the source and the drain in the source-drain doping layer 106 is relatively short, and thus when the semiconductor structure works, the effect of the doping region 105 on inhibiting the expansion of the depletion layer of the source-drain doping layer 106 is not significant, so that the potential barrier introduced by the drain in the source-drain doping layer 106 is significantly reduced and the sub-threshold swing amplitude is significantly improved, further the short channel effect is severe, and the electrical performance of the semiconductor structure is not improved. In the present embodiment, the doping concentration of the C ions is 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter.
It should be noted that the doping concentration of F is not too large or too small. In this example, the doping concentration of F is 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter. Specifically, the description of the doping concentration of the doped C ions is not repeated herein.
It should be noted that, in the semiconductor process, hydrogen ions are the most common impurities, and the doped F ions can replace the hydrogen ions to form stable silicon-fluorine bonds, so that interface trap charges are not easily formed, thereby enhancing the stability of the interface structure, improving the negative bias temperature instability effect of the semiconductor device to the maximum extent, and further prolonging the service life of the semiconductor device.
The doped region 105 is located in the fin 101 below the channel region 107, and the bottom of the source-drain doped layer 106 is close to the fin 101 of the gate structure 102.
It should be noted that, in a direction parallel to the normal of the surface of the substrate 100, the distance between the top surface of the doped region 105 and the top surface of the fin 101 is not too close or too far. If the distance is too close, the gate structure 102 may cover the doped region 105 too much, and carriers in the channel may be scattered easily during operation of the semiconductor structure, resulting in a low carrier mobility rate. If the distance is too far, in the extending direction perpendicular to the gate structure 102, the doped region 105 is not easy to block doped ions in the source-drain doped layer 106 from diffusing below the channel region 107, so that the source and the drain in the source-drain doped layer 106 are not easy to keep a longer interval, and when the semiconductor structure works, the effect of the doped region 105 on inhibiting the depletion layer of the source-drain doped layer 106 from expanding is not significant, so that the potential barrier introduced by the drain in the source-drain doped layer 106 is obviously reduced and the subthreshold swing is obviously improved, further the short channel effect is serious, and the electrical performance of the semiconductor structure is not improved. In this embodiment, the distance between the top surface of the doped region 105 and the top surface of the fin 101 is greater than one quarter of the height of the fin 101 and less than or equal to one half of the height of the fin 101.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (20)

1. A method of forming a semiconductor structure for forming a transistor of a first type, comprising:
providing a substrate;
forming a gate structure on the substrate, wherein the substrate below the gate structure is used as a channel region;
forming grooves in the substrate on two sides of the grid structure;
forming a doped region at the position of the bottom of the groove close to the channel region and in the substrate below the channel region, wherein the doped region contains second type ions, and the type of the second type ions is different from that of the first type transistor;
and forming a source drain doping layer in the groove after the doping region is formed.
2. The method as claimed in claim 1, wherein the doping region is formed by doping ions of the second type in the trench at a position close to the gate structure by ion implantation.
3. The method of claim 2, wherein the process parameters of the second type ion implantation comprise, when the semiconductor structure is used to form an NMOS: the second type of ions comprises: one or more of boron, gallium and indium; the implantation energy is 0.5Kev to 1.5 Kev;
the implantation dosage of the second type ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees;
when the semiconductor structure is used for forming PMOS, the process parameters of the second type ion implantation comprise: the second type of ions comprises: one or more of phosphorus, arsenic and antimony; the implantation energy is 1Kev to 3 Kev; the implantation dose of the second type of ions is 5E12 atoms per square centimeter to 3E13 atoms per square centimeter; the injection direction forms an angle of 5 to 25 degrees with the normal of the substrate.
4. The method of forming a semiconductor structure of claim 1, wherein the step of forming the doped region further comprises: doping with C and F.
5. The method as claimed in claim 4, wherein the doping region is formed by doping C and F in the trench at a position close to the gate structure by ion implantation.
6. The method of claim 4, wherein the process parameters for doping C in the doped region comprise: the implantation energy is 1Kev to 3 Kev; the implantation dosage of the ions is 1E14 atoms per square centimeter to 5E14 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees;
the process parameters for doping F in the doped region comprise: the implantation energy is 2Kev to 4 Kev; the implantation dosage of the ions is 3E14 atoms per square centimeter to 1E15 atoms per square centimeter, and the implantation direction forms an included angle of 5 degrees to 25 degrees with the normal line of the substrate.
7. The method for forming a semiconductor structure according to claim 1, wherein after forming the doped region and before forming the source-drain doped layer, the method further comprises: and annealing the doped region.
8. The method of claim 7, wherein the annealing process comprises a first annealing process and a second annealing process, and the second annealing process has a temperature higher than a temperature of the first annealing process;
a first annealing process for repairing the lattice defect;
and a second annealing process for activating the ions.
9. The method of forming a semiconductor structure of claim 8, wherein the process parameters of the first annealing process comprise: the annealing temperature is 400 ℃ to 600 ℃; the annealing time is 10 minutes to 30 minutes.
10. The method of claim 1, wherein the second annealing process is performed using a spike anneal or a laser anneal.
11. The method of claim 1, wherein the base comprises a substrate and a fin on the substrate;
the step of forming the trench includes: forming the grooves in the fin parts on two sides of the grid structure;
in the step of forming the doped region, the doped region is formed at a position of the bottom of the trench close to the channel region and in the fin portion under the channel region.
12. The method of forming a semiconductor structure of claim 11, wherein in the step of forming a doped region, a distance between a top surface of the doped region and a top surface of the fin is greater than one quarter of the height of the fin and less than or equal to one half of the height of the fin.
13. The method for forming a semiconductor structure according to claim 1, wherein when the semiconductor structure is used for forming an NMOS, the material of the source-drain doping layer comprises one or more of Si, SiP, and SiC;
when the semiconductor structure is used for forming PMOS, the material of the source-drain doping layer comprises one or two of Si and SiGe.
14. A semiconductor structure being a transistor of a first type, comprising:
a substrate;
the grid structure is positioned on the substrate;
the source-drain doping layers are positioned in the substrate on two sides of the grid structure;
the channel region is positioned in the substrate below the grid structure and is positioned between the source-drain doped layers;
and the doped region is positioned in the substrate below the channel region and the bottom of the source drain doped layer is close to the substrate of the grid structure, and the doped region contains second type ions which are different from the type of the doped ions of the first type transistor.
15. The semiconductor structure of claim 14, wherein when the first type transistor is an NMOS, the second type ions comprise: one or more of boron, gallium and indium; the second type ion concentration is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter;
when the first type transistor is a PMOS, the second type ions comprise: one or more of phosphorus, arsenic and antimony; the second type of ion concentration is from 5E17 atoms per cubic centimeter to 3E18 atoms per cubic centimeter.
16. The semiconductor structure of claim 14, wherein said doped region is further doped with C and F.
17. The semiconductor structure of claim 16,
the doping concentration of C is 1E19 atoms per cubic centimeter to 5E19 atoms per cubic centimeter;
the doping concentration of F is 3E19 atoms per cubic centimeter to 1E20 atoms per cubic centimeter.
18. The semiconductor structure of claim 14, wherein the base comprises a substrate and a fin on the substrate;
the source-drain doped layers are positioned in the fin parts on two sides of the gate structure;
the doped region is located in the fin part below the grid structure, the fin part at the bottom of the source-drain doped layer and the fin part close to the grid structure.
19. The semiconductor structure of claim 18, wherein a distance between a top surface of the doped region and a top surface of the fin is greater than one quarter of the height of the fin and less than or equal to one half of the height of the fin.
20. The semiconductor structure of claim 18, wherein when the semiconductor structure is an NMOS, the material of the source drain doping layer comprises one or more of Si, SiP, and SiC; when the semiconductor structure is PMOS, the material of the source-drain doped layer comprises one or two of Si and SiGe.
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CN105513968A (en) * 2014-09-26 2016-04-20 中国科学院微电子研究所 Fin field effect transistor production method
CN105575807A (en) * 2014-10-08 2016-05-11 中国科学院微电子研究所 Fin field-effect transistor and manufacturing method thereof
CN105575804A (en) * 2014-10-08 2016-05-11 中国科学院微电子研究所 Fin field-effect transistor and manufacturing method thereof
CN107045985A (en) * 2016-02-05 2017-08-15 中芯国际集成电路制造(上海)有限公司 The forming method of semiconductor structure
CN107591447A (en) * 2016-07-08 2018-01-16 中芯国际集成电路制造(上海)有限公司 The forming method of transistor
CN107785422A (en) * 2016-08-29 2018-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and its manufacture method
CN108630548A (en) * 2017-03-21 2018-10-09 中芯国际集成电路制造(上海)有限公司 Fin field effect pipe and forming method thereof

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