CN113539825B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113539825B
CN113539825B CN202010305064.8A CN202010305064A CN113539825B CN 113539825 B CN113539825 B CN 113539825B CN 202010305064 A CN202010305064 A CN 202010305064A CN 113539825 B CN113539825 B CN 113539825B
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region
forming
substrate
ions
gate structure
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CN113539825A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate for forming a transistor, wherein the substrate comprises a first region for forming a source region, a second region for forming a drain region and a preset region positioned between the first region and the second region; forming a pseudo gate structure covering a preset area on a substrate; doping the first region and the second region to form a source region and a drain region respectively; forming interlayer dielectric layers covering the source region and the drain region on two sides of the pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the interlayer dielectric layer; filling the grid electrode opening to form an initial grid electrode structure; and removing the initial gate structure with partial width adjacent to the drain region, taking the rest initial gate structure as a gate, enclosing the gate and the interlayer dielectric layer to form an isolation opening, and forming a drift region on a substrate at the bottom of the isolation opening. The embodiment of the invention is beneficial to optimizing the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
As semiconductor chips are increasingly used, the semiconductor chips are increasingly subject to electrostatic damage. In existing chip designs, electrostatic discharge (ESD, electrostatic Discharge) protection circuits are often used to reduce chip damage. The design and application of existing esd protection circuits include: grounded gate N-type field effect transistor (Gate Grounded NMOS, GGNMOS) protection circuits, silicon controlled rectifier (Silicon Controlled Rectifier, SCR) protection circuits, lateral double-diffused field effect transistor (Lateral Double Diffused MOSFET, LDMOS) protection circuits, bipolar junction transistor (Bipolar Junction Transistor, BJT) protection circuits, and the like. Among them, LDMOS are widely used for ESD protection because they can withstand higher breakdown voltages.
In order to improve the pressure resistance, a drift region is further arranged in the substrate between the source region and the drain region, and the doping concentration of the drift region is low, so that when the LDMOS is connected with high voltage, the drift region is high in resistance, the partial voltage is high, the voltage can be borne to be higher, and the pressure resistance of the LDMOS is improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the performance of an LDMOS device.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate for forming a transistor, wherein the substrate comprises a first region for forming a source region, a second region for forming a drain region and a preset region between the first region and the second region; forming a dummy gate structure covering the preset area on the substrate; doping the first region and the second region to form a source region and a drain region respectively; forming interlayer dielectric layers covering the source region and the drain region on two sides of the pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the interlayer dielectric layer; filling the grid electrode opening to form an initial grid electrode structure; and removing the initial gate structure with partial width adjacent to the drain region, taking the rest initial gate structure as a gate, enclosing the gate and the interlayer dielectric layer to form an isolation opening, and forming a drift region on a substrate at the bottom of the isolation opening.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: the substrate comprises a first region used for forming a source region, a second region used for forming a drain region and a preset region located between the first region and the second region, wherein a part of the substrate adjacent to the second region in the preset region is used for forming a drift region; the dummy gate structure is positioned on the substrate and covers the preset area; a source region in the substrate of the first region; and the drain region is positioned in the substrate of the second region.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming the semiconductor structure provided by the embodiment of the invention, the substrate comprises a first region used for forming the source region, a second region used for forming the drain region, and a preset region positioned between the first region and the second region, in the step of forming the pseudo gate structure, the pseudo gate structure covering the preset region is formed on the substrate, the process of forming the source region and the drain region comprises the step of doping the first region and the second region, the pseudo gate structure covers the preset region between the source region and the drain region, so that the probability of doping ions into the preset region is reduced, after the grid electrode is formed, the grid electrode and the interlayer dielectric layer enclose an isolation opening, and the substrate at the bottom of the isolation opening is used for forming the drift region, that is, part of the preset region is used for forming the drift region, and the doping type in the drift region is generally the same as the doping type in the source region and the drain region.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
Referring to fig. 1 to 6, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate is provided in which a well region 1 and a drift region 2 are formed adjacent to each other.
With continued reference to fig. 1, a dummy gate structure 3 is formed on the substrate, the dummy gate structure 3 covering the substrate at the junction of the well region 1 and the drift region 2.
Referring to fig. 2, in the well region 1 and the drift region 2 where the dummy gate structure 3 is exposed, a source region 4 and a drain region 5 are formed correspondingly, and a part of the drift region 2 is exposed between the drain region 5 and the dummy gate structure 3.
Referring to fig. 3, the source region 4 and the drain region 5 are ion-implanted to increase the doping concentration of the source region 4 and the drain region 5.
Referring to fig. 4, after ion implantation is performed on the source region 4 and the drain region 5, an interlayer dielectric layer 6 is formed on the exposed substrate of the dummy gate structure 3 to cover the source region 4 and the drain region 5.
Referring to fig. 5, the dummy gate structure 3 is removed, and a gate opening 7 is formed in the interlayer dielectric layer 6.
Referring to fig. 6, the gate opening 7 is filled to form a gate structure 8.
In the above forming method, a part of the drift region 2 is further exposed between the drain region 5 and the dummy gate structure 3, and the process of implanting ions into the source region 4 and the drain region 5 generally further includes a step of forming a mask for implanting ions, since a part of the drift region 2 is also exposed between the drain region 5 and the dummy gate structure 3, when an overlay shift (overlay shift) exists in the process of forming the mask, the ions are easily implanted into the drift region 2 between the dummy gate structure 3 and the drain region 5, the doping type of the ions in the drift region 2 is the same as the doping type of the implanted ions, and the ion implantation into the drift region 2 between the dummy gate structure 3 and the drain region 5 easily causes a decrease in the resistance of the drift region 2, thereby easily reducing the voltage dividing capability of the drift region 2.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first region well for forming a source region, a second region for forming a drain region and a preset region positioned between the first region and the second region; forming a dummy gate structure covering the preset area on the substrate; doping the first region and the second region to form a source region and a drain region respectively; forming interlayer dielectric layers covering the source region and the drain region on two sides of the pseudo gate structure; removing the pseudo gate structure and forming a gate opening in the interlayer dielectric layer; filling the grid electrode opening to form an initial grid electrode structure; and removing the initial gate structure with partial width adjacent to the drain region, taking the rest initial gate structure as a gate, enclosing the gate and the interlayer dielectric layer to form an isolation opening, and forming a drift region on a substrate at the bottom of the isolation opening.
In the method for forming the semiconductor structure provided by the embodiment of the invention, the substrate comprises a first region used for forming the source region, a second region used for forming the drain region, and a preset region positioned between the first region and the second region, in the step of forming the pseudo gate structure, the pseudo gate structure covering the preset region is formed on the substrate, the process of forming the source region and the drain region comprises the step of doping the first region and the second region, the pseudo gate structure covers the preset region between the source region and the drain region, so that the probability of doping ions into the preset region is reduced, after the grid electrode is formed, the grid electrode and the interlayer dielectric layer enclose an isolation opening, and the substrate at the bottom of the isolation opening is used for forming the drift region, that is, part of the preset region is used for forming the drift region, and the doping type in the drift region is generally the same as the doping type in the source region and the drain region.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 7 and 8, fig. 8 is a cross-sectional view taken along a-a1 of fig. 7, providing a substrate including a first region I for forming a source region and a second region II for forming a drain region, and a preset region D between the first region I and the second region II.
The substrate is used to provide a process platform for forming the LDMOS transistor.
In this embodiment, the substrate is used to form an N-type LDMOS transistor. In other embodiments, the substrate may also be used to form a P-type LDMOS transistor.
In this embodiment, taking the formed LDMOS transistor as a fin field effect transistor as an example, the base includes a substrate 100 and a fin portion 110 protruding from the substrate 100. In other embodiments, when the LDMOS transistor formed is a planar transistor, the base includes only the substrate, respectively.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the fin may be made of semiconductor material such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, which are suitable for forming the fin.
In this embodiment, the first region I is used to form a source region, and the second region II is used to form a drain region.
In this embodiment, the preset region D between the first region I and the second region II defines a formation position of the subsequent dummy gate structure.
In this embodiment, in the step of providing the substrate, ions are doped in the substrate of the preset region D, where the ions are different from the doping type of the LDMOS transistor.
In this embodiment, a portion of the preset region D adjacent to the first region I is used to form a well region, and the remaining preset region D adjacent to the second region II is used to form a drift region.
In this embodiment, a drift region is formed by doping a portion of the preset region D adjacent to the second region II, and the remaining preset region D is used as a well region, so that the ion doping type in the preset region D is the same as the doping type of the well region.
In this embodiment, the substrate is used to form an N-type LDMOS transistor, and the doping ions in the preset region D are P-type ions. In other embodiments, when the substrate is used to form a P-type LDMOS transistor, the dopant ions in the predetermined region are N-type ions.
Note that, an isolation layer 111 is further formed on the substrate 100 where the fin portion 110 is exposed, and the isolation layer 111 covers a portion of the sidewall of the fin portion 110.
The isolation layer 111 is used to isolate adjacent devices from each other. In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation layer may also be silicon nitride or other dielectric materials such as silicon oxynitride.
Referring to fig. 9, a dummy gate structure 113 is formed on the substrate to cover the preset region D.
The dummy gate structure 113 is used to occupy a spatial position for subsequent formation of an initial gate structure.
The subsequent steps further comprise: and doping the first region I and the second region II to form a source region and a drain region respectively.
In the embodiment of the invention, the part of the preset region D adjacent to the second region II is used for forming the drift region, and the doping type in the drift region is generally the same as the doping type of the source region and the drain region, so that the dummy gate structure 113 covers the preset region D between the first region I and the second region II, thereby being beneficial to preventing ions from being doped into the preset region D in the process of forming the source region and the drain region, correspondingly being beneficial to preventing doped ions of the source region and the drain region from being doped into the drift region, further being beneficial to preventing the problem of reduced resistance of the drift region caused by increased ion doping concentration in the drift region, further being beneficial to ensuring the capability of the drift region for sharing higher voltage, and correspondingly optimizing the performance of the semiconductor structure.
In this embodiment, the dummy gate structure 113 spans across the fin 110 and covers a portion of the top and a portion of the sidewall of the fin 110.
In this embodiment, the dummy gate structure 113 is a single-layer structure, and the dummy gate structure 113 includes only a dummy gate layer.
In this embodiment, the material of the dummy gate structure 113 is polysilicon.
In this embodiment, in the process of forming the dummy gate structure 113, a gate mask layer 114 is further formed on top of the dummy gate structure 113. The gate mask layer 114 is used as an etching mask when forming the dummy gate structure 113, and the gate mask layer 114 is also used to protect the top of the dummy gate structure 113.
In this embodiment, the material of the gate mask layer 114 is silicon nitride.
In this embodiment, after providing the substrate, before forming the dummy gate structure 113, the method for forming a semiconductor structure further includes: a dummy gate oxide layer 112 is formed on the top surface and the sidewalls of the fin portion 110 where the isolation layer 111 is exposed. The dummy gate oxide 112 is used to protect the fin 110, and the dummy gate oxide 112 can also be used as a stop layer during subsequent removal of the dummy gate structure 113.
In this embodiment, the material of the dummy gate oxide layer 112 is silicon oxide.
In this embodiment, after the dummy gate structure 113 is formed, the method for forming a semiconductor structure further includes: a sidewall 115 is formed on sidewalls of the dummy gate structure 113 and the gate mask layer 114.
In this embodiment, the sidewall 115 is used to define the formation regions of the source region and the drain region. Specifically, in this embodiment, fin 110 is exposed at two sides of dummy gate structure 114 and sidewall 115, where fin 110 at one side exposed by dummy gate structure 114 and sidewall 115 is used as first region I, and fin 110 at the other side exposed by dummy gate structure 114 and sidewall 115 is used as second region II.
The material of the side wall 115 may be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride oxide, silicon oxynitride, boron nitride and boron carbonitride, and the side wall 115 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 115 has a single-layer structure, and the material of the side wall 115 is silicon nitride.
Referring to fig. 10 to 11, the first region I and the second region II are doped to form a source region 120 (shown in fig. 11) and a drain region 130 (shown in fig. 11), respectively.
The source region 120 is formed in a first region I on one side of the dummy gate structure 113, and the drain region 130 is formed in a second region II on the other side of the dummy gate structure 113.
In this embodiment, the source region 120 and the drain region 130 are respectively formed in the fin portion 110 at two sides of the dummy gate structure 113 and the sidewall 114.
In this embodiment, the source region 120 and the drain region 130 have doped ions therein, and the ion doping types in the source region 120 and the drain region 130 are opposite to the ion doping types in the fin 110. Specifically, the ion doping type in the source region 120 and the drain region 130 is opposite to the ion doping type in the well region.
In this embodiment, the step of forming the source region 120 and the drain region 130 includes:
as shown in fig. 10, a source drain epitaxial layer 116 is formed in the substrate of the first region I and the second region II.
The source drain epitaxial layer 116 is used to form a source region or a drain region.
As an example, in this embodiment, the step of forming the source-drain epitaxial layer 116 includes: a stress layer is formed in the substrate of the first region I and the second region II, and the source drain epitaxial layer 116 is formed in situ by self-doping ions during the formation of the stress layer.
The stress layer is used for providing stress for the channel when the device works, so that the carrier mobility of the channel is improved. When the N-type LDMOS transistor is formed, the stress layer is made of Si or SiC, so that the source-drain epitaxial layer 116 provides a tensile stress effect for a channel region of the N-type LDMOS transistor, and the carrier mobility of the N-type LDMOS transistor is improved; when the P-type LDMOS transistor is formed, the stress layer is made of Si or SiGe, so that the source-drain epitaxial layer 116 provides a compressive stress for the channel region of the P-type LDMOS transistor, which is beneficial to improving the carrier mobility of the P-type LDMOS transistor.
The doping type of the in-situ self-doping ions is the same as that of the transistor.
Specifically, when the N-type LDMOS transistor is formed, the doped ions of the in-situ self-doped ions are N-type ions, wherein the N-type ions comprise P ions, as ions, sb ions or the like; when the P-type LDMOS transistor is formed, the doped ions of the In-situ self-doped ions are P-type ions, and the P-type ions comprise B ions, ga ions, in ions and the like.
Specifically, in this embodiment, the step of forming the source-drain epitaxial layer 116 includes: etching the substrate exposed by the dummy gate structure 113 by using the dummy gate structure 113 as a mask, and forming grooves (not shown) in the substrates of the first region I and the second region II; the source drain epitaxial layer 116 is formed in the recess.
The recesses are used to provide spatial locations for forming source drain epitaxial layers 116.
In this embodiment, the step of forming the groove includes: and etching the substrate exposed by the dummy gate structure 113 by using the dummy gate structure 113 as a mask and adopting a dry etching process.
Specifically, in this embodiment, the fin portions 110 exposed by the dummy gate structures 113 and the sidewalls 115 are etched to form the grooves. Accordingly, the source-drain epitaxial layer 116 is formed in the fin 110 exposed by the dummy gate structure 113 and the sidewall 115.
In this embodiment, in-situ self-doping ions are taken as an example in the process of forming the source-drain epitaxial layer 116. In other embodiments, the step of in-situ self-doping ions may not be performed during the formation of the source-drain epitaxial layer, and accordingly, the source-drain epitaxial layer does not have doping ions therein during the formation of the source-drain epitaxial layer.
As shown in fig. 11, the source-drain epitaxial layer 116 is doped with ions to form a source region 120 and a drain region 130, respectively.
In this embodiment, the source-drain epitaxial layer 116 is located in the first region I and the second region II on both sides of the dummy gate structure 113, and the preset region D between the first region I and the second region II is covered by the dummy gate structure 113, so that in the process of doping ions into the source-drain epitaxial layer 116, it is beneficial to prevent the ions from being doped into the substrate of the preset region D, and the portion of the substrate of the preset region D adjacent to the second region II is used to form a drift region, where the doping type is the same as that of the source region 120 or the drain region 130, so that this embodiment is beneficial to prevent the ions from being doped into the drift region, and further prevent the problem of decreasing the resistance of the drift region due to increasing the ion doping concentration in the drift region, and accordingly ensures the capability of the drift region for higher voltage.
In this embodiment, during the process of forming the source-drain epitaxial layer 116, the method further includes a step of performing in-situ self-doping, and by doping ions into the source-drain epitaxial layer 116 after forming the source-drain epitaxial layer 116, the ion doping concentration of the source region 120 or the drain region 130 is advantageously increased, so that the resistance of the source region 120 and the drain region 130 is advantageously reduced; the subsequent steps further include forming a source plug and a drain plug that are respectively in contact with the source region 120 and the drain region 130, where the source region 120 or the drain region 130 has a higher ion doping concentration, which is correspondingly beneficial to reducing the contact resistance between the source plug and the source region 120, and reducing the contact resistance between the drain plug and the drain region 130, thereby being beneficial to improving the performance of the semiconductor structure.
In this embodiment, an ion implantation process is used to dope the source-drain epitaxial layer 116 with ions.
When forming an NMOS transistor, the dopant ions are N-type ions, such as: as ions or P ions, the parameters of the ion implantation process include: the implantation energy is 3KeV to 30KeV, the implantation dosage is 5.0E14 atoms per square centimeter to 8.0E15 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees; when forming PMOS transistors, the dopant ions are P-type ions, such as: b ions, the parameters of the ion implantation process including: the implantation energy is 0.5KeV to 10KeV, the implantation dosage is 8.0E14 atoms per square centimeter to 1.0E16 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees.
The implantation energy of the ion implantation process is not too small nor too large. If the implantation energy is too small, it is difficult to reduce the parasitic resistance of the source drain epitaxial layer 116; if the implantation energy is too large, it is difficult to control short channel effect, and problems such as implantation contamination and particle scattering are easily caused, and in addition, the implantation energy is too large, which easily causes that after the ions are implanted into the source drain epitaxial layer 116, the ions still have a certain energy so as to be easily diffused into the substrate, for example: ions may be caused to diffuse into the substrate used to form the drift region, which also tends to cause a decrease in the resistance of the drift region. For this reason, in the present embodiment, when the implanted ions are N-type ions, the implantation energy is 3KeV to 30KeV; when the implanted ions are P-type ions, the implantation energy is 0.5KeV to 10KeV.
The implantation dose of the ion implantation process is not too small or too large. If the implantation dose is too small, the effect of improving the ion doping concentration in the source-drain epitaxial layer 116 is not obvious; if the implantation dose is too large, it is difficult to control short channel effects, and the implanted ions may also diffuse into the substrate used to form the drift region. For this reason, in the present embodiment, when the implanted ions are N-type ions, the implantation dose is 5.0E14 atoms per square centimeter to 8.0E15 atoms per square centimeter; when the implanted ions are P-type ions, the implantation dose is 8.0E14 atoms per square centimeter to 1.0E16 atoms per square centimeter.
The included angle between the implantation direction of the ion implantation and the normal line of the substrate is not too large, otherwise the risk of implanting ions into the substrate below the dummy gate structure 113 is easily increased, the region adjacent to the source region 120 is subsequently used as a channel, the region adjacent to the drain region 130 is used to form a drift region, the ions are diffused into the substrate below the dummy gate structure 113, and the ions are easily diffused into the channel or the position where the drift region is located, which will all have adverse effects on the performance of the semiconductor structure. For this reason, in the embodiment, when the implanted ions are N-type ions, the included angle between the implantation direction and the normal line of the substrate is 5 ° to 25 °; when the implanted ions are P-type ions, the included angle between the implantation direction and the normal line of the substrate is 5-25 degrees.
Referring to fig. 12, an interlayer dielectric layer 140 is formed on both sides of the dummy gate structure 113 to cover the source region 120 and the drain region 130.
The interlayer dielectric layer 140 is used to achieve electrical isolation between adjacent devices.
The interlayer dielectric layer 140 is made of a dielectric material. The material of the interlayer dielectric layer 140 may be one or more of silicon oxide silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride.
In this embodiment, the interlayer dielectric layer 140 has a single-layer structure, and the material of the interlayer dielectric layer 140 is silicon oxide. In this embodiment, the step of forming the interlayer dielectric layer 140 includes: forming a dielectric material layer covering the source and drain regions 120 and 130 and the gate mask layer 114 on the substrate; the dielectric material layer above the dummy gate structure 113 is removed and the remaining dielectric material layer is used as the interlayer dielectric layer 140.
In this embodiment, in the process of removing the dielectric material layer higher than the dummy gate structure 113, the gate mask layer 114 is also removed. Therefore, after the interlayer dielectric layer 140 is formed, the interlayer dielectric layer 140 exposes the top surface of the dummy gate structure 113, so that the dummy gate structure 113 can be removed later.
Referring to fig. 13, the dummy gate structure 113 is removed, and a gate opening 10 is formed in the interlayer dielectric layer 140.
The gate opening 10 is used to provide a spatial location for forming an initial gate structure.
In this embodiment, in the process of removing the dummy gate structure 113, the dummy gate oxide layer 112 at the bottom of the dummy gate structure 113 is also removed. Thus, the bottom of the gate opening 10 exposes the fin 110.
In this embodiment, the process of removing the dummy gate structure 113 includes a dry etching process, for example: an anisotropic dry etching process.
Referring to fig. 14, the gate opening 10 is filled to form an initial gate structure 150.
After the initial gate structure 150 of a partial width adjacent to the drain region 130 is subsequently removed, the remaining initial gate structure 150 is used as a gate.
In the present embodiment, the initial gate structure 150 is used to form a metal gate, and thus, the initial gate structure 150 includes the work function film 12 located at the bottom and side walls of the gate opening 10, and the gate electrode film 13 located on the work function film 12.
The work function film 12 is used to form a work function layer. When the N-type LDMOS transistor is formed, the work function film 12 is an N-type work function material, and the work function film 12 includes one or more of TiAl, taAlN, tiAlN, moN, taCN and AlN; when forming the P-type LDMOS transistor, the work function film 12 is a P-type work function material, and the work function film 12 includes one or more of Ta, tiN, taN, taSiN and TiSiN.
The gate electrode film 13 is used to form a gate electrode layer. The material of the gate electrode film 13 is a conductive material, for example: w, al, cu, ag, au, pt, ni or Ti, etc.
In this embodiment, after forming the gate opening 10, before forming the initial gate structure 150, the method for forming a semiconductor structure further includes: a high-k gate dielectric layer 11 is formed at the bottom and sidewalls of the gate opening 10. Accordingly, a work function layer 12 is located on the high-k gate dielectric layer 11.
The high-k gate dielectric layer 11 is used to electrically isolate the gate structure from the substrate.
The material of the high-k gate dielectric layer 11 is a high-k dielectric material, where the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide, for example: hfO (HfO) 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al 2 O 3 Etc.
It should be noted that, in this embodiment, after the initial gate structure 150 is formed, the method for forming a semiconductor structure further includes: etching back part of the initial gate structure 150 to enable the rest of the initial gate structure 150 and the high-k gate dielectric layer 13 to form a groove (not shown); the trench is filled to form a protective layer 160.
Specifically, the gate electrode film 13 and the work function film 12 of the etched back portion form the trench.
The protection layer 160 serves to protect the top of the initial gate structure 150. After the gate structure is formed, the method further includes a step of forming a gate plug in contact with the gate structure, where the step of forming the gate plug generally includes a step of etching a dielectric layer on the gate structure, and the protective layer 160 can serve to define an etching stop position during the process of etching the dielectric layer on the gate structure, so as to prevent damage to the gate structure 150.
In this embodiment, the material of the protection layer 160 is silicon nitride.
Referring to fig. 15, the initial gate structure 150 with a partial width adjacent to the drain region 130 is removed, and the remaining initial gate structure 150 is used as a gate 170, where the gate 170 and the interlayer dielectric layer 140 enclose an isolation opening 20, and a substrate at the bottom of the isolation opening 20 is used to form a drift region.
The gate 170 is used to control the opening and closing of the conduction channel when the device is in operation.
By removing the portion of the initial gate structure 150 adjacent to the drain region 130, the gate 170 is isolated from the drain region 130, exposing the substrate adjacent to the drain region 130, thereby increasing the distance between the gate 170 and the drain region 130, enabling the drift region to act as an extension resistance region, and thus enabling the drift region to withstand a greater voltage division.
In this embodiment, the gate electrode film 13 and the work function film 12 are removed in a portion of the width adjacent to the drain region 130, the remaining gate electrode film 13 is used as the gate electrode layer 23, the remaining work function film 12 is used as the work function layer 22, and the gate electrode layer 23 and the work function layer 22 constitute the gate electrode 170.
Regarding the gate electrode layer 23 and the work function layer 22, reference is made to the foregoing descriptions of the gate electrode film 13 and the work function film 12, respectively, and the description of this embodiment is omitted here.
In this embodiment, in the step of removing the gate electrode film 13 and the work function film 12 of a partial width adjacent to the drain region 130, the protective layer 160 of a partial width adjacent to the drain region 130 is also removed.
In this embodiment, the step of removing the portion of the width of the initial gate structure 150 adjacent to the drain region 130 includes: forming a shielding layer (not shown) covering a portion of the width of the initial gate structure 150 adjacent to the source region 120; and removing the initial gate structure 150 exposed by the shielding layer.
In this embodiment, the process of removing the portion of the width of the initial gate structure 150 adjacent to the drain region 130 includes a dry etching process, for example: an anisotropic dry etching process.
In this embodiment, the parameters of the dry etching process include: the etching gas includes CF 4 、SF 6 And Cl 2 ，CF 4 Is 100sccm to 900sccm, SF 6 Is 60sccm to 300sccm, cl 2 The gas flow rate is 100sccm to 2000sccm, the process pressure is 10mTorr to 350mTorr, and the bias power is 80W to 500W. In this embodiment, the gas flow, bias power and process pressure of the dry etching process are set within reasonable ranges and are matched with each other, so that the processing efficiency and stability are improved, and meanwhile, the process cost and side effects are reduced.
The bottom of the isolation opening 20 exposes a portion of the preset region D adjacent to the drain region 130, and the exposed portion of the preset region D is used to form a drift region.
In this embodiment, the bottom of the isolation opening 20 and the sidewall of the isolation opening 20 near the drain region 130 expose the high-k gate dielectric layer 11, and the isolation opening 20 is surrounded by the gate 170 and the high-k gate dielectric layer 11.
The subsequent steps further comprise: ions are doped in the substrate exposed by the isolation opening 20 and are diffused into a part of the substrate at the bottom of the gate 170 to form a drift region, wherein the high-k gate dielectric layer 11 at the bottom of the isolation opening 20 is further used for protecting the fin 110 during the formation of the drift region.
It should be noted that the aspect ratio of the isolation opening 20 defined by the gate 170 and the interlayer dielectric layer 140 should not be too small or too large. If the aspect ratio of the isolation opening 20 is too small, the width of the isolation opening 20 is correspondingly too large, which tends to cause the volume of the gate 170 to be too small, thereby easily causing the control capability of the gate 170 on the channel to be reduced; if the aspect ratio of the isolation opening 20 is too large, the width of the isolation opening 20 is too small correspondingly under the condition that the depth of the isolation opening 20 is certain, and the subsequent process further comprises filling the isolation opening 20 with an isolation structure, which easily results in that the filling difficulty of the isolation structure in the isolation opening 20 is large, and the probability of generating defects such as cavities inside the isolation structure is high. For this reason, in the present embodiment, the aspect ratio of the isolation opening 20 is 1:10 to 1:30.
Referring to fig. 16 in combination, in this embodiment, the method for forming a semiconductor structure further includes: after the gate 170 is formed, ions are doped in the substrate exposed by the isolation opening 20, and the ions are diffused into a portion of the substrate at the bottom of the gate 170, forming the drift region 102.
In this embodiment, after the drift region 102 is formed, the remaining region of the preset region D is used as the well region 101, and the well region 101 is adjacent to the drift region 102.
The well region 101 serves as a lateral diffusion region to form a channel having a concentration gradient, and the drift region 102 serves to withstand a large partial pressure.
In this embodiment, after the gate 170 is formed, the drift region 102 is formed, so that the shielding layer can be used as the ion doped mask, which is beneficial to saving the photomask and saving the process cost; in addition, in the embodiment, after the gate 170 is formed, ions are doped in the substrate exposed by the isolation opening 20 and are diffused into a portion of the substrate at the bottom of the gate 170 to form the drift region 102, so that the gate 170 can cover the junction between the well region 101 and the drift region 102, the doping profile of the drift region 102 meets the process requirement, and further the process stability is improved.
The type of dopant ions in the drift region 102 is different from the type of dopant ions in the well region 101. When the N-type LDMOS transistor is formed, the doped ions in the well region 101 are P-type ions, and the doped ions in the drift region 102 are N-type ions; when forming the P-type LDMOS transistor, the doped ions in the well region 101 are N-type ions, and the doped ions in the drift region 102 are P-type ions.
In this embodiment, the step of forming the drift region 102 includes: ion implantation 30 is performed on the substrate exposed by the isolation opening 20.
When forming an NMOS transistor, the implanted ions are N-type ions, such as: as ions or P ions, the parameters of the ion implantation process include: the implantation energy is 10KeV to 70KeV, the implantation dosage is 5.0E13 atoms per square centimeter to 8.0E14 atoms per square centimeter, and the implantation angle is 5 degrees to 25 degrees; when forming PMOS transistors, the implanted ions are P-type ions, such as: b ions, the parameters of the ion implantation process including: the implantation energy is 2KeV to 25KeV, the implantation dosage is 6.0E13 atoms per square centimeter to 1.0E15 atoms per square centimeter, and the implantation angle is 5 DEG to 25 deg.
The implantation energy of the ion implantation 30 is not preferably too small nor too large. If the implantation energy of the ion implantation 30 is too small, it is easy to cause the doping depth of the formed drift region 102 to be small; if the implantation energy of the ion implantation 30 is too large, damage to the fin 110 or the gate 170 is likely to occur. For this reason, when forming an NMOS transistor, the implanted ions are N-type ions with an implantation energy of 10KeV to 70KeV; when forming PMOS transistors, the implanted ions are P-type ions with implant energies of 2KeV to 25KeV.
The implantation dose of the ion implantation 30 is not preferably too small nor too large. If the implantation dose of the ion implantation 30 is too small, it is easy to cause too low ion doping concentration in the drift region 102; if the implantation dose of the ion implantation 30 is too large, the ion doping concentration in the drift region 102 is liable to be high, and thus the withstand voltage capability of the drift region 102 is liable to be lowered. For this reason, when forming an NMOS transistor, the implanted ions are N-type ions with an implantation dose of 5.0E13 atoms per square centimeter to 8.0E14 atoms per square centimeter; when forming PMOS transistors, the implanted ions are P-type ions with an implant dose of 6.0E13 atoms per square centimeter to 1.0E15 atoms per square centimeter.
The angle between the implantation direction of the ion implantation 30 and the normal to the substrate should not be too large, otherwise the risk of implanting ions into the gate 170 is easily increased. In this embodiment, the angle between the implantation direction of the ion implantation 30 and the normal of the substrate is 5 ° to 25 °.
In the present embodiment, the drift region 102 is formed as an example after the gate electrode 170 and the isolation opening 20 are formed.
In other embodiments, the method for forming a semiconductor structure further includes: in the step of providing the substrate, ions are doped in a part of the substrate adjacent to the second region in the preset region to form a drift region. Specifically, the well region and the drift region may be formed by doping ions in different regions in the substrate, respectively, through a Mask (Mask). Accordingly, in this embodiment, in the step of forming a gate, the gate also covers part of the drift region. The steps for forming the drift region and the well region are not limited thereto, and the present invention is not limited thereto.
Referring to fig. 17 in combination, in this embodiment, the method for forming a semiconductor structure further includes: after forming the isolation opening 20 and after forming the drift region 102, the isolation opening 20 is filled to form an isolation structure 185.
The isolation structure 185 is used to fill the isolation opening 20, so as to isolate adjacent devices, and reduce the probability of leakage current and short circuit between the adjacent devices.
In this embodiment, the step of forming the isolation structure 185 includes: an inter-metal dielectric layer 180 is formed on the inter-metal dielectric layer 140, the inter-metal dielectric layer 180 also covers the gate 170 and fills the isolation opening 20, and the inter-metal dielectric layer 180 filled in the isolation opening 20 is used as the isolation structure 185.
Thus, the material of isolation structure 185 is the same as the material of inter-metal dielectric layer 180.
The inter-metal dielectric layer 180 is used to achieve isolation between conductive plugs or interconnect lines. Therefore, the material of the inter-metal dielectric layer 180 is a dielectric material. The material of the inter-metal dielectric layer 180 may be silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride or silicon boron carbide nitride. In this embodiment, the material of the inter-metal dielectric layer 180 is silicon oxide, and the material of the isolation structure 185 is correspondingly silicon oxide.
In this embodiment, the process of forming inter-metal dielectric layer 180 includes flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD). The flowable chemical vapor deposition process has good filling capability, is suitable for filling the openings with high aspect ratio, is beneficial to reducing the probability of generating defects such as voids in the material of the inter-metal dielectric layer 180 positioned in the isolation opening 20, and correspondingly improves the film forming quality of the isolation structure 185.
In other embodiments, the process of forming the inter-metal dielectric layer further includes a deposition process such as a plasma chemical vapor deposition process or a low pressure chemical vapor deposition process.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 11, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: the substrate comprises a first region I used for forming a source region, a second region II used for forming a drain region and a preset region D positioned between the first region I and the second region II, wherein a part of the substrate adjacent to the second region II in the preset region D is used for forming a drift region; a dummy gate structure 113 located on the substrate and covering the preset region D; a source region 120 in the substrate of the first region I; and a drain region 130 in the substrate of the second region II.
The process of forming the source region 120 and the drain region 130 generally includes the step of doping the first region I and the second region II, and in the semiconductor structure provided in the embodiment of the present invention, the dummy gate structure 113 covers the preset region D between the source region 120 and the drain region 130, so that it is beneficial to prevent ions from being doped into the preset region D, that is, to prevent ions from being doped into the drift region, where the doping types of the ions are the same as those of the source region 120 and the drain region 130, which is beneficial to prevent the problem that the resistance of the drift region is reduced due to the higher ion doping concentration of the drift region, and further to ensure the capability of the drift region for sharing higher voltages.
The substrate is used to provide a process platform for forming the LDMOS transistor.
In this embodiment, the substrate is used to form an N-type LDMOS transistor. In other embodiments, the substrate may also be used to form a P-type LDMOS transistor.
In this embodiment, taking the formed LDMOS transistor as a fin field effect transistor as an example, the base includes a substrate 100 and a fin portion 110 protruding from the substrate 100.
In this embodiment, the substrate 100 is a silicon substrate.
In this embodiment, the material of the fin portion 110 is the same as that of the substrate 100, and the material of the fin portion 110 is silicon.
In this embodiment, the first region I is used to form the source region 120, and the second region II is used to form the drain region 130.
The preset region D between the first region I and the second region II is used to define a formation position of the dummy gate structure 113. In this embodiment, a portion of the preset region D adjacent to the first region I is used to form a well region, and the remaining preset region D adjacent to the second region II is used to form a drift region.
In this embodiment, the drift region is formed by doping the preset region D adjacent to the second region II, and the remaining preset region D is used as the well region, so that the ion doping type in the preset region D is the same as the doping type of the well region.
In this embodiment, the substrate is used to form an N-type LDMOS transistor, and the doping ions in the preset region D are P-type ions. In other embodiments, when the substrate is used to form a P-type LDMOS transistor, the dopant ions in the predetermined region are N-type ions.
In this embodiment, a drift region is formed in a subsequent step as an example.
In other embodiments, the semiconductor structure further comprises: the well region is positioned in the substrate, close to the first region, of the preset region; and the drift region is positioned in the substrate of the preset region, which is close to the second region.
The well region is adjacent to the drift region. The well region acts as a lateral diffusion region to form a channel with a concentration gradient, and the drift region is used to withstand a large partial pressure.
The doping ion type in the drift region is different from the doping ion type in the well region. When the N-type LDMOS transistor is formed, the doped ions in the well region are P-type ions, and the doped ions in the drift region are N-type ions; when the P-type LDMOS transistor is formed, the doped ions in the well region are N-type ions, and the doped ions in the drift region are P-type ions.
It should be noted that the semiconductor structure further includes: and the isolation layer 111 is positioned on the substrate 100 exposed by the fin portion 110, and the isolation layer 111 covers part of the side wall of the fin portion 110.
The isolation layer 111 is used to isolate adjacent devices from each other. In this embodiment, the material of the isolation layer 111 is silicon oxide. In other embodiments, the material of the isolation layer may also be silicon nitride or other dielectric materials such as silicon oxynitride.
In this embodiment, the semiconductor structure further includes: the dummy gate oxide layer 112 is located on the top surface and the side wall of the fin portion 110 where the isolation layer 111 is exposed. The dummy gate oxide 112 is used to protect the fin 110, and the dummy gate oxide 112 can also be used as a stop layer during subsequent removal of the dummy gate structure 113.
In this embodiment, the material of the dummy gate oxide layer 112 is silicon oxide.
The dummy gate structure 113 is used to occupy a spatial position for subsequent formation of an initial gate structure.
In this embodiment, the dummy gate structure 113 spans across the fin 110 and covers a portion of the top and a portion of the sidewall of the fin 110.
In this embodiment, the dummy gate structure 113 is a single-layer structure, and the dummy gate structure 113 includes only a dummy gate layer.
In this embodiment, the material of the dummy gate structure 113 is polysilicon.
In this embodiment, the dummy gate structure 113 is located on the dummy gate oxide layer 112.
In this embodiment, the semiconductor structure further includes: a gate mask layer 114 on top of the dummy gate structure 113. The gate mask layer 114 is used as an etching mask when forming the dummy gate structure 113, and the gate mask layer 114 is also used to protect the top of the dummy gate structure 113.
In this embodiment, the material of the gate mask layer 114 is silicon nitride.
In this embodiment, the semiconductor structure further includes: and a sidewall 115 on the sidewalls of the dummy gate structure 113 and the gate mask layer 114.
In this embodiment, the sidewall 115 is used to define the formation regions of the source region 120 and the drain region 130. Specifically, in this embodiment, fin 110 is exposed at two sides of dummy gate structure 114 and sidewall 115, where fin 110 at one side exposed by dummy gate structure 114 and sidewall 115 is used as first region I, and fin 110 at the other side exposed by dummy gate structure 114 and sidewall 115 is used as second region II.
In this embodiment, the side wall 115 has a single-layer structure, and the material of the side wall 115 is silicon nitride.
The source region 120 is formed in a first region I on one side of the dummy gate structure 113, and the drain region 130 is formed in a second region II on the other side of the dummy gate structure 113.
In this embodiment, the source region 120 and the drain region 130 are respectively formed in the fin portion 110 at two sides of the dummy gate structure 113 and the sidewall 114.
In this embodiment, the source region 120 and the drain region 130 have doped ions therein, and the ion doping types in the source region 120 and the drain region 130 are opposite to the ion doping types in the fin 110. Specifically, the ion doping type in the source region 120 and the drain region 130 is opposite to the ion doping type in the well region.
When forming the N-type LDMOS transistor, the doped ions in the source region 120 and the drain region 130 are N-type ions, where the N-type ions include P ions, as ions, sb ions, or the like; when forming the P-type LDMOS transistor, the doped ions In the source region 120 and the drain region 130 are P-type ions, and the P-type ions include B ions, ga ions, in ions, and the like.
In this embodiment, the source region 120 and the drain region 130 include a stress layer doped with ions.
The stress layer is used for providing stress for the channel when the device works, so that the carrier mobility of the channel is improved.
When the N-type LDMOS transistor is formed, the stress layer is made of Si or SiC, so that the source region 120 and the drain region 130 provide a tensile stress effect for a channel region of the N-type LDMOS transistor, and the carrier mobility of the N-type LDMOS transistor is improved; when the P-type LDMOS transistor is formed, the stress layer is made of Si or SiGe, so that the source region 120 and the drain region 130 provide a compressive stress for the channel region of the P-type LDMOS transistor, which is beneficial to improving the carrier mobility of the P-type LDMOS transistor.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (14)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region used for forming a source region, a second region used for forming a drain region and a preset region positioned between the first region and the second region;
Forming a dummy gate structure covering the preset area on the substrate;
doping the first region and the second region to form a source region and a drain region respectively;
forming interlayer dielectric layers covering the source region and the drain region on two sides of the pseudo gate structure;
removing the pseudo gate structure and forming a gate opening in the interlayer dielectric layer;
filling the grid electrode opening to form an initial grid electrode structure;
removing the initial gate structure with partial width adjacent to the drain region, taking the rest initial gate structure as a gate, enclosing the gate and an interlayer dielectric layer to form an isolation opening, wherein a substrate at the bottom of the isolation opening is used for forming a drift region;
filling the isolation opening after forming the isolation opening and the drift region to form an isolation structure; the step of forming the isolation structure comprises the steps of: and forming a metal interlayer dielectric layer on the interlayer dielectric layer, wherein the metal interlayer dielectric layer also covers the grid electrode and is filled in the isolation opening, and the metal interlayer dielectric layer filled in the isolation opening is used as the isolation structure.
2. The method of forming a semiconductor structure of claim 1, wherein forming the source and drain regions comprises: forming a source-drain epitaxial layer in the substrate of the first region and the second region;
And doping ions into the source-drain epitaxial layer to form a source region and a drain region respectively.
3. The method of forming a semiconductor structure of claim 2, wherein forming the source drain epitaxial layer comprises: and forming a stress layer in the substrate of the first region and the second region, and forming a source drain epitaxial layer by in-situ self-doping ions in the process of forming the stress layer.
4. The method of forming a semiconductor structure of claim 2, wherein forming the source drain epitaxial layer comprises: etching the substrate exposed by the dummy gate structure by taking the dummy gate structure as a mask, and forming grooves in the substrates of the first area and the second area;
and forming the source-drain epitaxial layer in the groove.
5. The method of forming a semiconductor structure of claim 4, wherein the step of forming the recess comprises: and etching the substrate exposed by the pseudo gate structure by using the pseudo gate structure as a mask and adopting a dry etching process.
6. The method of forming a semiconductor structure of claim 3, wherein said source drain epitaxial layer is doped with ions using an ion implantation process.
7. The method of claim 6, wherein the dopant ions are N-type ions when forming the NMOS transistor, and wherein the parameters of the ion implantation process include: the implantation energy is 3KeV to 30KeV, the implantation dosage is 5.0E14 atoms per square centimeter to 8.0E15 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees;
When forming the PMOS transistor, the dopant ions are P-type ions, and the parameters of the ion implantation process include: the implantation energy is 0.5KeV to 10KeV, the implantation dosage is 8.0E14 atoms per square centimeter to 1.0E16 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees.
8. The method of forming a semiconductor structure of claim 1, wherein the process of removing a portion of the width of the initial gate structure adjacent to the drain region comprises a dry etching process.
9. The method of forming a semiconductor structure of claim 8, wherein the parameters of the dry etching process comprise: the etching gas includes CF 4 、SF 6 And Cl 2 ，CF 4 Is 100sccm to 900sccm, SF 6 Is 60sccm to 300sccm, cl 2 The gas flow rate is 100sccm to 2000sccm, the process pressure is 10mTorr to 350mTorr, and the bias power is 80W to 500W.
10. The method of forming a semiconductor structure of claim 1, further comprising: in the step of providing the substrate, doping ions in a part of the substrate adjacent to the second region in the preset region to form a drift region;
In the step of forming a gate, the gate also covers a portion of the drift region.
11. The method of forming a semiconductor structure of claim 1, further comprising: and doping ions in the substrate exposed by the isolation opening after the grid electrode is formed, and diffusing the ions into part of the substrate at the bottom of the grid electrode to form a drift region.
12. The method of forming a semiconductor structure of claim 11, wherein forming the drift region comprises: and carrying out ion implantation on the substrate exposed by the isolation opening.
13. The method of claim 12, wherein the implanted ions are N-type ions when forming the NMOS transistor, and wherein the parameters of the ion implantation process include: the implantation energy is 10KeV to 70KeV, the implantation dosage is 5.0E13 atoms per square centimeter to 8.0E14 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 degrees to 25 degrees;
when forming the PMOS transistor, the implanted ions are P-type ions, and the parameters of the ion implantation process include: the implantation energy is 2KeV to 25KeV, the implantation dosage is 6.0E13 atoms per square centimeter to 1.0E15 atoms per square centimeter, and the included angle between the implantation direction and the normal line of the substrate is 5 DEG to 25 deg.
14. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the isolation opening, an aspect ratio of the isolation opening is 1:10 to 1:30.
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CN110581174A (en) * 2018-06-08 2019-12-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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CN107437563A (en) * 2016-05-27 2017-12-05 中芯国际集成电路制造(上海)有限公司 Ldmos transistor and forming method thereof and ESD device and forming method thereof
CN110581174A (en) * 2018-06-08 2019-12-17 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

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