CN102446767B - Manufacturing method of NMOS (N-channel metal oxide semiconductor) transistor - Google Patents
Manufacturing method of NMOS (N-channel metal oxide semiconductor) transistor Download PDFInfo
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Abstract
The invention discloses a manufacturing method of a NMOS (N-channel metal oxide semiconductor) transistor in the technical field of semiconductors. The manufacturing method comprises the following steps of: providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate and forming a gate positioned on the gate dielectric layer; forming source/drain regions in the semiconductor substrate on the two sides of the gate, implanting fluorine ions and phosphorus ions into the gate during the period of forming the source/drain regions; and after forming the source/drain regions, performing rapid spike annealing and laser pulse annealing in sequence. In the manufacturing method, the fluorine ions enter the gate dielectric layer, and the fluorine ions replace a part of oxygen ions in the gate dielectric layer to form fluorine-silicon groups, which improves quality of the interface between the gate dielectric layer and the semiconductor substrate, so as to improve the hot carrier injection effect.
Description
Technical field
What the present invention relates to is a kind of device making method of technical field of semiconductors, particularly be a kind of manufacture method of nmos pass transistor.
Background technology
Along with improving constantly of semiconductor device integrated level; its characteristic size reduces gradually; source/drain electrode and source/drain electrode extension area (Source/Drain Extension) correspondingly shoals; the degree of depth of the source/drain junction of current technological level requirement semiconductor device is less than 1000 dusts, and the degree of depth that finally may require to tie is at 200 dusts or the littler order of magnitude.
Junction depth reduce the lower heat treatment temperature of requirement, and lower heat treatment temperature is (less than 500 degrees centigrade, even lower) make the lateral dimension of knot reduce thereupon, the electric field between knot and channel region that reduces to cause device to form when work of the lateral dimension of described knot forms spike at the edge, boundary of knot and channel region, namely the boundary edge at knot and channel region is formed with high electric field, electronics will be subjected to this high electric field to accelerate to be high energy particle in mobile process, described high energy particle collision produces electron-hole pair (being called hot carrier), described hot carrier obtains energy from electric field, can enter in gate oxide or the grid, then influence the threshold voltage control of device and the drift of mutual conductance, namely produce HCI (Hot CarrierInjection, hot carrier is injected) effect, thus cause the rising of threshold voltage, the following degradation of the decline of saturation current and carrier mobility.
The conduction carrier of nmos pass transistor is electronics, and the transistorized conduction carrier of PMOS is the hole, and the mobility ratio hole of electronics is a lot of greatly, therefore under same electric field, electronics can obtain bigger energy, under high electric field, electronics is accelerated and is " hot electron ", and hot hole is difficult to occur.Thus, how to suppress the HCI effect of nmos pass transistor, namely suppress hot carrier and enter gate oxide or penetrate described gate oxide and enter conducting channel, become those skilled in the art's problem demanding prompt solution.
Current, industry is to improve the HCI of nmos pass transistor, usually adopt LDD (Lightly DopedDrain, the lightly doped drain injection) optimization method of ion injection, utilization reduces dosage and the increase LDD injection energy that the LDD ion injects, obtain darker LDD knot, reduce transverse electric field intensity, thereby improve HCI.But increase the LDD ion implantation energy, along with the increasing of junction depth, the length of effective channel of device also will reduce, and will increase short-channel effect (Short Channel Effect is called for short SCE) like this, cause the decline of device DC characteristic.Therefore, merely to improve HCI be not enough by changing dosage that the LDD ion injects and energy.
In order to overcome above-mentioned shortcoming, Chinese patent application number is: 200410089222.1, name is called: reduce the method that I/O nmos device hot carrier is injected, this technology is at first carried out polysilicon gate etching, carries out polysilicon gate again and reoxidizes, and carries out the LDD rapid thermal annealing then, after the annealing, in LDD, adopt arsenic ion to inject earlier, then in LDD, adopt phosphonium ion to inject, carry out polysilicon side wall deposit and etching at last.But this technology has changed existing processes, compatible relatively poor with existing technology.
In order to improve the HCI effect of nmos pass transistor, prior art also discloses a kind of technical scheme, annealing after the source/the leakage extended structure forms of nmos pass transistor, so that the foreign ion that low doping source/drain region is injected fully activates and spreads.But in above-mentioned technology, along with dimensions of semiconductor devices continue dwindle, such as in the semiconductor device of 65nm and following size, technique scheme is not enough to suppress hot carrier injection effect, thereby inapplicable.
Summary of the invention
Problem to be solved by this invention is: in the manufacturing process of nmos pass transistor, how to improve the HCI effect.
For addressing the above problem, the invention provides a kind of manufacture method of nmos pass transistor, comprising: Semiconductor substrate is provided; Form gate dielectric and the grid that is positioned on the gate dielectric in described Semiconductor substrate; Formation source/drain region in the Semiconductor substrate of grid both sides, and during formation source/drain region, in described grid, inject fluorine ion and phosphonium ion; Behind formation source/drain region, carry out fast peak annealing and laser pulse annealing successively.
Alternatively, described formation source/drain region comprises successively: the light dope ion injects; In described grid, inject fluorine ion and phosphonium ion; Heavy doping ion is injected.
Alternatively, described formation source/drain region comprises successively: the light dope ion injects; Heavy doping ion is injected; Inject fluorine ion and phosphonium ion in the described grid.
Alternatively, described formation source/drain region comprises successively: inject fluorine ion and phosphonium ion in described grid; The light dope ion injects; Heavy doping ion is injected.
Alternatively, injection fluorine ion and phosphonium ion comprise in described grid: inject phosphonium ion at described grid earlier, inject fluorine ion then in described grid.
Alternatively, injection fluorine ion and phosphonium ion comprise in described grid: inject fluorine ion and phosphonium ion simultaneously at described grid.
Alternatively, in described grid, inject fluorine ion simultaneously and phosphonium ion comprises: directly inject PF at described grid
3And PF
5In a kind of or its combination.
Alternatively, the temperature peak scope of described fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds.
Alternatively, the temperature peak scope of described laser pulse annealing is 1200 ℃ to 1300 ℃.
Compared with prior art, the present invention has the following advantages: the present invention injects fluorine ion in grid, and make the part fluorine ion diffuse into gate dielectric by the fast peak annealing process, activated the fluorine ion in the gate dielectric by laser pulse annealing again, make the partial oxygen ion in the fluorine ion replacement gate dielectric, thereby form the fluorine silicon group, simultaneously because fluorine ion is repaired the function of chemical bond, and then make the interface of gate dielectric and Semiconductor substrate become finer and close, improved the interface quality between gate dielectric and Semiconductor substrate, stop and form charge trap, prevent lightly-doped source under making alive/drain region gathering electric charge, thereby improved the HCI effect of nmos pass transistor greatly.
Description of drawings
Fig. 1 is the schematic flow sheet of the transistorized manufacture method of embodiment 1NMOS;
Fig. 2 to Fig. 9 is the schematic diagram that forms nmos pass transistor according to flow process shown in Figure 1;
Figure 10 is the schematic flow sheet of the transistorized manufacture method of embodiment 2NMOS;
Figure 11 is the schematic flow sheet of the transistorized manufacture method of embodiment 3NMOS.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Just as described in the background section, HCI is owing to there is stronger transverse electric field in nmos pass transistor, makes the charge carrier ionization that bumps to produce extra electron hole pair in the process that transports, in portion of hot charge carrier injection grid oxide layer or the grid, thereby produce the HCI effect.
Therefore, when making semiconductor device, for preventing above-mentioned generation of defects.The manufacture method of nmos pass transistor provided by the invention comprises: Semiconductor substrate is provided; Form gate dielectric and the grid that is positioned on the gate dielectric in described Semiconductor substrate; Formation source/drain region in the Semiconductor substrate of grid both sides, and during formation source/drain region, in described grid, inject fluorine ion and phosphonium ion; Behind formation source/drain region, carry out fast peak annealing and laser pulse annealing successively.The present invention adds fluorine ion in grid, and make the part fluorine ion diffuse into gate dielectric by the fast peak annealing process, activated the fluorine ion in the gate dielectric by laser pulse annealing again, make the partial oxygen ion in the fluorine ion replacement gate dielectric, thereby form the fluorine silicon group, simultaneously because fluorine ion is repaired the function of chemical bond, and then make the interface of gate dielectric and Semiconductor substrate become finer and close, improved the interface quality between gate dielectric and Semiconductor substrate, thereby improved the HCI of nmos pass transistor greatly, and can good and existing process compatible.
Embodiment 1
As shown in Figure 1, the manufacture method of nmos pass transistor may further comprise the steps in the present embodiment:
S100 provides Semiconductor substrate;
S101 forms gate dielectric and the grid that is positioned on the gate dielectric in described Semiconductor substrate;
S102 carries out the light dope ion and injects in the Semiconductor substrate of grid both sides, form lightly-doped source/drain region;
S103 injects fluorine ion and phosphonium ion in described grid;
S104 carries out heavy doping ion and injects in the Semiconductor substrate of grid both sides, form heavy-doped source/drain region;
S105 carries out fast peak annealing and laser pulse annealing successively.
With reference to figure 2, at first execution in step S100 provides Semiconductor substrate 200.Wherein, described Semiconductor substrate 200 is silicon, the silicon-on-insulator (SOI) that is formed with semiconductor device that is formed with semiconductor device or is body silicon.
Then execution in step S101 forms gate dielectric 201 and the grid 202 that is positioned on the gate dielectric 201 in described Semiconductor substrate 200, and gate dielectric 201 and grid 202 constitute grid structures, form structure as shown in Figure 3.
Described gate dielectric 201 is silicon dioxide or silicon oxynitride, and it forms technology can be chemical vapor deposition method.
Described grid 202 is polysilicon or multicrystalline silicon compounds, it forms technology can adopt any prior art well known to those skilled in the art, as when adopting chemical vapour deposition technique, can be low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition.
Then execution in step S102 carries out the light dope ion and injects in the Semiconductor substrate 200 of grid 202 both sides, forms lightly-doped source/drain region 203.In the prior art, it is to be mask with gate dielectric 201 and grid 202 that the light dope ion of nmos pass transistor injects, and carries out the light dope ion and inject in Semiconductor substrate 200, formation unactivated lightly-doped source/drain region 203a Semiconductor substrate 200 in.Because this zone is N-type MOS transistor zone, so the doping ion that described light dope ion injects can be phosphonium ion or arsenic ion etc.
When the ion of light dope ion injection was phosphonium ion, the energy range that ion injects was 1KeV to 20KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2
When the ion of light dope ion injection was arsenic ion, the energy range that ion injects was 2KeV to 35KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2
Further, in step S102, before or after carrying out the injection of light dope ion, can also carry out the injection of bag-like region ion and form unactivated bag-like region 204a, form structure as shown in Figure 4.It should be noted that the ionic conduction type opposite that the ion that described bag-like region ion injects and light dope ion inject.Accordingly, also having carried out the bag-like region ion before or after light dope ion in step S102 injects injects, after forming the technology of unactivated bag-like region 204a, then in step S102, also comprise the lightly-doped source/drain region 203 that forms bag-like region 204 and activate by spike annealing at a slow speed, form structure as shown in Figure 5.
In addition; in the embodiment of above-mentioned manufacturing nmos pass transistor; spike annealing technology is to carry out after the injection of light dope ion and bag-like region ion implantation step at a slow speed; but not as limit; in other embodiments; spike annealing technology also can divide secondary to carry out at a slow speed; namely after light dope ion implantation step, carry out the first time of spike annealing step and after bag-like region ion implantation step, carry out the second time of spike annealing step at a slow speed at a slow speed, should too much not limit protection scope of the present invention at this.
Follow execution in step S103; in described grid 202, inject phosphonium ion 207 and fluorine ion 208; form structure as shown in Figure 6; wherein ● expression phosphonium ion 207; ★ represents fluorine ion 208; schematic diagram just herein, can not represent phosphonium ion 207 and fluorine ion 208 reality implantation dosage and inject the degree of depth, this should be not too much restriction protection scope of the present invention.
Described injection phosphonium ion 207 and fluorine ion 208 are to inject phosphonium ion 207 at described grid 202 earlier, inject fluorine ion 208 then in described grid 202; Or in described grid 202, inject fluorine ion 208 and phosphonium ion 207 simultaneously.
When in described grid 202, injecting fluorine ion 208 and phosphonium ion 207 simultaneously, can be in described grid 202, directly to inject PF
3And PF
5In a kind of or its combination, this moment, to inject energy range be 3KeV to 10KeV, the implantation dosage scope is 1E15/cm
2To 6E15/cm
2
Execution in step S104 carries out heavy doping ion and injects in the Semiconductor substrate 200 of described grid 202 both sides then, forms heavy-doped source/drain region 206.
Further, the described heavy doping ion of carrying out is injected and to be comprised: the relative both sides at described gate dielectric 201 and described grid 202 form isolated side wall 205, form as shown in Figure 7 structure (isolated side wall 205 can be in silica, silicon nitride, the silicon oxynitride a kind of or they make up arbitrarily); Be mask with described grid 202 and described isolated side wall 205, in Semiconductor substrate 200, inject phosphonium ion or arsenic ion to form heavy-doped source/drain region 206, form structure as shown in Figure 8.
When injecting phosphonium ion when forming heavy-doped source/drain region 206 in Semiconductor substrate 200, the energy range that ion injects is 8KeV to 30KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2
When injecting arsenic ion when forming heavy-doped source/drain region 206 in Semiconductor substrate 200, the energy range that ion injects is 8KeV to 50KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2
Last execution in step S105 carries out fast peak annealing and laser pulse annealing successively.
The temperature peak scope of described fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds, and the fast peak annealing of this moment can make wherein that part fluorine ion 208 diffuses into gate dielectric 201, with reference to shown in Figure 9.
The temperature peak scope of described laser pulse annealing is 1200 ℃ to 1300 ℃, the laser pulse annealing of this moment can make the fluorine ion 208 that enters gate dielectric 201 be activated, and the partial oxygen ion that the fluorine ion 208 that is activated replaces in the gate dielectric 201, thereby form the fluorine silicon group, bring into play fluorine ion simultaneously and repair the function of chemical bond, and then make the interface of gate dielectric 201 and Semiconductor substrate 200 become finer and close.
Present embodiment is by after adding the technology of injecting fluorine ion in grid 202, the nmos pass transistor of preparing can be by the system performance testing of HCI; And the nmos pass transistor that adopts prior art for preparing to go out can not be by the system performance testing of HCI.
Embodiment 2
As shown in figure 10, the manufacture method of nmos pass transistor may further comprise the steps in the present embodiment:
S300 provides Semiconductor substrate;
S301 forms gate dielectric and the grid that is positioned on the gate dielectric in described Semiconductor substrate;
S302 carries out the light dope ion and injects in the Semiconductor substrate of grid both sides, form lightly-doped source/drain region;
S303 carries out heavy doping ion and injects in the Semiconductor substrate of grid both sides, form heavy-doped source/drain region;
S304 injects fluorine ion and phosphonium ion in described grid;
S305 carries out fast peak annealing and laser pulse annealing successively.
The difference of present embodiment and embodiment 1 only is that " carrying out heavy doping ion in the Semiconductor substrate of grid both sides injects; form heavy-doped source/drain region " step is different with the execution sequence of " injecting fluorine ion and phosphonium ion in described grid " step, and carrying into execution a plan that each step is concrete is identical with embodiment 1.
Present embodiment by technology that in grid, add to inject fluorine ion after, the nmos pass transistor of preparing can be by the system performance testing of HCI, and effect is with embodiment 1; And the nmos pass transistor that adopts prior art for preparing to go out can not be by the system performance testing of HCI.
Embodiment 3
As shown in figure 11, the manufacture method of nmos pass transistor may further comprise the steps in the present embodiment:
S400 provides Semiconductor substrate;
S401 forms gate dielectric and the grid that is positioned on the gate dielectric in described Semiconductor substrate;
S402 injects fluorine ion and phosphonium ion in described grid;
S403 carries out the light dope ion and injects in the Semiconductor substrate of grid both sides, form lightly-doped source/drain region;
S404 carries out heavy doping ion and injects in the Semiconductor substrate of grid both sides, form heavy-doped source/drain region;
S405 carries out fast peak annealing and laser pulse annealing successively.
The difference of present embodiment and embodiment 1 only is that " carrying out the light dope ion in the Semiconductor substrate of grid both sides injects; form lightly-doped source/drain region " step is different with the execution sequence of " injecting fluorine ion and phosphonium ion in described grid " step, and carrying into execution a plan that each step is concrete is identical with embodiment 1.
Present embodiment by technology that in grid, add to inject fluorine ion after, the nmos pass transistor of preparing can be by the system performance testing of HCI, and effect is with embodiment 1; And the nmos pass transistor that adopts prior art for preparing to go out can not be by the system performance testing of HCI.
Only in grid, inject phosphonium ion in the prior art to reduce the loss of grid, and the compatibility of the present invention and prior art is very strong, just in grid, inject after the phosphonium ion or also injected fluorine ion at grid when injecting phosphonium ion, and make the part fluorine ion diffuse into gate dielectric by the fast peak annealing process, activated the fluorine ion in the gate dielectric by laser pulse annealing again, make the partial oxygen ion in the fluorine ion replacement gate dielectric, thereby form the fluorine silicon group, simultaneously because fluorine ion is repaired the function of chemical bond, and then make the interface of gate dielectric and Semiconductor substrate become finer and close, improved the interface quality between gate dielectric and Semiconductor substrate, stop and form charge trap, prevent lightly-doped source under making alive/drain region gathering electric charge, thereby improved the HCI effect of nmos pass transistor greatly.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. the manufacture method of a nmos pass transistor comprises: Semiconductor substrate is provided; Form gate dielectric and the grid that is positioned on the gate dielectric in described Semiconductor substrate; Formation source/drain region in the Semiconductor substrate of grid both sides, formation source/drain region comprises: the light dope ion injects and heavy doping ion is injected; It is characterized in that,
During formation source/drain region, in described grid, inject fluorine ion and phosphonium ion;
Also comprise: behind formation source/drain region, carry out fast peak annealing and laser pulse annealing successively;
The temperature peak scope of described fast peak annealing is 900 ℃ to 1070 ℃, and annealing time is 5 seconds to 60 seconds; The temperature peak scope of described laser pulse annealing is 1200 ℃ to 1300 ℃.
2. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, described formation source/drain region comprises successively: the light dope ion injects; In described grid, inject fluorine ion and phosphonium ion; Heavy doping ion is injected.
3. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, described formation source/drain region comprises successively: the light dope ion injects; Heavy doping ion is injected; In described grid, inject fluorine ion and phosphonium ion.
4. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, described formation source/drain region comprises successively: inject fluorine ion and phosphonium ion in described grid; The light dope ion injects; Heavy doping ion is injected.
5. according to the manufacture method of claim 2 or 3 or 4 described nmos pass transistors, it is characterized in that described light dope ion injects and comprises: be mask with the grid, in Semiconductor substrate, inject phosphonium ion or arsenic ion to form lightly-doped source/drain region; When the ion of light dope ion injection was phosphonium ion, the energy range that ion injects was 1KeV to 20KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2When the ion of light dope ion injection was arsenic ion, the energy range that ion injects was 2KeV to 35KeV, and the dosage range that ion injects is 1E14/cm
2To 1E15/cm
2
6. according to the manufacture method of claim 2 or 3 or 4 described nmos pass transistors, it is characterized in that described heavy doping ion is injected and comprised: the relative both sides at described gate dielectric and described grid form isolated side wall; Be mask with described grid and described isolated side wall, in Semiconductor substrate, inject phosphonium ion or arsenic ion to form heavy-doped source/drain region; When injecting phosphonium ion when forming heavy-doped source/drain region in Semiconductor substrate, the energy range that ion injects is 8KeV to 30KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2When injecting arsenic ion in Semiconductor substrate when forming heavy-doped source/drain region, the energy range that ion injects is 8KeV to 50KeV, and the ion implantation dosage scope is 1.5E14/cm
2To 6E15/cm
2
7. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, injection fluorine ion and phosphonium ion comprise in described grid: inject phosphonium ion at described grid earlier, inject fluorine ion then in described grid.
8. the manufacture method of nmos pass transistor according to claim 7 is characterized in that, the injection energy range of described fluorine ion is 2KeV to 20KeV, and the implantation dosage scope is 1E14/cm
2To 3E15/cm
2The injection energy range of described phosphonium ion is 3KeV to 10KeV, and the implantation dosage scope is 1E15/cm
2To 5E15/cm
2
9. the manufacture method of nmos pass transistor according to claim 1 is characterized in that, injection fluorine ion and phosphonium ion comprise in described grid: inject fluorine ion and phosphonium ion simultaneously at described grid.
10. the manufacture method of nmos pass transistor according to claim 9 is characterized in that, injects fluorine ion simultaneously and phosphonium ion comprises in described grid: directly inject PF at described grid
3And PF
5In a kind of or its combination, the injection energy range is 3KeV to 10KeV, the implantation dosage scope is 1E15/cm
2To 6E15/cm
2
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| CN104078359A (en) * | 2013-03-28 | 2014-10-01 | 中芯国际集成电路制造(上海)有限公司 | NMOS transistor and manufacturing method thereof |
| CN113224097B (en) * | 2021-04-25 | 2023-03-24 | 华虹半导体(无锡)有限公司 | Method for improving negative signal of CIS product |
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| US6274448B1 (en) * | 1998-12-08 | 2001-08-14 | United Microelectronics Corp. | Method of suppressing junction capacitance of source/drain regions |
| CN1551356A (en) * | 2003-03-31 | 2004-12-01 | 台湾积体电路制造股份有限公司 | CMOS assembly and its manufacturing method |
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