CN101431024B - Method for separately optimizing source and drain - Google Patents

Method for separately optimizing source and drain Download PDF

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CN101431024B
CN101431024B CN2007100479942A CN200710047994A CN101431024B CN 101431024 B CN101431024 B CN 101431024B CN 2007100479942 A CN2007100479942 A CN 2007100479942A CN 200710047994 A CN200710047994 A CN 200710047994A CN 101431024 B CN101431024 B CN 101431024B
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ion
inject
source
drain
substrate
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CN101431024A (en
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赵猛
王津洲
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

A method for separately optimizing a source/drain electrode comprises the following steps: forming a grid on a substrate when the substrate is prepared and a layer of oxide is formed on the substrate; carrying out ion implantation by lightly doping the source/drain electrode and forming a lightly doping source/drain region on the substrate; then carrying out the first annular ion implantation and implanting ions in the source region and the drain region; then carrying out the second ion implantation and implanting ions only in the source region; forming lateral walls on two sides of the grid; and then carrying out heavy doping ion implantation and forming a source electrode and a drain electrode on the source region and the drain region. The adoption of the optimization method not only can satisfactorily obtain short-channel characteristics but also can effectively reduce junction capacitance and leakage current and improve the voltage-breakdown resistance performance of components.

Description

The method of a kind of separately optimizing source/drain electrode
Technical field
The present invention relates to the manufacturing process field of CMOS pipe, relate in particular to the method for a kind of separately optimizing source/drain electrode.
Background technology
Along with field effect transistor (Metal Oxide Semiconductor Field Effect Transistor, abbreviation MOSFET) size constantly reduces, super shallow junction (ultra-shallow junction, abbreviation USJ) technology usually is used to improve short-channel properties (the Short Channel Effects of metal-oxide-semiconductor, be called for short SCE), however this has increased the difficulty that suppresses drain junction capacitance and leakage current greatly.
In the common CMOS manufacture craft, we only carry out a source and leak symmetrical annular ion injection after carrying out LDD ion injection formation source/drain region.Owing to form the requirement of super shallow junction, often need the annular ion of bigger concentration to inject to overcome the device property degeneration that the device short-channel effect brings.Though such method still can obtain good current drives performance in the time of can making device narrow down to profound and subtle meter level, but the Impurity Distribution gradient is excessive near but very easily causing drain region pn knot, electric field is strong excessively, thereby make junction capacitance Cj0 and leakage current excessive, badly influence the short-channel properties of metal-oxide-semiconductor.
Summary of the invention
The method that the object of the present invention is to provide a kind of new source/drain electrode to optimize reduces junction capacitance and leakage current.
The method of a kind of separately optimizing of the present invention source/leakage comprises,
1), after making substrate and on substrate, forming one deck oxide, on substrate, forms grid;
2), carry out lightly-doped source/drain ion and inject, on substrate, form lightly-doped source/drain region;
3) carry out the annular ion injection first time, again, inject ion in described source region and drain region;
4) and then carry out the second time annular ion and inject, only inject ion in described source region;
5), form side wall on the both sides of grid;
6) carry out heavy doping ion, again and inject, on described source region and drain region, form source electrode and drain electrode.
Wherein inject at for the first time annular ion,
To the PMOS device, adopt phosphonium ion, arsenic ion to inject, inject energy range between 10keV~40keV, dosage range is at 5E12/cm 2~4E13/cm 2Between, the implant angle scope is between 0~30 °;
To nmos device, adopt boron ion, BF2, indium ion to inject, inject energy range between 3keV~70keV, dosage range is between 5E12/cm2~4E13/cm2, and the implant angle scope is between 0~30 °.
Wherein inject at for the second time annular ion,
To the PMOS device, adopt phosphonium ion, arsenic ion to inject, inject energy range between 10keV~45keV, dosage range is at 1E13/cm 2~5E13/cm 2Between, the implant angle scope is between 0~30 °;
To nmos device, adopt boron ion, BF2, indium ion to inject, inject energy range between 3keV~70keV, dosage range is at 1E13/cm 2~5E13/cm 2Between, the implant angle scope is between 0~30 °.
The present invention has been owing to adopted above technical characterictic, can reduce the ion concentration in drain region effectively and do not reduce the ion concentration in source region, can reduce junction capacitance and leakage current effectively, and not reduce Devices Characteristics.
Description of drawings
Fig. 1 is the flow chart of separately optimizing source/drain electrode;
Fig. 2 is according to the formed transistor of method provided by the invention.
Embodiment
The present invention is the further improvement that the manufacturing process of existing C metal-oxide-semiconductor is made, and promptly provides a provenance/drain electrode separately optimizing method to substitute the method that existing source/drain electrode is optimized together.
Below in conjunction with a specific embodiment the present invention is done a detailed introduction, as shown in Figure 1, in the technology manufacture process of CMOS pipe, on substrate 7, make grid 1, and can form the very thin insulative sidewall of one deck; Carry out the LDD ion then and inject, form lightly doped source region 3 and drain region 4; And then carry out the first time annular ion and inject, in the source region 3 and the drain region 4 lower ion of implantation concentrations respectively, make the ion concentration in source region 3 and drain region 4 lower; And then carry out the annular ion injection second time, and promptly on the substrate on grid both sides, be coated with photoresist, after exposure, development, etching, only source region 3 is exposed, only the annular ion injection second time is carried out in source region 3, with the ion concentration increase in source region 3; Form side wall 2 in the both sides of grid then; Again the heavy doping ion injection is carried out in source region 3 and drain region 4, formed source electrode 5 and drain electrode 6.
In the present invention, because annular ion is carried out when injecting in source/drain region, it is divided into two steps and carries out, and when for the first time annular ion injects, the ion concentration of injecting is lower, and the ion concentration in formed like this drain region is lower, can reduce junction capacitance Cj0 like this; And when the second time, annular source electrode ion injected, only ion is carried out in the source region and inject, effectively increased the ion concentration in source region, improved to leak causing potential barrier reduction effect, optimized Devices Characteristics, also further optimized transistorized short-channel properties.
The NMOS pipe is identical with the manufacture craft principle of PMOS pipe, is the ionic type that injects, density, and energy is different.
1, the LDD ion injects
Concerning nmos device, adopt phosphonium ion and arsenic ion to inject more, when adopting phosphonium ion to inject, between the 4KeV, the dosage of ion is 5*10 to its energy range at 0.5KeV 14To 1*10 15Between individual/square centimeter; When arsenic ion injected, between the 5KeV, the dosage of ion was 5*10 to LDD ion implantation energy scope at 1KeV 14To 1*10 15Between individual/square centimeter;
Concerning the PMOS device,
The boron ions or BF2 ion or indium ion of adopting inject more, and when adopting the boron ion to inject, between the 15KeV, the dosage of ion is 5*10 to LDD ion implantation energy scope at 0.5KeV 14To 1*10 15Between individual/square centimeter.
2, annular ion injects
(1) for the first time annular ion injects
To the PMOS device, adopt phosphonium ion, arsenic ion to inject, inject energy range between 10keV~40keV, dosage range is at 5E12/cm 2~4E13/cm 2Between, the implant angle scope is between 0~30 °;
To nmos device, adopt boron ion, BF2, indium ion to inject, inject energy range between 3keV~70keV, dosage range is at 5E12/cm 2~4E13/cm 2Between, the implant angle scope is between 0~30 °.
(2) for the second time annular ion injects,
To the PMOS device, adopt phosphonium ion, arsenic ion to inject, inject energy range between 10keV~45keV, dosage range is at 1E13/cm 2~5E13/cm 2Between, the implant angle scope is between 0~30 °;
To nmos device, adopt boron ion, BF2, indium ion to inject, inject energy range between 3keV~70keV, dosage range is at 1E13/cm 2~5E13/cm 2Between, the implant angle scope is between 0~30 °.
3, heavy doping ion is injected, and adopts the multiple tracks ion to inject
Concerning nmos device, adopt phosphonium ion or arsenic ion to inject, when adopting phosphonium ion to inject, between the 40KeV, the dosage of ion is 2*10 to its heavy-doped source drain region ion implantation energy scope at 5KeV 13To 2*10 15Between individual/square centimeter; When adopting arsenic ion to inject, between the 45KeV, the dosage of ion is 2*10 to its heavy-doped source drain region ion implantation energy scope at 20KeV 13To 3*10 15Between individual/square centimeter.
Concerning the PMOS device, adopt boron ion or BF2 ion or indium ion to inject, when adopting the boron ion to inject, between the 8KeV, the dosage of ion is 2*10 to its heavy-doped source drain region ion implantation energy scope at 0.5KeV 13To 2*10 15Between individual/square centimeter.When adopting the BF2 ion to inject, between the 20KeV, the dosage of ion is 2*10 to its heavy-doped source drain region ion implantation energy scope at 2KeV 13To 2*10 15Between individual/square centimeter.
Present embodiment is a preferred forms of the present invention; invention which is intended to be protected far is not limited thereto; those skilled in the art all can not break away from the modifications and changes of making necessity under the spirit of the present invention, and protection scope of the present invention is exceeded with claims.

Claims (3)

1. the method for separately optimizing source/drain electrode is characterized in that, comprise,
1), making substrate and on substrate, after formation one deck oxide, on substrate, forming grid;
2), carry out lightly-doped source/drain ion and inject, on substrate, form lightly-doped source/drain region;
3) carry out the annular ion injection first time, again, inject ion in described source region and drain region;
4) and then carry out the second time annular ion and inject, only inject ion in described source region;
5), form side wall on the both sides of grid;
6) carry out heavy doping ion, again and inject, on described source region and drain region, form source electrode and drain electrode.
2. the method for a kind of separately optimizing as claimed in claim 1 source/drain electrode is characterized in that, the described annular ion injection first time,
To the PMOS device, adopt phosphonium ion, arsenic ion to inject, inject energy range between 10keV~40keV, dosage range is at 5E12/cm 2~4E13/cm 2Between, the implant angle scope is between 0~30 °;
To nmos device, adopt boron ion, BF2, indium ion to inject, inject energy range between 3keV~70keV, dosage range is at 5E12/cm 2~4E13/cm 2Between, the implant angle scope is between 0~30 °.
3. the method for a kind of separately optimizing as claimed in claim 1 source/drain electrode is characterized in that, the described annular ion injection second time,
To the PMOS device, adopt phosphonium ion, arsenic ion to inject, inject energy range between 10keV~45keV, dosage range is at 1E13/cm 2~5E13/cm 2Between, the implant angle scope is between 0~30 °;
To nmos device, adopt boron ion, BF2, indium ion to inject, inject energy range between 3keV~70keV, dosage range is at 1E13/cm 2~5E13/cm 2Between, the implant angle scope is between 0~30 °.
CN2007100479942A 2007-11-08 2007-11-08 Method for separately optimizing source and drain Active CN101431024B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102479718B (en) * 2010-11-29 2014-03-26 中芯国际集成电路制造(上海)有限公司 Manufacturing method of metal-oxide-semiconductor field effect transistor (MOSFET)
CN102737965A (en) * 2011-04-12 2012-10-17 中芯国际集成电路制造(上海)有限公司 Formation method of Halo structure
CN102683186A (en) * 2012-05-09 2012-09-19 上海宏力半导体制造有限公司 Method for inhibiting hot carrier injection and manufacture method of BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) device
CN108597997B (en) * 2018-02-28 2021-03-23 中国电子科技集团公司第十三研究所 Preparation method of ohmic contact electrode of GaN-based device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1294411A (en) * 1999-10-26 2001-05-09 三星Sdi株式会社 Method for mfg. lightly mixed leakage polar/bias structure of thin film transistor
CN1787192A (en) * 2004-12-08 2006-06-14 上海华虹Nec电子有限公司 Method for reducing injecting hot carrier of I/O NMOS device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1294411A (en) * 1999-10-26 2001-05-09 三星Sdi株式会社 Method for mfg. lightly mixed leakage polar/bias structure of thin film transistor
CN1787192A (en) * 2004-12-08 2006-06-14 上海华虹Nec电子有限公司 Method for reducing injecting hot carrier of I/O NMOS device

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