CN102693904B - Method for reducing HCI effect of I/O MOS device - Google Patents
Method for reducing HCI effect of I/O MOS device Download PDFInfo
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- CN102693904B CN102693904B CN201110069777.XA CN201110069777A CN102693904B CN 102693904 B CN102693904 B CN 102693904B CN 201110069777 A CN201110069777 A CN 201110069777A CN 102693904 B CN102693904 B CN 102693904B
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- 230000000694 effects Effects 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000005468 ion implantation Methods 0.000 claims abstract description 57
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 150000002500 ions Chemical class 0.000 claims description 69
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- 238000000059 patterning Methods 0.000 claims description 20
- -1 phosphonium ion Chemical class 0.000 claims description 11
- 125000001475 halogen functional group Chemical group 0.000 claims description 6
- 230000009467 reduction Effects 0.000 claims description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-O phosphonium Chemical compound [PH4+] XYFCBTPGUUZFHI-UHFFFAOYSA-O 0.000 claims 2
- 239000010410 layer Substances 0.000 abstract 5
- 239000002344 surface layer Substances 0.000 abstract 3
- 238000009792 diffusion process Methods 0.000 description 9
- 230000005684 electric field Effects 0.000 description 8
- 238000002513 implantation Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Abstract
The invention provides a method for reducing an HCI effect of an I/O MOS device. The method comprises the steps of providing a semiconductor substrate and forming a patterned mask layer on the semiconductor substrate; carrying out an LDD ion implantation of a first ion in a surface layer of the semiconductor substrate using the patterned mask layer as a mask; carrying out an LDD ion implantation of a second ion in the surface layer of the semiconductor substrate using the patterned mask layer as a mask, the second ion having an opposite conductive type to that of the first ion; and carrying out an LDD ion implantation of a phosphor ion in the surface layer of the semiconductor substrate using the patterned mask layer as a mask. According to the method of the invention, SCE and HCI effects can be improved through the triple LDD ion implantations of the first ion, the second ion and the phosphor ion, and with no need of adding extra mask layers; and simultaneously good electric properties of MOS device can be maintained.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of method reducing I/O MOS device HCI.
Background technology
In current integrated circuit, I/O (I/O) device is important part.Compared with core devices, I/O device has the feature of high working voltage and high driving ability.But under high working voltage, the transverse electric field that I/O device channel internal memory is stronger, charge carrier is collided ionization in transport process, produce extra electron hole pair, part hot carrier in jection gate oxide, make device threshold voltage increase, degradation under saturation current and carrier mobility, this phenomenon is called HCI (hot carrier in jection) effect.HCI effect is the problem often run in I/O device layout, is the principal element affecting device property and reliability, especially nmos device.
Because the technique being improved HCI effect by change device architecture is very complicated, consuming cost is high, reduce the dosage of light dope source/drain region (LDD) ion implantation, increase the energy of LDD ion implantation, obtain darker LDD knot to reduce transverse electric field, just become the most effective means improving HCI effect.
As shown in Figure 1, at present, phosphorus (P) the ion LDD ion implantation 103 of many employings high-energy low dosage and arsenic (As) ion LDD ion implantation 102 technique of low-yield high dose, the diffusion increasing P ion is assisted by As ion, obtain darker LDD knot 1 to reduce transverse electric field, improve HCI effect.But along with MOSFET element size constantly reduces, particularly enter into 65 nanometers and with lower node, gate oxide thickness is also more and more thinner, LDD knot also shoals thereupon.Above-mentioned technique is when LDD ion implantation, and in order to avoid puncturing of grid oxygen during ion implantation, the corresponding reduction of energy of injection, makes the LDD knot formed become more shallow, be unfavorable for improving HCI effect; On the other hand, become large because the concentration gradient between As ion with P ion is relative, the LDD diffusion region 1 of formation is more and more less with the crossover region of grid, and cause transverse electric field intensity in raceway groove to become large, device HCI effect is more and more obvious.
Therefore, it is inadequate that dosage and energy merely by changing LDD ion implantation improve HCI effect.
Summary of the invention
The object of the present invention is to provide a kind of method reducing I/O MOS device hot carrier injection effect, overcoming the simple problem by changing the dosage of LDD ion implantation and the short-channel effect caused by energy and device property decline.
For solving the problem, the present invention proposes a kind of method reducing I/O MOS device HCI effect, and the method comprises the steps:
Semiconductor substrate is provided, and forms the mask layer of patterning on the semiconductor substrate;
With the mask layer of described patterning for mask, in the top layer of described Semiconductor substrate, carry out first kind ion LDD ion implantation;
With the mask layer of described patterning for mask, in the top layer of described Semiconductor substrate, carry out Equations of The Second Kind ion LDD ion implantation, described Equations of The Second Kind ion is contrary with the conduction type of first kind ion;
With the mask layer of described patterning for mask, in the top layer of described Semiconductor substrate, carry out phosphonium ion LDD injection.
Further, the mask layer of described patterning is grid structure.
Further, described first kind ion is In ion or Ge ion.
Further, the energy of described In ion or Ge ion implantation is 5KeV ~ 20KeV, and dosage is 1E13 ~ 8E13/cm
2, angle is 0 ° ~ 11 °.
Further, described Equations of The Second Kind ion is As ion, Sb ion or Bi ion.
Further, the energy of described As ion implantation is 2KeV ~ 10KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °.
Further, the energy of described Sb ion implantation is 10KeV ~ 30KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °.
Further, the energy of described Bi ion implantation is 20KeV ~ 40KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °.
Further, described phosphonium ion LDD ion implantation is before or after described first kind ion LDD ion implantation.
Further, the energy that described phosphonium ion injects is 10KeV ~ 25KeV, and dosage is 1E13 ~ 6E13/cm
2, angle is 0 ° ~ 35 °.
Further, also comprise with described mask layer for mask before or after described first kind ion LDD ion implantation, in described Semiconductor substrate, carry out the step of halo injection.
Further, also comprised with described mask layer for mask before or after described Equations of The Second Kind ion LDD ion implantation, in described Semiconductor substrate, carry out the step of halo injection.
Further, exchange before and after described first kind ion LDD ion implantation and Equations of The Second Kind ion LDD ion implantation step.
Compared with prior art, the present invention is by the triple LDD ion implantation of first kind ion, Equations of The Second Kind ion and phosphonium ion, produce and preserve a large amount of implantation defects, increase LDD diffusion, the LDD formed is tied darker, the crossover region of LDD diffusion region and grid increases, and the concentration gradient injecting ion reduces, in raceway groove, transverse electric field intensity reduces, and then reduces HCI effect and the decline of device electrology characteristic.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of I/O nmos device in prior art
Fig. 2 is the process chart of the embodiment of the present invention;
Fig. 3 A to 3D is the cross-sectional view of the embodiment of the present invention.
Embodiment
Be described in further detail below in conjunction with the method for the drawings and specific embodiments to the reduction I/O MOS device hot carrier injection effect that the present invention proposes.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form simplified very much, only for object that is convenient, the aid illustration embodiment of the present invention lucidly.
As shown in Figure 1, the invention provides a kind of method reducing I/O nmos device hot carrier injection effect, completed by step shown in S1 to S3, below in conjunction with the technique cross-sectional view shown in the process chart shown in Fig. 2 and Fig. 3 A ~ 3D, said method is explained in detail.
S1, provides Semiconductor substrate, and forms the mask layer of patterning on the semiconductor substrate.
Please refer to Fig. 3 A, Semiconductor substrate 300 is provided, and in described Semiconductor substrate 300, form the mask layer 301 of patterning, in the present embodiment, the mask layer 301 of patterning is grid structure, by depositing gate dielectric layer and polysilicon layer in Semiconductor substrate 300, with photoresist mask plate for mask to this polysilicon layer and gate dielectric layer etching formed.Gate dielectric layer can be silica or silicon oxynitride, below 65nm technology node, and preferred high-k (high K) material, as aluminium oxide, zirconia, hafnium oxide etc.
S2, with the mask layer of described patterning for mask, carries out first kind ion LDD ion implantation in the top layer of described Semiconductor substrate.
Please refer to Fig. 3 B, with the mask layer 301 of described patterning for mask, with the vertical plane perpendicular to Semiconductor substrate 300 surface for benchmark, angled manner carries out first kind ion LDD ion implantation in the top layer of described Semiconductor substrate 300 at a certain angle, shorten injection length, improve injection efficiency, form a LDD district 302.In the present embodiment, described first kind ion is In ion or Ge ion, and the Implantation Energy of employing is 5KeV ~ 20KeV, and dosage is 1E13 ~ 8E13/cm
2, angle is 0 ° ~ 11 °.In this step, a large amount of implantation defects can be produced after first kind ion implantation, as hole etc., increase carrier mobility, the threshold voltage of adjusting device simultaneously, be conducive to the raising of device property, increase simultaneously follow-up Equations of The Second Kind ion and P ion to the diffusion bottom the mask layer 301 of Semiconductor substrate 300 well region and described patterning, the final LDD diffusion region 2 formed is deepened relatively, change in concentration along the grid structure underlying conductive channel direction of this I/O MOS device is slow, concentration gradient reduces, and then transverse electric field intensity in raceway groove is reduced, improve HCI effect.In other embodiments, also comprise with described mask layer for mask before or after described first kind ion LDD ion implantation, in described Semiconductor substrate, carry out the step of halo injection.
S3, with the mask layer of described patterning for mask, in the top layer of described Semiconductor substrate, carry out Equations of The Second Kind ion LDD ion implantation, described Equations of The Second Kind ion is contrary with the conduction type of first kind ion.
Please refer to Fig. 3 C, with the mask layer 301 of described patterning for mask, with the vertical plane perpendicular to Semiconductor substrate 300 surface for benchmark, angled manner carries out the Equations of The Second Kind ion LDD ion implantation contrary with the conduction type of first kind ion again in the top layer of described Semiconductor substrate 300 at a certain angle, shorten injection length, improve injection efficiency, form the 2nd LDD district 303.In the present embodiment, described Equations of The Second Kind ion is As ion, Sb ion or Bi ion, and wherein, the energy of described As ion implantation is 2KeV ~ 10KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °; The energy of described Sb ion implantation is 10KeV ~ 30KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °; The energy of described Bi ion implantation is 20KeV ~ 40KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °.In this step, SCE effect that first kind ion implantation causes can be eliminated after Equations of The Second Kind ion implantation and to shorten GIBL (grid the cause drain terminal electric leakage) effect caused due to raceway groove, reduce concentration gradient, reduce the intensity of transverse electric field in raceway groove, thus be conducive to the anti-breakdown performance reducing HCI effect and device gate-oxide.In other embodiments, also comprised with described mask layer for mask before or after described Equations of The Second Kind ion LDD ion implantation, in described Semiconductor substrate, carry out the step of halo injection, described Equations of The Second Kind ion LDD ion implantation step can with first kind ion LDD ion implantation step before and after exchange.
S4, with the mask layer of described patterning for mask, carries out phosphonium ion LDD injection in the top layer of described Semiconductor substrate.
Please refer to Fig. 3 D, with the mask layer 301 of described patterning for mask, with the vertical plane perpendicular to Semiconductor substrate 300 surface for benchmark, angled manner carries out phosphonium ion LDD ion implantation again in the top layer of described Semiconductor substrate 300 at a certain angle, shorten injection length, improve injection efficiency, form the 3rd LDD district 304.In this step, the injection of phosphonium ion can preserve a large amount of implantation defect of above-mentioned generation, and control LDD diffusion area, reduce SCE and HCI effect further.In the present embodiment, the energy that described phosphonium ion injects is 10KeV ~ 25KeV, and dosage is 1E13 ~ 6E13/cm
2, angle is 0 ° ~ 35 °.In other embodiments, described phosphonium ion LDD ion implantation can also be carried out before or after described first kind ion LDD ion implantation.
In sum, the present invention, by the triple LDD ion implantation of first kind ion, Equations of The Second Kind ion and phosphonium ion, produces and preserves a large amount of implantation defects, obtaining longer length of effective channel; Triple LDD ion implantation increases LDD diffusion, the LDD formed is tied darker, the crossover region of LDD diffusion region and grid increases, and the concentration gradient injecting ion reduces, in raceway groove, transverse electric field intensity reduces, and then reduces HCI effect and the decline of device electrology characteristic.The present invention does not need to increase extra mask layer, only needs to increase ion implantation technology, just can improve SCE, HCI effect, maintain again the good electrology characteristic of MOS device simultaneously.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (11)
1. reduce a method for I/O MOS device HCI effect, it is characterized in that, comprising:
Semiconductor substrate is provided, and forms the mask layer of patterning on the semiconductor substrate;
With the mask layer of described patterning for mask, in the top layer of described Semiconductor substrate, carry out first kind ion LDD ion implantation;
With the mask layer of described patterning for mask, in the top layer of described Semiconductor substrate, carry out Equations of The Second Kind ion LDD ion implantation, described Equations of The Second Kind ion is contrary with the conduction type of first kind ion;
With the mask layer of described patterning for mask, in the top layer of described Semiconductor substrate, carry out phosphonium ion LDD injection;
Wherein, described first kind ion is In ion or Ge ion, and described Equations of The Second Kind ion is As ion, Sb ion or Bi ion.
2. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, the mask layer of described patterning is grid structure.
3. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, the energy of described In ion or Ge ion implantation is 5KeV ~ 20KeV, and dosage is 1E13 ~ 8E13/cm
2, angle is 0 ° ~ 11 °.
4. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, the energy of described As ion implantation is 2KeV ~ 10KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °.
5. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, the energy of described Sb ion implantation is 10KeV ~ 30KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °.
6. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, the energy of described Bi ion implantation is 20KeV ~ 40KeV, and dosage is 3E14 ~ 8E14/cm
2, angle is 0 ° ~ 11 °.
7. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, described phosphonium ion LDD ion implantation was carried out before or after described first kind ion LDD ion implantation.
8. the method for the reduction I/O MOS device HCI effect as described in claim 1 or 7, is characterized in that, the energy that described phosphonium ion injects is 10KeV ~ 25KeV, and dosage is 1E13 ~ 6E13/cm
2, angle is 0 ° ~ 35 °.
9. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, before or after described first kind ion LDD ion implantation, also comprise: with described mask layer for mask, in described Semiconductor substrate, carry out the step of halo injection.
10. the method reducing I/O MOS device HCI effect as claimed in claim 1, it is characterized in that, before or after described Equations of The Second Kind ion LDD ion implantation, also comprise: with described mask layer for mask, in described Semiconductor substrate, carry out the step of halo injection.
11. methods reducing I/O MOS device HCI effect as claimed in claim 1, is characterized in that, exchange before and after described first kind ion LDD ion implantation and Equations of The Second Kind ion LDD ion implantation step.
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| CN201110069777.XA CN102693904B (en) | 2011-03-22 | 2011-03-22 | Method for reducing HCI effect of I/O MOS device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1787192A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for reducing injecting hot carrier of I/O NMOS device |
| CN101207085A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1787192A (en) * | 2004-12-08 | 2006-06-14 | 上海华虹Nec电子有限公司 | Method for reducing injecting hot carrier of I/O NMOS device |
| CN101207085A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
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