CN101330048A - Light dope ion injection method - Google Patents
Light dope ion injection method Download PDFInfo
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- CN101330048A CN101330048A CNA2007100421354A CN200710042135A CN101330048A CN 101330048 A CN101330048 A CN 101330048A CN A2007100421354 A CNA2007100421354 A CN A2007100421354A CN 200710042135 A CN200710042135 A CN 200710042135A CN 101330048 A CN101330048 A CN 101330048A
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- light dope
- lateral wall
- wall substrate
- dope ion
- output device
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Abstract
The invention relates to a light doping ion injecting method which comprises the following steps of: providing a semiconductor substrate which comprises a core device area and an input and output device area; forming a grid on the semiconductor substrate; implementing the light doping ion injecting to the input and output device area; forming a side wall substrate at the side wall of the grid; and implementing the light doping ion injecting to the core device area. The method can reduce the occurrence of hot-carrier effect.
Description
Technical field
The present invention relates to the ic manufacturing technology field, particularly a kind of light dope ion injection method.
Background technology
The light dope ion injects in order to form light doping section, and described light doping section comprises the lightly doped drain injection, and (Lightly Doped Drain, LDD) district and pocket type (Pocket) ion implanted region, described light doping section are used to define the leakage expansion area, source of MOS device.LDD impurity is positioned at the grid below and is close to the channel region edge, and Pocket impurity is positioned at below, LDD district and is close to the channel region edge, is source-drain area the impurity concentration gradient is provided.
It is the standard technique of the dopant material that changes conductance being introduced Semiconductor substrate that ion injects.In ion implant systems, needed dopant material is ionized in ion source, ion is accelerated into the surface that is drawn towards Semiconductor substrate behind the ion beam with predetermined energy, and the energetic ion in the ion beam is infiltrated semi-conducting material and is mounted among the lattice of semi-conducting material.
In the existing technology,, before carrying out the injection of light dope ion, need be pre-formed lateral wall substrate (offset spacer), the mask of using when itself and the common composition of grid carry out the injection of light dope ion along with reducing of critical dimension; Promptly, the step of utilizing existing technology to carry out the injection of light dope ion comprises: as shown in Figure 1, the semiconductor-based end 10 is provided, comprises core device region 12 and input and output device district 14 at described the semiconductor-based end 10, described core device region 12 and input and output device district 14 isolate by shallow trench 16; As shown in Figure 2, on the described semiconductor-based end 10, form grid 20; As shown in Figure 3, form lateral wall substrate 30 on the described semiconductor-based end 10 that forms grid 20, described lateral wall substrate 30 is bonded in the sidewall of core device region 12 inner grids 20, and around described grid 20; As shown in Figure 4, carry out the ion implant operation in core device region 12 and the input and output device district 14 respectively, and form ion injection interface 40, the ion implant operation of described core device region 12 is a mask with described lateral wall substrate 30 and grid 20.
In the practice, the complete integrated circuit of one cover comprises at least one core devices and at least one input and output device (IO device, IO device), described core devices is formed in the core device region, described input and output device is formed in the input and output device district, and the operating voltage of described input and output device (being about 2.5V) is higher than the operating voltage (being about 1.2V) of described core devices; High working voltage easily causes in the input and output device boundary edge of knot and channel region to be formed with high electric field, electronics will be subjected to this high electric field to quicken to become high energy particle in the process that moves, described high energy particle collision produces electron-hole pair (being called hot carrier), described hot carrier obtains energy from electric field, can enter in gate oxide or the grid, then influence the threshold voltage control of device and the drift of mutual conductance, promptly produce hot carrier's effect.The generation that how to suppress described hot carrier's effect is the target that industry is pursued always.
As, on September 27th, 2006, disclosed notification number was for providing the technology integrating method that improves hot carrier's effect in a kind of CMOS manufacturing in the Chinese patent of " CN1277305C ", after finishing, transistor gate polycrystalline graphical definition increases thermal oxidation technology by before gate oxidation technology, reaching respectively, with the interface trap in effective minimizing gate oxide, particularly drain terminal is near the oxide layer interface trap at polycrystalline edge, thereby reduce hot carrier captive probability in grid oxygen, improve hot carrier's effect.But adopting said method need increase processing step when suppressing described hot carrier's effect, influences production efficiency.
In addition, on June 15th, 2005, disclosed notification number provided a kind of I/O nmos device that reduces hot carrier's effect in the Chinese patent application of " CN1627532 ", described device comprises that the place, pars intermedia top that the both sides, top of silicon substrate, substrate have source region and drain region, a silicon substrate has gate oxide, has polysilicon layer on the gate oxide, the both sides of polysilicon and gate oxide have side wall, especially, the pars intermedia position of substrate is slightly higher than source region and drain region.By adopting above setting, make the peak point of the channel laterally electric field that drain voltage causes will be away from channel surface, can effectively reduce the injection of hot carrier to gate oxide, reduce the peak value electric field value in the raceway groove simultaneously, with the remarkable hot carrier's effect that improves, improve device lifetime, and then guarantee the high reliability of device.But adopting said method can cause the change of gate oxide structure when suppressing described hot carrier's effect, influence subsequent technique.
Summary of the invention
The invention provides a kind of light dope ion injection method, can reduce the generation of hot carrier's effect.
A kind of light dope ion injection method provided by the invention comprises:
The semiconductor-based end that comprises core device region and input and output device district, be provided;
On the described semiconductor-based end, form grid;
Carrying out input and output device district light dope ion injects;
Sidewall at grid forms lateral wall substrate;
Carrying out core device region light dope ion injects.
Alternatively, described light dope ion injects and comprises lightly doped drain injection and the injection of pocket type ion; Alternatively, the reaction temperature that forms the operation of described lateral wall substrate is 600～700 degrees centigrade; Alternatively, described lateral wall substrate comprises first lateral wall substrate and second lateral wall substrate; Alternatively, the described first lateral wall substrate material is a silicon dioxide; Alternatively, the described first lateral wall substrate thickness is 2～4 nanometers; Alternatively, the described second lateral wall substrate material is a silicon nitride; Alternatively, the described second lateral wall substrate thickness is 6～8 nanometers.
Compared with prior art, the present invention has the following advantages:
Light dope ion injection method provided by the invention by before forming lateral wall substrate, is carried out input and output device district light dope ion and is injected; Then, carry out the step that forms lateral wall substrate and the injection of light dope ion in turn, the operating temperature when forming lateral wall substrate to utilize strengthens the injection of injecting ion in the input and output device district and spreads; Make in input and output device district, to form to have the light doping section of higher junction depth, and then make the possibility that becomes that suppresses hot carrier's effect.
Description of drawings
Fig. 1 is explanation semiconductor-based bottom structure schematic diagram of the prior art;
Fig. 2 is for illustrating the semiconductor-based bottom structure schematic diagram behind the formation grid in the prior art;
Fig. 3 is for illustrating the semiconductor-based bottom structure schematic diagram behind the formation lateral wall substrate in the prior art;
Fig. 4 is for carrying out the semiconductor-based bottom structure schematic diagram after the light dope ion injects in the explanation prior art;
Fig. 5 is the schematic flow sheet of the execution light dope ion injection of the explanation embodiment of the invention;
Fig. 6 is the semiconductor-based bottom structure schematic diagram of the explanation embodiment of the invention;
Fig. 7 for the explanation embodiment of the invention the formation grid after semiconductor-based bottom structure schematic diagram;
Fig. 8 is the semiconductor-based bottom structure schematic diagram after the execution input and output device district light dope ion of the explanation embodiment of the invention injects;
Fig. 9 for the explanation embodiment of the invention the formation lateral wall substrate after semiconductor-based bottom structure schematic diagram;
Figure 10 is the semiconductor-based bottom structure schematic diagram after the execution core device region light dope ion of the explanation embodiment of the invention injects.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work for those skilled in the art with advantage of the present invention.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Usually, the high electric field that the boundary edge of knot and channel region forms in the device, make electronics in the process that moves, will be subjected to this high electric field to quicken to become high energy particle, described high energy particle collision produces electron-hole pair (being called hot carrier), described hot carrier obtains energy from electric field, can enter in gate oxide or the grid, influence the threshold voltage control of device and the drift of mutual conductance then, promptly produce hot carrier's effect.The generation that how to suppress described hot carrier's effect always is the target that industry is pursued.Current, industry generally acknowledges that the high electric field that the boundary edge of knot and channel region forms in device can change along with the increase of light doping section junction depth, and thus, the junction depth that how to increase the device light doping section becomes the direction that suppresses described hot carrier's effect.
In the practical work process of device, the operating voltage of device that is positioned at input and output device district is usually above the operating voltage of the device that is positioned at non-input and output device district, be the operating voltage of the operating voltage of input and output device, make how described hot carrier's effect occurs in described input and output device usually above core devices.
When suppressing described hot carrier's effect by the junction depth that increases the device light doping section, when junction depth increases, the lateral dimension of knot also has the increase of respective degrees, for core devices, the increase of the lateral dimension of knot will cause tying edge, boundary with channel region to the channel region indentation, be accompanied by dwindling of device critical dimension, this indentation will cause channel region to shorten, and very easily cause short channel effect, and then influence device performance.The present inventor thinks after analyzing that the junction depth that how to increase input and output device light doping section becomes the subject matter that the inventive method solves.
Be to increase the junction depth of input and output device light doping section, the present inventor by analysis with practice, a kind of light dope ion injection method is provided.
The step of utilizing method provided by the invention to carry out the injection of light dope ion comprises: the semiconductor-based end that comprises core device region and input and output device district is provided; On the described semiconductor-based end, form grid; Carrying out input and output device district light dope ion injects; Sidewall at grid forms lateral wall substrate; Carrying out core device region light dope ion injects.
As shown in Figure 5, the concrete steps of utilizing method provided by the invention to carry out the injection of light dope ion comprise:
Step 501: the semiconductor-based end that comprises core device region and input and output device district is provided.
As shown in Figure 6, the described semiconductor-based end 100, is for defining device active region and having finished the Semiconductor substrate that shallow trench 160 is isolated.Surface, the described semiconductor-based ends 100 has oxide layer (figure does not show); described oxide layer both can be used as 100 the separator of the grid and the described semiconductor-based end that the experience subsequent step forms, and can be used as again to carry out the injury-free protective layer in the described semiconductor-based end of protection in the light doping section forming process.Described oxide layer obtains via thermal oxidation technology.Described thermal oxidation technology is used high-temperature oxydation equipment or oxidation furnace carries out.
Usually, the complete integrated circuit of a cover comprises at least one core devices and at least one input and output device, and described core devices is formed in the core device region 120, and described input and output device is formed in the input and output device district 140.Described core device region 120 and input and output device district 140 isolate by shallow trench 160.
Step 502: as shown in Figure 7, on the described semiconductor-based end 100, form grid 200.
Comprise in the step that forms grid 200: deposition grid layer on the described semiconductor-based end 100 at described the semiconductor-based end 100; Form patterned resist layer, described patterned resist layer has gate patterns; With described patterned resist layer is mask, the described grid layer of etching.
Described grid layer material comprises polysilicon (poly).Described grid layer also can comprise metal silicide.Described metal silicide experiences annealing process then and obtains by depositing metal layers on polysilicon.
In the practice, the patterned resist layer of described formation comprises the steps such as coating, oven dry, photoetching, exposure and detection of described resist layer, related process can be used various traditional methods, the described resist layer of using can be selected any anticorrosive additive material that can be applicable in the manufacture of semiconductor for use, all repeats no more at this.
In the formation method of above-mentioned light doping section, form before the patterned resist layer at after forming grid the described semiconductor-based end, all can be included as the graphical effect that improves described resist layer and the step that under described resist layer, forms antireflecting coating (ARC), as BARC (figure does not show).When being pre-formed antireflecting coating before forming patterned resist layer, after forming described patterned resist layer, also comprise: with described patterned resist layer is mask, forms patterned described antireflecting coating; With described patterned resist layer and antireflecting coating is mask, carries out described light doping section ion implant operation.
Step 503: carry out input and output device district light dope ion and inject.
Described light dope ion injects and comprises lightly doped drain injection and the injection of pocket type ion.It is mask that light dope ion in the input and output device district injects with described grid.The lightly doped drain that forms injects interface 420 and/or the pocket type ion injects interface 440 as shown in Figure 8.
The ion injection method that relates to can adopt any traditional technology, does not repeat them here.
Particularly, implantation dosage can be 1e13～1e15 atomicity/square centimeter (atom/cm
2); Inject energy and can be 5k～10k electron-volt (eV).
Step 504: the sidewall at grid forms lateral wall substrate.
As shown in Figure 9, described lateral wall substrate 300 is in order to increase channel length under the restriction of device critical dimension, to prevent the generation of short channel effect.
As example, described lateral wall substrate can comprise first lateral wall substrate and second lateral wall substrate; In the actual production, the described first lateral wall substrate material is chosen as silicon dioxide, and for 65 nanometer technologies, the described first lateral wall substrate thickness is chosen as 2～4 nanometers; The described second lateral wall substrate material is chosen as silicon nitride, and for 65 nanometer technologies, the described second lateral wall substrate thickness is chosen as 6～8 nanometers.
Form the reaction temperature that the operation of described lateral wall substrate 300 relates to and can be 600～700 degrees centigrade.
Obtain after the processes such as described lateral wall substrate 300 experience depositions, etching, the reaction temperature that relates to can strengthen the injection diffusion of having injected ion in the input and output device district, and the junction depth of established doped region and the lateral dimension of knot are increased.For the input and output device in the input and output device district, though the injection of ion diffusion will cause the increase of the lateral dimension of knot, but the shortening of the channel dimensions that causes thus can be left in the basket, cause by strengthening the injection diffusion of ion, can realize the increase of junction depth in the input and output device light doping section, and be difficult for introducing short channel effect.
Among the present invention, the input and output device district light dope ion implant operation that operates in that forms lateral wall substrate 300 carries out afterwards, reaction temperature when causing the formation lateral wall substrate can strengthen the injection diffusion of the ion that has injected in the input and output device in the input and output device district, then, the annealing steps in the experience subsequent step can obtain the light doping section that junction depth increases in the input and output device.
Step 505: carry out core device region light dope ion and inject.
Described light dope ion injects and comprises lightly doped drain injection and the injection of pocket type ion.Light dope ion implant operation in the core device region is a mask with described grid and lateral wall substrate, and the core devices lightly doped drain of formation injects interface 422 and/or the pocket type ion injects interface 442 as shown in figure 10.
The ion injection method that relates to can adopt any traditional technology, does not repeat them here.
Particularly, implantation dosage can be 1e13～1e15 atomicity/square centimeter (atom/cm
2); Inject energy and can be 5k～10k electron-volt (eV).
Adopt method provided by the invention,, carry out input and output device light dope ion and inject by before forming lateral wall substrate; Then, carry out the step that forms lateral wall substrate and the injection of light dope ion in turn, the operating temperature when forming lateral wall substrate to utilize strengthens the injection diffusion of injection ion in the input and output device; Make in the input and output device, to form to have the light doping section of higher junction depth, and then make the possibility that becomes that suppresses described hot carrier's effect.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (8)
1. a light dope ion injection method is characterized in that, comprising:
The semiconductor-based end that comprises core device region and input and output device district, be provided;
On the described semiconductor-based end, form grid;
Carrying out input and output device district light dope ion injects;
Sidewall at grid forms lateral wall substrate;
Carrying out core device region light dope ion injects.
2. light dope ion injection method according to claim 1 is characterized in that: described light dope ion injects and comprises lightly doped drain injection and the injection of pocket type ion.
3. light dope ion injection method according to claim 1 is characterized in that: the reaction temperature that forms the operation of described lateral wall substrate is 600～700 degrees centigrade.
4. light dope ion injection method according to claim 1 is characterized in that: described lateral wall substrate comprises first lateral wall substrate and second lateral wall substrate.
5. light dope ion injection method according to claim 4 is characterized in that: the described first lateral wall substrate material is a silicon dioxide.
6. light dope ion injection method according to claim 4 is characterized in that: the described first lateral wall substrate thickness is 2～4 nanometers.
7. light dope ion injection method according to claim 4 is characterized in that: the described second lateral wall substrate material is a silicon nitride.
8. light dope ion injection method according to claim 4 is characterized in that: the described second lateral wall substrate thickness is 6～8 nanometers.
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| CNA2007100421354A CN101330048A (en) | 2007-06-18 | 2007-06-18 | Light dope ion injection method |
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| CNA2007100421354A CN101330048A (en) | 2007-06-18 | 2007-06-18 | Light dope ion injection method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102456554A (en) * | 2011-11-11 | 2012-05-16 | 上海华力微电子有限公司 | Method for reducing GIDL (gate-induced drain leakage) effect of MOS IO (metal oxide semiconductor input-output) apparatus |
| CN102683351A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | One-time programmable device and integrated circuit |
| CN101996949B (en) * | 2009-08-11 | 2012-09-26 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN110739273A (en) * | 2019-10-30 | 2020-01-31 | 华虹半导体(无锡)有限公司 | Manufacturing method of ultra-thin grid CMOS device |
-
2007
- 2007-06-18 CN CNA2007100421354A patent/CN101330048A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101996949B (en) * | 2009-08-11 | 2012-09-26 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102456554A (en) * | 2011-11-11 | 2012-05-16 | 上海华力微电子有限公司 | Method for reducing GIDL (gate-induced drain leakage) effect of MOS IO (metal oxide semiconductor input-output) apparatus |
| CN102683351A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | One-time programmable device and integrated circuit |
| CN110739273A (en) * | 2019-10-30 | 2020-01-31 | 华虹半导体(无锡)有限公司 | Manufacturing method of ultra-thin grid CMOS device |
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