CN101740576A - SONOS flash memory unit and manufacturing method thereof - Google Patents
SONOS flash memory unit and manufacturing method thereof Download PDFInfo
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- CN101740576A CN101740576A CN200810044023A CN200810044023A CN101740576A CN 101740576 A CN101740576 A CN 101740576A CN 200810044023 A CN200810044023 A CN 200810044023A CN 200810044023 A CN200810044023 A CN 200810044023A CN 101740576 A CN101740576 A CN 101740576A
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Abstract
The invention discloses an SONOS flash memory unit and a manufacturing method thereof, wherein an SONOS component and a selected transistor both adopt enhanced PMOS components, therefore, the substrate bias of the components can be realized without a deep N-well process. A P-type buried channel on the surface of an N-well can provide a great deal of cavities for the programming of the SONOS component, thereby greatly improving the programming efficiency and overcoming the defects of large effective quality and difficult programming of the cavities. The P-type SONOS component can obtain a programming and erasing threshold voltage which is more symmetrical than that of an N-type SONOS component; furthermore, the invention ensures that the drain electrode implantation volume is larger than that of a source electrode, increases the effective channel length and creates conditions for shortening the size of the components by fully utilizing the characteristic of small grid spacing between the two components of the flash memory unit and adopting source-drain ion implantation with large angle and light dope; and finally, the invention further reduces the short channel effect by carrying out bag-shaped ion implantation on the two components of the flash memory unit.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit structure, particularly relate to a kind of SONOS flash cell.
Background technology
SONOS (silicon-oxide-nitride--oxide-silicon, Silicon-Oxide-Nitride-Oxide-Silicon) flash memory is that (silica-silicon-nitride and silicon oxide, Oxide-Nitride-Oxide) erase function of flash memory is realized in silicon nitride store electrons in the dielectric layer or hole by ONO.Charge carrier (electronics or hole) is by adding bias voltage between grid, drain electrode and raceway groove, finishing migration by tunnel current.
The SONOS flash cell is to add that by a SONOS device selection transistor of a series connection constitutes.In the erasable process to the SONOS flash cell, the source electrode of SONOS device, the transistorized source electrode of selection and drain electrode all are in floating state.And in the process that the SONOS flash cell " is read ", select transistor to be in the conducting operating state.
Present SONOS flash cell is all based on NMOS, and the SONOS device adopts the buried channel nmos device, and keeping this device initial threshold voltage is negative value, guarantees to be in conducting state after device is wiped.Usually wiping of N type SONOS device do not programmed fully, and N type buried channel can provide a large amount of electronics when programming, improve programing effect.N type SONOS device must be put into dark N trap in addition, so that with the raceway groove and the substrate isolation of SONOS device, so that be added with bias voltage on raceway groove.Dark N trap has increased the complexity of technology.
Summary of the invention
Technical problem to be solved by this invention provides a kind of SONOS flash cell, based on PMOS, has more performance, and technology realizes simple.For this reason, the present invention also provides the manufacture method of above-mentioned SONOS flash cell.
For solving the problems of the technologies described above, SONOS flash cell of the present invention comprises the SONOS device and selects transistor that this flash cell comprises:
P type silicon substrate 10 is at this flash cell orlop;
P type buried channel 12, on described N trap 11, comprise the drain electrode 23 of SONOS device, shared source electrode 24, the transistorized raceway groove 112 of selection and the selection transistor drain 25 of raceway groove 111, SONOS device and selection transistor of SONOS device in the described P type buried channel 12;
Ono dielectric 13 is on the raceway groove 111 of described SONOS device;
The polysilicon gate 21 of SONOS device is on described ono dielectric 13;
Select transistorized polysilicon gate 22, on described gate oxide 14;
Silicon nitride side wall 17, in the two side of the polysilicon gate 21 and the silicon nitride 16 of described ono dielectric 13, SONOS device, also at described gate oxide 14, select the two side of transistorized polysilicon gate 22 and silicon nitride 16.
The manufacture method of above-mentioned SONOS flash cell comprises the steps:
The 1st step, on P type silicon substrate 10, adopt ion implantation technology to inject N type impurity, form N trap 11, then on N trap 11, adopt ion implantation technology to inject p type impurity, form P type buried channel 12;
In the 2nd step, at silicon chip surface deposit one deck ono dielectric 13 and one deck silica 14, described ono dielectric 13 is horizontal with 14 one-tenth of silica;
The 3rd step, at silicon chip surface deposit one deck polysilicon 15, adopt ion implantation technology that this layer polysilicon 15 injected N type impurity again, then deposit one deck silicon nitride 16 on this layer N type polysilicon 15 adopts photoetching and etching technics to etch the polysilicon gate 21 and the transistorized polysilicon gate 22 of selection of SONOS device then;
The 4th step, adopt bag shape ion implantation technology that silicon chip is injected N type impurity, adopt the light dope ion implantation technology that silicon chip is injected p type impurity again, form lightly doped drain injection region 231, the SONOS device of SONOS device and select the shared lightly-doped source injection region 241 of transistor and select transistorized lightly doped drain injection region 251, described three light dope injection regions 231,241,251 all are the P types;
The 5th step, at silicon chip surface deposit one deck silicon nitride 17, anti-carve this layer silicon nitride 17 again, stay silicon nitride side wall 17 at the grid 21 of ono dielectric 13, SONOS device and the two side of silicon nitride 16, also stay silicon nitride side wall 17 in the two side of silica 14, the transistorized grid 14 of selection and silicon nitride 16;
The 6th goes on foot, and the employing source is leaked injection technology silicon chip is carried out the injection of P type ion, forms drain electrode 23, the SONOS device of SONOS device and selects the shared source electrode 24 of transistor and selection transistor drain 25.
SONOS flash cell of the present invention and manufacture method thereof are compared with traditional SONOS flash cell, have following characteristics:
1, SONOS device and selection transistor all adopt the PMOS device, therefore need not dark N-well process and just can realize the device substrate biasing.
2, SONOS device and selection transistor all adopt buried channel PMOS device, but still are enhancement devices.The programming that the P type buried channel on N trap surface can be the SONOS device provides a large amount of holes, improve programming efficiency greatly, has overcome the hole owing to programme the greatly shortcoming of difficulty of effective mass.P type SONOS device can obtain than more symmetrical programming and the erase threshold voltage of N type SONOS device.
3, make full use of the little characteristics of gate pitch of two devices (SONOS device and selection transistor) of flash cell, adopt the lightly-doped source of wide-angle to leak the ion injection, make the drain electrode injection rate far more than source electrode, increased length of effective channel, dwindle creating conditions for size of devices.
4, two devices to flash cell carry out a bag shape example injection, further reduce short-channel effect.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 f is the silicon chip generalized section of SONOS flash cell of the present invention;
Fig. 1 a～Fig. 1 f is each step silicon chip generalized section of the manufacture method of SONOS flash cell of the present invention.
Reference numeral is among the figure: 10-P type silicon substrate; The 11-N trap; The raceway groove of 111-SONOS device; 112-selects transistorized raceway groove; 12-P type buried channel; The 13-ONO medium; The 14-silica; The 15-polysilicon; The 16-silicon nitride; The 17-silicon nitride; The grid of 21-SONOS device; 22-selects transistorized grid; The drain electrode of 23-SONOS device; The lightly doped drain injection region of 231-SONOS device; 24-SONOS device and the shared source electrode of selection transistor; 241-SONOS device and the shared lightly-doped source injection region of selection transistor; 25-selects transistor drain; 251-selects transistorized lightly doped drain injection region.
Embodiment
The 1st step saw also Fig. 1 a, adopted ion implantation technology to inject N type impurity on P type silicon substrate 10, formed N trap 11.N type impurity commonly used has phosphorus, arsenic, antimony etc.Then on N trap 11, adopt ion implantation technology to inject p type impurity, form P type buried channel 12.P type impurity commonly used has boron etc.
The 2nd step saw also Fig. 1 b, at silicon chip surface deposit one deck ONO (silicon oxide/silicon nitride/silicon oxide) medium 13 and one deck silica 14, was respectively applied for the gate dielectric layer and the gate oxide of SONOS device.14 one-tenth of ono dielectric 13 and silica are horizontally but not be arranged above and below.
For example, can be earlier at the complete deposit one deck of silicon chip surface silica 14, then resist coating exposes etching window behind the exposure imaging, and this etching window is the zone that silicon chip surface is wished the deposit ono dielectric.Etch away silica in this etching window, the deposit ono dielectric 13 again, remove photoresist.
The silica 14 of deposit in this step will be used for make selecting transistorized grid, and under the preferable case, the thickness of silica 14 is about 1.5 times of thickness of ono dielectric 13.
The 3rd step saw also Fig. 1 c, at silicon chip surface deposit one deck polysilicon 15, adopted ion implantation technology that this layer polysilicon injected N type impurity again, then deposit one deck silicon nitride 16 on this layer N type polysilicon 15.
For example, ion injects can select phosphorus, and implantation dosage is 3 * 10
15Ions/cm
2(every square centimeter in ion)～8 * 10
15Ions/cm
2
And then resist coating on the silicon chip, expose etching window behind the exposure imaging, this etching window is the zone of SONOS device except that grid.In this etching window, etch away silicon nitride 16, polysilicon 15, ono dielectric 13 and/or silica 14, form two polysilicon gates 21,22 of SONOS flash cell.Wherein the polysilicon gate 21 of SONOS device selects transistorized polysilicon gate 22 on silica 14 on ono dielectric 13, and silica 14 is as gate oxide.
The 4th step, see also Fig. 1 d, adopt bag shape ion to inject (pocket implant) technology silicon chip is injected N type impurity, adopt the light dope ion to inject (LDD) technology again silicon chip is injected p type impurity, because stopping of silicon nitride 16, the zone that this two secondary ion injects all is that silicon chip surface is not by the zone that orthographic projection covered of silicon nitride 16.Form the lightly doped drain injection region 231, SONOS device of SONOS device this moment and select the shared lightly-doped source injection region 241 of transistor and select transistorized lightly doped drain injection region 251, these three light dope injection regions 231,241,251 all are the P types.Being the raceway groove 111 of SONOS device between lightly doped drain injection region 231 and the lightly-doped source injection region 241, is to select transistorized raceway groove 112 between lightly-doped source injection region 241 and the lightly doped drain injection region 251.
So-called bag shape ion injects and is meant at the source electrode of MOS transistor and the example that injects around the drain electrode with substrate doping homomorphosis, is injected to p type impurity as the bag shape ion of NMOS pipe.For example, the bag shape ion in this step injects and can select arsenic ion.Inject by bag shape arsenic ion, in the SONOS of short channel device and selection transistor, obtain moderate threshold voltage.
The light dope ion injects can select wide-angle, dosage, low-energy boron ion to inject, and the angle that ion injects is 40 degree～60 degree (is benchmark with the vertical line), and ion implantation dosage is 1 * 10
13Ions/cm
2(every square centimeter in ion)～1 * 10
14Ions/cm
2, ion implantation energy is 1keV～10keV.
Because injecting, the light dope ion adopts wide-angle, therefore utilize the grid of adjacent SONOS device and select shadow effect between the transistorized grid, reduce the SONOS device and select the overlapping of the shared source electrode of transistor and two grids, the asymmetry that leak in the realization source reduces short-channel effect.
Can also there be gate oxidation technology in this step before bag shape ion injects, promptly make superficial growth one deck silica of two grids 21,22 and P type buried channel 12 by heating.(not shown)
The 5th step, see also Fig. 1 e, at silicon chip surface deposit one deck silicon nitride 17, anti-carve this layer silicon nitride 17 again until exposing silicon chip surface, also leave silicon nitride side wall 17 at the grid 21 of ono dielectric 13, SONOS device and the two side of silicon nitride 16 this moment, also leaves silicon nitride side wall 17 in the two side of silica 14, the transistorized grid 14 of selection and silicon nitride 16.
The 6th step, see also Fig. 1 f, the employing source is leaked injection technology silicon chip is carried out the injection of P type ion, the lightly doped drain injection region 231 of SONOS device and below form the drain electrode 23 of SONOS device, the SONOS device and select the shared lightly-doped source injection region 241 of transistor and below form the SONOS device and select the shared source electrode 24 of transistor, select transistorized lightly doped drain injection region 251 and below form and select transistor drain 25.
The source in this step is leaked ion and is injected, and implant angle is a zero degree, with the grid that prevents adjacent SONOS device with select shadow effect between the transistorized grid.
The SONOS flash cell of Zhi Zaoing according to the method described above, SONOS device wherein and select transistor to be P type MOS transistor, and non-traditional nmos pass transistor.P type SONOS device and selection transistor are directly finished on P type buried channel, and P type buried channel is on N trap surface, and the N trap is nature and the isolation of P type silicon substrate, therefore need not traditional dark N-well process.
And SONOS device and selection transistor are the p type buried layer raceway groove on the N type polysilicon bar utmost point and surface, and threshold voltage is negative value, and this shows that these two devices are reinforcing MOS transistor.Because initial threshold voltage is less, guarantees normally to end at the erase status device.P type buried layer is on N trap surface, and the N trap provides enough electronics for wiping of device.
Moreover, the present invention adopts the lightly-doped source of wide-angle to leak the ion injection, make full use of the grid of SONOS device and selected shadow effect between the transistorized grid, reduce the overlapping of common-source and two grids, the asymmetric light dope of realizing source electrode and drain electrode injects, increase length of effective channel, can create conditions for littler device size.
At last, the SONOS device in the SONOS flash cell of the present invention is together and carries out with the transistorized channel doping of selection (the bag shape ion injection in the 4th step), lightly-doped source leakage ion injection (the light dope ion in the 4th step injects) and source leakage ion injection (the 6th goes on foot).
Claims (9)
1. a SONOS flash cell comprises the SONOS device and selects transistor, and it is characterized in that: this flash cell comprises:
P type silicon substrate (10) is at this flash cell orlop;
N trap (11) is on described P type silicon substrate (10);
P type buried channel (12), on described N trap (11), comprise raceway groove (111), the SONOS device of drain electrode (23), the SONOS device of SONOS device in the described P type buried channel (12) and select the shared source electrode (24) of transistor, select transistorized raceway groove (112) and selection transistor drain (25);
Ono dielectric (13) is on the raceway groove (111) of described SONOS device;
The polysilicon gate of SONOS device (21) is on described ono dielectric (13);
Gate oxide (14) is on the transistorized raceway groove of described selection (112);
Select transistorized polysilicon gate (22), on described gate oxide (14);
Silicon nitride (16) is on described two polysilicon gates (21,22);
Silicon nitride side wall (17), in the two side of the polysilicon gate (21) and the silicon nitride (16) of described ono dielectric (13), SONOS device, also at described gate oxide (14), select the two side of transistorized polysilicon gate (22) and silicon nitride (16).
2. SONOS flash cell according to claim 1 is characterized in that: described SONOS device is P type reinforcing MOS transistor with selecting transistor.
3. SONOS flash cell according to claim 1 is characterized in that: the thickness of described gate oxide (14) is 1.5 times of ono dielectric (13).
4. the manufacture method of a SONOS flash cell as claimed in claim 1, it is characterized in that: this method comprises the steps:
The 1st step, go up the employing ion implantation technology at P type silicon substrate (10) and inject N type impurity, form N trap (11), then go up the employing ion implantation technology and inject p type impurity at N trap (11), form P type buried channel (12);
In the 2nd step, at silicon chip surface deposit one deck ono dielectric (13) and one deck silica (14), described ono dielectric (13) becomes horizontal with silica (14);
The 3rd step, at silicon chip surface deposit one deck polysilicon (15), adopt ion implantation technology that this layer polysilicon (15) injected N type impurity again, then deposit one deck silicon nitride (16) on this layer N type polysilicon (15) adopts photoetching and etching technics to etch the polysilicon gate (21) and the selection transistorized polysilicon gate (22) of SONOS device then;
The 4th step, adopt bag shape ion implantation technology that silicon chip is injected N type impurity, adopt the light dope ion implantation technology that silicon chip is injected p type impurity again, form lightly doped drain injection region (231), the SONOS device of SONOS device and select the shared lightly-doped source injection region (241) of transistor and selection transistorized lightly doped drain injection region (251), described three light dope injection regions (231,241,251) all are the P types;
The 5th step, at silicon chip surface deposit one deck silicon nitride (17), anti-carve this layer silicon nitride (17) again, stay silicon nitride side wall (17) at the grid (21) of ono dielectric (13), SONOS device and the two side of silicon nitride (16), also at silica (14), select the two side of transistorized grid (14) and silicon nitride (16) to stay silicon nitride side wall (17);
The 6th goes on foot, and the employing source is leaked injection technology silicon chip is carried out the injection of P type ion, forms drain electrode (23), the SONOS device of SONOS device and selects the shared source electrode (24) of transistor and selection transistor drain (25).
5. the manufacture method of SONOS flash cell according to claim 2 is characterized in that: in the 3rd step of described method, adopt ion implantation technology that polysilicon (15) is injected phosphorus, ion implantation dosage is 3 * 10
15Ions/cm
2～8 * 10
15Ions/cm
2
6. the manufacture method of SONOS flash cell according to claim 2, it is characterized in that: in the 3rd step of described method, the polysilicon gate (21) of the SONOS device that etches is on ono dielectric (13), and the transistorized polysilicon gate of the selection that etches (22) is on gate oxide (14).
7. the manufacture method of SONOS flash cell according to claim 2 is characterized in that: in the 4th step of described method, adopt the light dope ion implantation technology to inject boron to silicon chip, the angle that ion injects is 40 degree～60 degree, and ion implantation dosage is 1 * 10
13Ions/cm
2～1 * 10
14Ions/cm
2, ion implantation energy is 1keV～10keV.
8. the manufacture method of SONOS flash cell according to claim 2, it is characterized in that: in the 4th step of described method, before bag shape ion injects, earlier silicon chip is heated, in the side of two polysilicon gates (21,22) and superficial growth one deck silica of P type buried channel (12).
9. the manufacture method of SONOS flash cell according to claim 2 is characterized in that: in the 6th step of described method, the angle that the ion injection is leaked in the source is a zero degree.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102324429A (en) * | 2011-09-29 | 2012-01-18 | 上海宏力半导体制造有限公司 | New type double transistor SONOS flash memory unit structure and method of operation thereof |
| CN103021948A (en) * | 2011-09-22 | 2013-04-03 | 上海华虹Nec电子有限公司 | Process integrating method for deep-submicron semiconductor device |
| CN105679712A (en) * | 2015-12-31 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Technique for SONOS device |
| CN105742249A (en) * | 2014-12-12 | 2016-07-06 | 上海华虹宏力半导体制造有限公司 | Method for improving SONOS memory reading operation capability |
| CN106373965A (en) * | 2016-11-09 | 2017-02-01 | 上海华力微电子有限公司 | Manufacturing method for integrating 5 V device and SONOS storage device |
| CN108054168A (en) * | 2017-11-14 | 2018-05-18 | 上海华力微电子有限公司 | Flash memory unit structure and its manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1208836C (en) * | 2001-04-11 | 2005-06-29 | 华邦电子股份有限公司 | Electrically-erasable programmable internal storage device and its production method |
| CN100343981C (en) * | 2004-09-16 | 2007-10-17 | 中芯国际集成电路制造(上海)有限公司 | Method for producing embedded flash memory |
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2008
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103021948A (en) * | 2011-09-22 | 2013-04-03 | 上海华虹Nec电子有限公司 | Process integrating method for deep-submicron semiconductor device |
| CN102324429A (en) * | 2011-09-29 | 2012-01-18 | 上海宏力半导体制造有限公司 | New type double transistor SONOS flash memory unit structure and method of operation thereof |
| CN105742249A (en) * | 2014-12-12 | 2016-07-06 | 上海华虹宏力半导体制造有限公司 | Method for improving SONOS memory reading operation capability |
| CN105742249B (en) * | 2014-12-12 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | Improve the method for SONOS memory read operations abilities |
| CN105679712A (en) * | 2015-12-31 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Technique for SONOS device |
| CN106373965A (en) * | 2016-11-09 | 2017-02-01 | 上海华力微电子有限公司 | Manufacturing method for integrating 5 V device and SONOS storage device |
| CN108054168A (en) * | 2017-11-14 | 2018-05-18 | 上海华力微电子有限公司 | Flash memory unit structure and its manufacturing method |
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