KR101033224B1 - Flash memory device and method for fabricating the same - Google Patents

Abstract

The flash memory device of the present invention comprises a substrate, an insulating film disposed on the substrate, a first conductive semiconductor layer disposed on the insulating film in the cell region, select transistors and memory cells disposed on the semiconductor layer, and selection It is disposed in the semiconductor layer below the transistor, and includes an impurity layer of a first conductivity type higher than that of the semiconductor layer.

Charge-Trap Flash Memory, Hot Hole, Erased, SONOS

Description

Flash memory device and method for fabricating the same {Flash memory device and method for fabricating the same}

The present invention relates to a method for manufacturing a flash memory device, and more particularly, to a method for manufacturing a charge trap type flash memory device.

The development of NAND flash memory devices is proceeding with the development of devices having a small size and a high capacity as with other semiconductor memory devices. In particular, the charge trap type flash memory is considered as the next generation NAND flash memory device to meet these demands.

1 is a cross-sectional view illustrating an example of a flash memory device having a charge trap layer.

A tunneling layer 110 made of an oxide film is formed on a substrate 100 such as a silicon substrate. The impurity regions 102 such as the source / drain are disposed in the substrate 100 so as to be spaced apart from each other by a predetermined interval, and the channel region 104 is disposed therebetween. A silicon nitride film is formed as the charge trap layer 120 on the tunneling layer 110, and an insulating film as the blocking layer 130 and a control gate electrode 140 are sequentially disposed thereon.

When the control gate electrode 140 is positively charged and an appropriate bias is applied to the impurity region 102, hot electrons from the substrate 100 are trapped in the charge trap layer 120. To be trapped. This is the operation of writing to or programming a memory cell. On the other hand, when the control gate electrode 140 is negatively charged and an appropriate bias is applied to the impurity region 102, holes from the substrate are also trapped in the trap site in the charge trap layer 120. Holes trapped in the charge trap layer recombine with the extra electrons already in the trap site, which is the erase operation of the programmed memory cell.

As the size of the memory device is reduced, the cell size of the chip is rapidly decreasing to increase the degree of integration. There are many difficulties in reducing cell size in current floating gate or charge trapping devices. In particular, in order to form a device isolation layer and a gate structure, it is advantageous to have a small stack structure, but since the charge trap device traps electrons in the nitride film, the stack height is smaller than the polysilicon floating gate used in the floating gate device. have. In the development of such a charge trapping flash memory, it is necessary to develop a manufacturing process of a charge trapping device capable of enlarging a program / erase window without being more complicated than existing processes. .

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a charge trapping flash memory device having a structure capable of simplifying a process and improving an integration degree.

Another object of the present invention is to provide a method for manufacturing a charge trap type flash memory device having a structure that can simplify the process and improve the degree of integration.

In order to achieve the above technical problem, a flash memory device according to the present invention includes a substrate, an insulating film disposed on the substrate, a first conductive semiconductor layer disposed on the insulating film in the cell region, and a selection disposed on the semiconductor layer. And an impurity layer of a first conductivity type disposed in the semiconductor layer below the transistor and the memory cells and the selection transistor, and having a higher concentration than that of the semiconductor layer.

The semiconductor layer may be formed of a polysilicon film doped with N-type impurities at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3.

The selection transistor may be a MOS transistor having a gate insulating layer stacked on the semiconductor layer and a gate electrode disposed on the gate insulating layer.

The memory cell may include a tunneling layer, a charge trap layer, a blocking layer, and a control gate electrode sequentially stacked on the semiconductor layer.

The impurity layer may be disposed from the outside of the selection transistor to a half region of the channel, and may be doped with an N-type impurity at a concentration of 1 × 10 ¹⁷ ions / cm 3 to 1 × 10 ²¹ ions / cm 3. .

According to another aspect of the present invention, there is provided a method of manufacturing a flash memory device, the method including sequentially forming a first insulating film and a semiconductor layer on a substrate, defining a device isolation region of the semiconductor layer, and Forming a tunneling layer and a charge trapping layer of a memory cell on the resultant, forming a second insulating film on the resultant to be used as a gate insulating layer and a blocking layer of the memory cell, and Forming an impurity layer for increasing hot hole generation in the semiconductor layer, forming a gate conductive film on the second insulating film, and patterning the gate conductive film, the second insulating film, the charge trap layer, and the tunneling layer. And forming a gate stack of memory cells.

The semiconductor layer may be formed of a polysilicon film doped with N-type impurities at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3.

The semiconductor layer can be formed to a thickness of 100 to 600 kPa.

Defining an isolation region of the semiconductor layer may include etching the semiconductor layer in an inactive region, filling a region in which the semiconductor layer is etched with an insulating film, and planarizing the insulating film. have.

In the forming of the impurity layer, after the diffusion of the impurity, the impurity layer may be positioned from the outside of the selection transistor to a half region of the channel.

In the step of forming the impurity layer, the N-type impurity ions may be implanted at an energy of about 5 to 15 KeV and a concentration of 1 × 10 ¹⁷ ions / cm 3 to 1 × 10 ²¹ ions / cm 3.

The gate conductive layer may be formed of a polysilicon layer or a metal doped with a P-type dopant having a large work function.

After forming the gate stack of the selection transistor and the memory cell, the method may further include implanting impurities into the semiconductor layer at one edge of the selection transistor. At this time, an N-type impurity can be implanted at an energy of about 5 to 25 KeV and a concentration of 1 × 10 ¹⁷ ions / cm 3 to 1 × 10 ²¹ ions / cm 3.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below.

2 to 7 are cross-sectional views illustrating a method of manufacturing a charge trap type flash memory device according to the present invention.

Referring to FIG. 2, after forming an insulating film 210 such as an oxide film on the semiconductor substrate 200, a polysilicon film 220 is formed on the insulating film. The insulating film 210 is for electrically separating the semiconductor substrate 200 and the polysilicon film 220. The insulating film 210 is formed to a thickness of 1,000 Å or more so that the semiconductor substrate 200 and the polysilicon film 220 do not conduct with each other. do. The polysilicon layer 220 serves as a well in which a channel is formed in the charge trap type flash memory device. The polysilicon film 220 is thin because the on / off characteristics of the cell are not well seen when it is thick. However, the polysilicon film 220 is formed to a thickness that does not directly conduct from the source to the drain when a source / drain is formed in a subsequent process and a bias is applied. . That is, the thickness of the polysilicon film 220 should be determined so as to be conductive through each word line. This may vary depending on a bias condition. In a general bias condition, the thickness of the polysilicon film 220 may be determined within a range of 100 to 600 kHz. Since the doping concentration of the polysilicon film 220 does not exhibit an off characteristic due to a large current at high concentrations, the N-type impurities are doped at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3 Degree is preferred.

Referring to FIG. 3, the polysilicon film 220 in the inactive region is etched and the etched region is filled with an insulating film (not shown) and then planarized to limit the active region. Since the insulating film 210 is formed between the semiconductor substrate 200 and the polysilicon film 220, the thickness of the polysilicon film 220 may be etched to limit the active region. This method is advantageous in terms of etching thickness compared to the method of filling the trench isolation layer, and also increases the filling margin for filling the region in which the polysilicon layer is etched into the insulating layer.

Next, the tunneling layer 230 and the charge trap layer 240 are formed on the polysilicon film 220 having the active region defined therein. The tunneling layer 230 may be formed of, for example, an oxide film, and may be formed to a thickness capable of F-N tunneling, for example, a thickness of about 10 to about 40 kPa. The charge trap layer 240 may be formed of a silicon nitride film, and may be formed to a thickness of about 40 to 150 kV so that electrons that may change a threshold voltage may be trapped during a program operation.

A photoresist pattern 250 is formed on the charge trap layer 240 to define a region where the selection transistor is to be formed. Using the photoresist pattern 250 as a mask, the charge trap layer and the tunneling layer of the region where the selection transistor is to be formed are removed. When the charge trap layer and the tunneling layer remain in the selection transistor region, a hot hole that contributes to erasure in the erase operation after completion of the device has an electric field between the gate of the selection transistor and the polysilicon layer 220. This is because the phenomenon of tunneling and programming to the charge trap layer in the selection transistor region occurs. In order to prevent this phenomenon, the tunneling layer and the charge trap layer of the selection transistor region are removed to form a MOS transistor.

Referring to FIG. 4, after the charge trap layer and the tunneling layer of the select transistor are removed, the photoresist pattern is removed, and then, for example, an oxide film 260 is formed on the resultant. The oxide layer 260 is used as a blocking layer of a memory cell and a gate insulating layer of a selection transistor. The blocking layer serves to prevent the charge trapped in the charge trap layer 240 of the memory cell from moving to the control gate and is formed to a thickness of about 50 to 150 Å.

Next, an ion implantation process is performed to increase the generation of hot holes in the selection transistors. To this end, first, a photoresist pattern 270 is formed on the resultant in which the oxide film 260 is formed to expose a region where the selection transistor is to be formed. Using the photoresist pattern 270 as a mask, the polysilicon film 220 has an energy of about 5 to 15 KeV and an N-type impurity, for example, an (As) ion, and 1 × 10 ¹⁷ ions / cm 3 to 1 × Inject at a concentration of 10 ²¹ ions / cm 3.

As described above, since the polysilicon layer 220 on which the channel is to be formed is doped at a low concentration for on / off characteristics, the channel region of the selection transistor may be high in order to increase the generation of hot holes that will contribute to erasure of the memory cell. Doped with If the region in which the channel of the select transistor is to be formed is heavily doped before the gate is formed, N-type impurities are accumulated in the channel region by lateral diffusion. Select transistors must not only act as on / off switches, but also generate hot holes through gate induced drain leakage (GIDL). In order for the GIDL to be well, the polysilicon film 220 must be bent at a high doping concentration because the band must be bent by a reverse bias. However, if the doping concentration is too high and the concentration of the entire surface of the channel region is high, the on / off characteristic is not shown. Therefore, the impurity layer formed by diffusion by the subsequent thermal process is located up to about 1/2 of the channel region of the selection transistor. It is desirable to adjust the doping concentration so that it is. When a hot hole occurs, when a negative bias is applied to the word line of the memory cell, the hot hole is recombined with electrons trapped in the charge trap layer, thereby erasing. As the number of hot holes increases, the length of diffusion of the hot holes increases, so that the number of memory cells can be increased, thereby increasing the degree of integration.

Referring to FIG. 5, a photoresist pattern used as an ion implantation mask is removed, and then a gate conductive film is formed on the resultant. The gate conductive layer is formed of a polysilicon layer doped with a high P-type dopant having a high work function of 1 × 10 ²⁰ ions / cm 3 or more in order to prevent back tunneling due to the inflow of electrons from the gate when the gate voltage increases. In some cases, it may be formed of a metal film such as titanium (Ti), tantalum (Ta), or tungsten (W).

A photoresist pattern 300 for patterning a gate is formed on the gate conductive layer. Using the photoresist pattern 300 as a mask, the gate conductive layer, the oxide layer 260, the charge trap layer 240, and the tunneling layer 230 are sequentially etched to form gate stacks of the selection transistor and the cell transistor. The gate stack of the select transistor includes a gate insulating film 260a and a gate conductive film 290a. The gate stack of the cell transistor includes a tunneling layer 230, a charge trap layer 240, a blocking layer 260b, and a control gate electrode. 290b.

Referring to FIG. 6, ion implantation is performed to increase the generation of hot holes in the select transistor. First, after removing the photoresist pattern for gate patterning, a photoresist pattern 310 exposing one side edge of the selection transistor is formed on the resultant. Phosphorus ions, for example, are implanted using the photoresist pattern 310 as a mask. At this time, considering the thickness of the polysilicon film 220 is injected with energy of about 5 to 25 KeV, the concentration is set to about 1 × 10 ¹⁷ ions / cm 3 ~ 1 × 10 ²¹ ions / cm 3 so as to produce hot holes. Next, an annealing process is performed to form an impurity layer 320 in the N-polysilicon film 220.

Referring to FIG. 7, the photoresist pattern used as the ion implantation mask is removed to form the charge trapping flash memory device of the present invention.

The charge trapping flash device of the present invention manufactured as described above is erased in a hot hole manner rather than a tunneling method by a general back bias. When a predetermined voltage is applied to the control gate WL of the memory cell and the gate of the selection transistor, and a constant voltage is applied to the source / drain of the selection transistor so that a constant bias is formed between the gate and the source / drain of the selection transistor. An inversion layer is formed by a negative bias applied to the gate 290a of the select transistor, and N-polysilicon by a positive bias applied to the source / drain 280. Hot-holes are generated as the electron-hole pairs (EHP) formed in the depletion region of the film 220 are broken. The generated hot holes move along the N-polysilicon film 220 and are erased by recombination with electrons trapped in the charge trap layer 240 of the memory cell.

According to the manufacturing method of the charge trapping flash memory device according to the present invention, the concentration is increased by performing ion implantation to increase the generation of hot holes in the semiconductor layer (polysilicon film) in the region where the channel of the selection transistor is to be formed. Let's do it. At this time, only about 1/2 of the channel region of the select transistor is implanted at a high concentration to increase the generation of hot holes while maintaining the on / off characteristics of the select transistor, thereby facilitating erasure by hot holes. In addition, since the number of memory cells can be increased by increasing the diffusion length of the generated hot holes, the degree of integration can be increased.

Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the technical spirit of the present invention. Do.

1 is a cross-sectional view illustrating an example of a flash memory device having a charge trap layer.

2 to 7 are cross-sectional views illustrating a method of manufacturing a charge trap type flash memory device according to the present invention.

Claims (16)

Board; An insulating film disposed on the substrate; A first conductive semiconductor layer disposed on the insulating film in the cell region; Select transistors and memory cells disposed on the semiconductor layer; And a first conductive type impurity layer disposed in the semiconductor layer below the selection transistor and having a higher concentration than that of the semiconductor layer. The method of claim 1, And the semiconductor layer is made of a polysilicon film doped with N-type impurities at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3. The method of claim 1, The selection transistor includes a gate insulating layer stacked on the semiconductor layer, and And a MOS transistor having a gate electrode disposed on the gate insulating film. The method of claim 1, And the memory cell includes a tunneling layer, a charge trap layer, a blocking layer, and a control gate electrode sequentially stacked on the semiconductor layer. The method of claim 1, The impurity layer is, And a half region of the channel from the outside of the selection transistor. The method of claim 5, And wherein the impurity layer is doped with N-type impurities at a concentration of 1 × 10 ¹⁷ ions / cm 3 to 1 × 10 ²¹ ions / cm 3. Sequentially forming a first insulating film and a semiconductor layer on the substrate; Forming a tunneling layer and a charge trap layer of a memory cell on the semiconductor layer; Forming a second insulating film on the resultant to be used as a gate insulating film of the selection transistor and a blocking layer of the memory cell; Forming an impurity layer for increasing hot hole generation in the semiconductor layer in the region where the channel of the selection transistor is to be formed; Forming a gate conductive film on the second insulating film; And Patterning the gate conductive layer, the second insulating layer, the charge trap layer, and the tunneling layer to form a gate stack of a selection transistor and a memory cell. The method of claim 7, wherein And the semiconductor layer is formed of a polysilicon film doped with an N-type impurity at a concentration of 1 × 10 ¹⁴ ions / cm 3 to 1 × 10 ¹⁸ ions / cm 3. The method of claim 7, wherein And the semiconductor layer is formed to a thickness of 100 to 600 GHz. The method of claim 7, wherein After forming a first insulating film and a semiconductor layer on the substrate, And forming a device isolation film defining a device isolation region in the semiconductor layer. The method of claim 10, Forming the device isolation film, Etching the semiconductor layer in the inactive region; Filling a region in which the semiconductor layer is etched with an insulating film, and Planarizing the insulating film to form an isolation layer. The method of claim 7, wherein In the step of forming the impurity layer, And dispersing the impurity layer from the outside of the selection transistor to a half region of the channel after diffusion of the impurity. The method of claim 7, wherein In the step of forming the impurity layer, N-type impurity ions of about 5 to 15 KeV energy, A method of manufacturing a flash memory device, comprising implanting at a concentration of 1 × 10 ¹⁷ ions / cm 3 to 1 × 10 ²¹ ions / cm 3. The method of claim 7, wherein And the gate conductive film is formed of a polysilicon film or a metal doped with a P-type dopant having a large work function. The method of claim 7, wherein And forming a gate stack of the selection transistor and the memory cell, and ion implanting impurities into the semiconductor layer at one edge of the selection transistor. The method of claim 15, In the step of implanting the impurity, Energy of about 5-25 KeV with N-type impurities, A method of manufacturing a flash memory device, comprising implanting at a concentration of 1 × 10 ¹⁷ ions / cm 3 to 1 × 10 ²¹ ions / cm 3.

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