JP2007081434A - Non-volatile semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fine flash memory with high integration, superior in element isolation capability, and with small parasitic resistors and capacitances. <P>SOLUTION: A NAND type flash EEPROM is formed on SOI substrate. An element region (active layer) has a lattice pattern, and a groove between the lattice patterns is embedded by an insulator. Elements of row direction are perfectly separated by the insulator. A silicon thin film in which memory cell is formed contains a minute amount of n-type impurity, and is located near an intrinsic semiconductor. A silicon thin film which is formed with a peripheral circuit and a selective gate transistor is p-type. A diffusion layer of memory cell and the selective gate transistor is n-type. A channel of each memory cell which constitutes NAND strings is configured at least two regions where threshold values are different. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to miniaturization and higher performance of a nonvolatile semiconductor memory device.

  EEPROM is a kind of nonvolatile semiconductor memory device that can electrically rewrite data, and its memory cell structure uses a MOS transistor having a stacked structure of a floating gate (charge storage layer) and a control gate. It has been known.

  15 and 16 show a memory cell structure of a FETMOS type EEPROM which is one of EEPROMs.

An element isolation insulating film 102 is formed in the element isolation region on the silicon substrate 101. A p ⁺ type diffusion layer 103 as a channel stopper is formed immediately below the element isolation insulating film 102. In the active region of the silicon substrate 101, a thin gate insulating film 104 through which a tunnel current can flow is formed. A floating gate (charge storage layer) 105 is formed on the gate insulating film 104, and a control gate 107 is formed on the floating gate 105 via an insulating film 106.

  Since the floating gate 105 and the control gate 107 are formed simultaneously with the same mask in the channel length direction, the edges in the channel length direction of both gates are aligned with each other. The source / drain diffusion layer 108 of the memory cell is formed in a self-aligned manner by ion implantation using the floating gate 105 and the control gate 107 as a mask.

  Conventionally, a field oxide film formed by thermally oxidizing a silicon substrate 101 is used for the element isolation insulating film 102. The LOCOS method is well known as a method for forming a field oxide film. In the LOCOS method, a silicon nitride film is used as a mask, and a thick silicon oxide film (element isolation insulating film) is formed in a region not covered with the silicon nitride film by thermal oxidation.

  However, when the element isolation insulating film (field oxide film) 102 is formed by the LOCOS method, a wedge-shaped portion called a bird's beak is formed in the element isolation insulating film 102. In this bird's beak, it is well known that the dimension of the element isolation insulating film 102 actually formed is larger than the dimension of the element isolation region in the design. Therefore, in general, the LOCOS method is not suitable for forming a fine element isolation region of 0.5 μm or less.

  Further, in the LOCOS method, the portion of the element isolation insulating film 102 that lies inside the surface of the silicon substrate 101 is only about the lower half of the element isolation insulating film 102, and therefore the element isolation capability is very poor. That is, even from this point, it can be said that it is very difficult to narrow the element separation interval by the LOCOS method.

  Further, in the case of the LOCOS method, a portion of the element isolation insulating film 102 that protrudes above the surface of the silicon substrate 101 causes a step on the silicon substrate 101. The step on the silicon substrate 101 reduces the processing margin of a pattern with a fine dimension in the photolithography process.

  As an element isolation technique for solving the above problems, a trench element isolation method (referred to as “Shallow Trench Isolation”) in which a trench groove is formed in a silicon substrate and this trench groove is filled with an insulating material is known.

  FIG. 17 shows a memory cell of a nonvolatile semiconductor memory device to which the trench element isolation method is applied.

  In the trench element isolation method, the actual dimensions are almost equal to the design dimensions compared with the LOCOS method, and the entire element isolation insulating film 102 is suitable for forming a fine element isolation region. Since the surface of the element isolation insulating film 102 is flat and substantially coincides with the surface of the silicon substrate 101, it does not cause a step on the silicon substrate 101. , And so on.

  Since the element isolation insulating film 102 of this example is formed in a self-aligned manner with the floating gate (charge storage layer) 105, the floating gate 105 has an overlap portion (“wing portion”) with the element isolation insulating film 102. Called) does not exist. Therefore, in the case of this example, the width of the element isolation insulating film 102 is determined only by the element isolation characteristics.

  However, even in the trench element isolation method, the element isolation capability is the distance between adjacent elements (memory cells), that is, the width of the element isolation insulating film 102 (the width of the trench) and the depth of the element isolation insulating film 102. Depends on (depth of trench). Therefore, if the width of the element isolation insulating film 102 is reduced for miniaturization, the depth of the element isolation film 102 must be increased in order to obtain sufficient element isolation capability. This means that the aspect ratio of the trench groove is increased, so that it is very difficult to realize a process such as etching when forming the trench groove and embedding an insulating material in the trench groove.

  On the other hand, from the standpoint of transistor performance, planar technology that forms a device by thermally oxidizing the surface of the silicon substrate to expose the substrate surface in the device region is extremely effective for increasing the scale and integration of integrated circuits. However, as the miniaturization and integration of semiconductor elements progress and the operation speed of the semiconductor elements increases, the influence of the parasitic capacitance between the metal wiring between the elements and the silicon substrate has become very large.

  The product of the voltage applied to the semiconductor element, the power consumed by the current flowing thereby, and the delay time of the semiconductor element becomes a constant value as a CR time constant composed of parasitic capacitance and parasitic resistance. Therefore, in order to realize high-speed operation while reducing power consumption, the parasitic CR must be reduced.

  Wiring resistance, contact resistance, element resistance, and the like that cause parasitic resistance are being greatly reduced by process improvements. On the other hand, the parasitic capacitance becomes extremely problematic as the distance between the elements becomes smaller. For example, the inter-wiring capacitance increases rapidly due to miniaturization, and therefore, interlayer filling with a low dielectric constant insulating material is required. However, as long as the elements are formed on the silicon substrate, the parasitic capacitance between the substrate and the wiring cannot be eliminated.

  From the viewpoint of further higher integration, it is necessary to three-dimensionally integrate semiconductor elements. If the semiconductor elements can be integrated in the vertical direction, the element density per unit area can be increased, so that the cost of the semiconductor integrated circuit can be reduced. However, since conventional semiconductor elements are formed on a silicon substrate except for some resistances and capacitors, three-dimensional integration cannot be performed.

As described above, in the conventional nonvolatile semiconductor memory device, it is very difficult to form an element isolation insulating film having sufficient element isolation characteristics due to element miniaturization and higher integration. In addition, parasitic resistance, parasitic capacitance, and the like increase, and it is desired to develop a technology that can easily reduce these.
JP-A-6-326277 JP-A-9-97851 JP-A-9-260617

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can be miniaturized and highly integrated, has excellent element isolation capability, and has reduced parasitic resistance and parasitic capacitance.

The nonvolatile semiconductor memory device of the present invention includes a memory cell transistor, and the memory cell transistor has a voltage Vg applied to a gate electrode and a cell current Id flowing at that time, the voltage Vg being higher than a reference voltage. A high positive voltage region and a negative voltage region where the voltage Vg is lower than the reference voltage, and the on-current in the positive voltage region and the negative voltage region is the voltage Vg There are at least ¹⁰⁴ times as compared to the off-state current flows when the reference voltage, the channel of the memory cell transistor is composed of at least two different regions of substantially the threshold, the at least two regions, It consists of two regions with a high threshold and two regions with a low threshold, and the region with a high threshold is sandwiched between two regions with a low threshold, The conductivity type of the diffusion layer constituting the drain and source of the memory cell transistor has the same polarity as the conductivity type of the substrate surface on which the memory cell transistor is formed.

  According to the example of the present invention, it is possible to realize a nonvolatile semiconductor memory device in which elements can be miniaturized and highly integrated, excellent in element isolation capability, and reduced in parasitic resistance and parasitic capacitance.

  Hereinafter, the nonvolatile semiconductor memory device of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows the layout of a NAND flash EEPROM according to the embodiment of the present invention. 2 is a cross-sectional view taken along line II-II in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III in FIG.

  An insulating layer 11 is formed on the silicon substrate 10, and a silicon thin film 12 is formed on the insulating layer 11. The insulating layer 11 is formed by thermally oxidizing the silicon substrate 10 or ion-implanting oxygen into the silicon substrate 10. The silicon thin film 12 is formed, for example, by single-crystallizing amorphous silicon or polycrystalline silicon. Thus, the technique for forming the silicon thin film 12 on the insulating layer 11 is called SOI (Silicon On Insulator).

  The silicon thin film 12 is formed in a lattice shape on the insulating layer 11 and used as an active layer. Between the lattice-like silicon thin films 12, an insulating material (silicon oxide film or the like) 13 is filled, and this insulating material 13 fulfills the function of element isolation. In this example, after the silicon thin film 12 is patterned in a lattice shape, elements adjacent in the row direction can be completely separated by filling the insulating material 13 between the lattice-like silicon thin films 12. For this reason, the width (element spacing) of the insulating material 13 in the row direction can be set to a minimum width determined in principle by a lithography technique or an etching technique.

  For example, a p-type impurity is introduced into the silicon thin film 12. An n-type source diffusion layer 18 -S is formed in a portion extending in the row direction of the lattice-like silicon thin film 12. A drain diffusion layer 18-D is formed between the source diffusion layer 18-S, which is a portion extending in the column direction of the lattice-like silicon thin film 12. Between the source diffusion layer 18-S and the drain diffusion layer 18-D, there are, for example, a NAND string composed of 16 memory cell transistors connected in series and two selection gate transistors arranged one by one at both ends thereof. Is formed.

  Each memory cell transistor includes an n-type diffusion layer 18, a floating gate electrode 15 as a charge storage layer formed on a channel region between the n-type diffusion layers 18 via a gate oxide film (tunnel oxide film) 14, The control gate electrode 17 is formed on the floating gate electrode 15 via an insulating film (ONO film or the like) 16.

  Each select gate transistor includes a gate oxide film 14A formed on a channel between the n-type diffusion layers 18, 18-S, 18-D and the n-type diffusion layers 18, 18-S, 18-D. It consists of electrodes SGS, SGD.

  Reference numeral 19 denotes a drain contact portion, and 20 denotes an interlayer insulating film. Further, a bit line is formed in the drain contact portion 19, and a source wiring is connected to the source diffusion layer 18-S through the source contact portion.

  The NAND flash EEPROM is characterized in that the memory cell array is formed on the silicon thin film 12 on the SOI substrate. In addition, the silicon thin film 12 has a lattice shape, and the lattice-shaped silicon thin film 12 is filled with an insulating material 13 having a function of element isolation. Therefore, elements adjacent in the row direction can be completely separated, and the width of the insulating material 13 in the row direction (element spacing) can be set to a minimum width determined by lithography or etching in principle (memory cell). It is no longer necessary to consider punch-through withstand voltage or field inversion withstand voltage).

  In addition, since the memory cell is formed on the insulating layer 11, the parasitic capacitance of the wiring such as the bit line becomes very small, and the performance of the memory can be improved. Further, since a thin film element such as a transistor is formed on the insulating layer 11, in the future, an insulating layer is further formed on the thin film element on the insulating layer, and a new silicon thin film on the insulating layer is newly formed. Three-dimensional integration in which thin film elements are formed is also possible.

  However, in the case of the above-described NAND flash EEPROM, each NAND string is completely separated by the insulating layer 11 constituting the SOI and the insulating material 13 for element isolation. That is, a well common to each NAND string cannot be formed in the silicon thin film 12.

  By the way, the threshold value of the memory cell can be changed by transferring charges between the floating gate electrode and the active region (channel). For example, when a positive high voltage is applied to the control gate electrode and 0 V is applied to the bit line and the source line, an inverted electron channel is formed in the active region of the memory cell. Electron injection is performed to increase the threshold value of the memory cell.

  In reading data, 0 V is applied to the control gate electrode of the selected memory cell, and it is determined whether the threshold voltage of the memory cell is higher or lower than 0 V depending on whether or not a current flows through the memory cell. That is, when the threshold value is higher than 0V, the channel does not flow because the memory cell is not turned on. On the other hand, if the threshold value is lower than 0V, the memory cell is turned on, so that a channel current flows. At this time, a positive potential that turns on the memory cell regardless of the data value is applied to the control gate electrode of the non-selected memory cell so that the channel current flows even when the threshold value is high.

  However, a NAND flash EEPROM using an SOI substrate performing such an operation has a problem that it is very difficult to draw electrons from the floating gate electrode to the active region to make the threshold value 0 V or less. .

  That is, when a negative high voltage is applied to the control gate electrode and 0 V is applied to the bit line and the source line, holes are accumulated on the surface of the active region of the memory cell, but a PN junction composed of the active region and the diffusion layer is formed. Since the flow of holes into and out of the diffusion layer is blocked, the potential of the bit line and the source line cannot be transferred to the active region of the memory cell.

  In other words, when a negative high voltage is applied to the word lines WL0 to WL15 of all the memory cell transistors constituting the NAND string, in the memory cell to which the potentials of the bit line and the source line are not transferred, the active region in the floating state has A negative potential is generated due to capacitive coupling with the control gate electrode, and a high electric field is not applied between the floating gate electrode and the active region, so that electrons cannot be extracted from the floating gate electrode.

  Accordingly, in the NAND flash EEPROM using the SOI substrate as shown in FIGS. 1 to 3, the bit line or the source line is connected to the memory cell transistor on the bit line side or the source line side from the memory cell transistor to be erased. It is necessary to sequentially erase data for each memory cell transistor in the NAND string by applying an applied potential, for example, a positive voltage capable of transferring 0 V, and from the floating gate electrodes of all the memory cell transistors in the NAND string. There is a problem that block erasure cannot be performed by pulling out electrons.

  The embodiment described below relates to a NAND flash EEPROM that solves such a problem.

  FIG. 4 shows a layout of a NAND flash EEPROM according to the embodiment of the present invention. 5 is a cross-sectional view taken along the line VV in FIG. 4, and FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG.

  An insulating layer 11 is formed on the silicon substrate 10, and a silicon thin film 12 is formed on the insulating layer 11. The insulating layer 11 is formed by thermally oxidizing the silicon substrate 10 or ion-implanting oxygen into the silicon substrate 10. The silicon thin film 12 is formed, for example, by single-crystallizing amorphous silicon or polycrystalline silicon. Thus, the technique for forming the silicon thin film 12 on the insulating layer 11 is called SOI (Silicon On Insulator).

  The silicon thin film 12 is formed in a lattice shape on the insulating layer 11 and used as an active layer. Between the lattice-like silicon thin films 12, an insulating material (silicon oxide film or the like) 13 is filled, and this insulating material 13 fulfills the function of element isolation. In this example, after the silicon thin film 12 is patterned in a lattice shape, elements adjacent in the row direction can be completely separated by filling the insulating material 13 between the lattice-like silicon thin films 12. For this reason, the width (element spacing) of the insulating material 13 in the row direction can be set to a minimum width determined in principle by a lithography technique or an etching technique.

A p-type impurity is introduced into a portion of the silicon thin film 12 where the selection gate transistor is formed. Further, a small amount of n-type impurity (high resistance and close to an intrinsic semiconductor) is introduced into a portion of the silicon thin film 12 where NAND strings (16 memory cell transistors connected in series) are formed. ing. The active layer in the portion where the memory cell is formed is set so that, for example, the impurity concentration is 1 × 10 ¹² cm ⁻³ or less and the resistivity is 1 × 10 ⁵ Ωcm or more.

  An n-type source diffusion layer 18 -S is formed in a portion of the silicon thin film 12 that extends in the row direction. A drain diffusion layer 18-D is formed between the source diffusion layer 18-S, which is a portion extending in the column direction of the lattice-like silicon thin film 12. Between the source diffusion layer 18-S and the drain diffusion layer 18-D, there are, for example, a NAND string composed of 16 memory cell transistors connected in series and two selection gate transistors arranged one by one at both ends thereof. Is formed.

  Each memory cell transistor includes an n-type diffusion layer 18, a floating gate electrode 15 as a charge storage layer formed on a channel region between the n-type diffusion layers 18 via a gate oxide film (tunnel oxide film) 14, The control gate electrode 17 is formed on the floating gate electrode 15 via an insulating film (ONO film or the like) 16.

  Each select gate transistor includes a gate oxide film 14A formed on a channel between the n-type diffusion layers 18, 18-S, 18-D and the n-type diffusion layers 18, 18-S, 18-D. It consists of electrodes SGS, SGD.

  Reference numeral 19 denotes a drain contact portion, and 20 denotes an interlayer insulating film. Further, a bit line is formed in the drain contact portion 19, and a source wiring is connected to the source diffusion layer 18-S through the source contact portion.

  FIG. 7 shows a potential relationship at the time of erasing (Erase), writing (Write), and reading (Read) of the NAND type flash EEPROM of FIGS.

  In block-to-block erase, the bit lines BL1, BL2,... And the source line SL in the block are set to a low potential (for example, a reference potential of 0 V), and an intermediate voltage is set so that the gate electrodes SGD, SGS of the select gate transistors are turned on. (For example, 4V) is applied. A negative high voltage (for example, −18 V) is applied to all the word lines WL0 to WL15 of the memory cells. At this time, a high electric field is applied between the active region (channel) and the floating gate electrode (charge storage layer), and electrons move from the charge storage layer to the active region through the gate oxide film. As a result, the threshold value of the memory cell in the block becomes lower than a reference potential (for example, 0 V).

  In selective writing, 0 V is applied to the selected bit line BL1, and a write inhibit voltage (for example, 8 V) is applied to the non-selected bit line BL2. A positive high voltage (for example, 18V) is applied to the selected word line WL1, and a write inhibit voltage is applied to the non-selected word lines WL0, WL2 to WL15 other than the selected word line WL1 and the gate electrode SGD of the drain-side selected gate transistor. A voltage for transfer (for example, 10 V) is applied. This voltage is higher than the write inhibit voltage by the threshold value of the memory cell transistor and the select gate transistor.

  A low voltage (for example, 0 V) is applied to the gate electrode SGS of the selection gate transistor on the source side to turn it off, and a current penetrating from the bit lines BL1, BL2,... To the source line SL is cut off. As a result, a high electric field is applied between the active region under the selected word line WL1 and the floating gate electrode (charge storage layer), so that electrons are injected from the active region into the floating gate electrode through the gate oxide film. As a result, the threshold value of the selected memory cell becomes higher than the reference potential.

  In reading, for example, 1V is applied to the selected bit line BL1, and 0V is applied to the non-selected bit line BL2, for example. A low voltage (for example, 0V) is applied to the selected word line WL1, and an intermediate potential (for example, 4V) is applied to the non-selected word lines WL0, WL2 to WL15 other than the selected word line WL1 and the gate electrodes SGD, SGS of the selected gate transistors. Apply to turn on. At this time, if the selected cell is in the erased state, current flows, and if the selected cell is in the written state, no current flows, so that the threshold value of the memory cell can be determined.

  In the NAND flash EEPROM formed on the SOI substrate, in order to perform the above-described batch erase, selective write and read, the following two points must be satisfied.

  The first point is that at the time of batch erase, all the memory cell transistors must be turned on and the low potential (0 V) of the bit line and / or source line must be transferred to all the memory cells to be erased. It is not to be. However, a normal memory cell is cut off below the threshold value. For this reason, when a negative high voltage is applied to the control gate electrode of the memory cell, the low potential (0 V) of the bit line and / or the source line cannot be transferred to all memory cells to be erased.

  The second point is that when the selected memory cell is in a writing state at the time of reading, the memory cell must be surely cut off at a low potential (0 V) applied to the control gate electrode. However, when a current flows through the memory cell due to a leak current or the like, the sense amplifier recognizes that the selected memory cell is in an erased state.

  FIG. 8 shows an ideal characteristic of the current-voltage characteristic of the memory cell that satisfies the above two conditions.

  As shown in FIG. 8A, the memory cell transistor has a source / source voltage when a positive voltage equal to or higher than the threshold value is applied and when a negative high voltage as applied during erasing is applied. A current flows between the drains, and a gate voltage lower than the threshold value by a difference (about 4 V) between a threshold value at the time of writing and a voltage (about 0 V) applied at the time of reading is cut off and no current flows. Something like that must be used.

  However, in the NAND cell array, the operation in which the potential difference is generated between the source and drain of the memory cell is only at the time of reading, and the applied voltage is very low, for example, 3 V or less. In addition, an on / off ratio between an off-state current that can be recognized by a sense amplifier as a write state with respect to a cell current flowing between the source and drain, for example, several μA, by applying a gate voltage of 0 V to an erased memory cell Is 4 digits or more.

Therefore, it is sufficient to set the on / off ratio of the memory cell transistor to four digits or more under the above two conditions. In other words, in order to transfer the voltage of the bit line at the time of data writing with respect to the cell current at the reference voltage (for example, 0V), a positive voltage region (in FIG. 8B) applied to the unselected word line. cell current in the region of the first region) and a negative voltage applied to the control gate electrode during data erase second region in (FIG. 8 (b)) may be set at about 10 ⁴ times or more.

  On the other hand, the selection gate transistor must transfer the bit line potential at the time of erasing, writing, and reading, and at the time of writing, the selection gate transistor on the source side has a low voltage (0 V) at the gate. Must be cut off when is applied. In particular, the cutoff state must be sufficiently reduced to 1 pA or less in order to eliminate the through current flowing from the bit line to the source line and reduce the power consumption in the booster circuit.

  FIG. 9 shows a cell transistor structure having memory cell characteristics that satisfy the above conditions.

An insulating layer (silicon oxide or the like) 11 is formed on the silicon substrate 10, and a silicon thin film (active region) 12 is formed on the insulating layer 11. It is assumed that the silicon thin film 12 includes an n-type impurity having an n-type low impurity density state close to that of an intrinsic semiconductor, for example, 1 × 10 ¹² cm ⁻³ or less. The resistivity of the silicon thin film (active region) 12 is very high resistance of 1 × 10 ⁵ Ωcm or more.

  FIG. 10 shows current-voltage characteristics in the write state of the memory cell transistor of FIG.

When a positive voltage is applied to the gate, 0 V to the source, and positive voltage to the drain, electrons are supplied from the n ⁺ diffusion layer 18 to form a storage electron layer at the active region interface. Accordingly, an electron current flows between the source and drain of the memory cell. Actually, an electron current flows even below the threshold due to diffusion.

On the other hand, when a negative voltage is applied to the gate, 0 V to the source, and positive voltage to the drain, the electrons in the electron-hole pair generated by thermal energy flow out to the drain and holes accumulate at the gate interface. Holes flow out to the source side by the source-drain electric field. Unlike the pn junction, the n ⁺ -n ⁻ junction between the n ⁺ diffusion layer 18 and the n ⁻ silicon thin film (active region) 12 has a very small blocking effect on holes. Therefore, holes are supplied from the drain side so as to compensate for the holes flowing out to the source side, and a hole current flows. In the state where the electron current and the hole current are the smallest, the drain current shows the minimum value. However, this value varies depending on the drain voltage.

  In the memory cell transistor of FIG. 10, when a negative high voltage is applied to the gate, the potential of the bit line can be transferred by the hole current, so that block erasure can be realized. However, since the off state occurs only in a very narrow gate voltage region, when the memory cell is in the write state, a hole current flows at a gate voltage of 0 V, and cannot be cut off at the time of reading. Remains.

  FIG. 11 shows a cell transistor structure that solves the above problem.

  An active region (channel) between the source and drain of the memory cell transistor is formed of at least two regions having different threshold voltages. Further, the active region having the lowest threshold is arranged on the drain side, and the active region having the highest threshold is arranged on the source side. In this example, a cell transistor configured by an active region having two threshold values (VthL, VthH) is shown.

  In order to consider the electrical characteristics of the cell transistor, FIG. 12 shows a simple equivalent circuit of the cell transistor of FIG. FIG. 13 shows current-voltage characteristics in the write state of the cell transistor of FIG.

  Consider a case where transistors having two different thresholds are connected in series, and 0 V is applied to the source, 4 V is applied to the drain, and Vg is applied to the gate. The drain and source of the two transistors are short-circuited to an intermediate potential VM. As for the transistor characteristics of VthH, when the VM potential is changed from 1V to 4V, the electron current in the subthreshold region hardly changes. However, the hole current has a characteristic of horizontally moving to the positive side by the increase of the VM potential.

  On the other hand, as for the transistor characteristics of VthL, when the VM potential is changed from 0V to 3V, the hole current in the subthreshold region is hardly changed. However, the electron current has a characteristic of horizontally moving to the positive side by the increase of the VM potential. The intersection of both characteristics having the same VM potential indicates the actual transistor characteristics.

  In the transistor characteristics shown in FIG. 13, by connecting two transistors having different threshold values in series, the gate voltage range in the off state is wider than the difference between VthH and VthL, which is more than that of a single transistor. It can be seen that the gate voltage range in the off state can be expanded.

  At this time, the gate voltage range in the off state is a range that reaches at least the read voltage 0 V applied to the gate electrode of the transistor at the time of data reading in a region below the threshold value (Vthw) when the memory cell is in the write state. It is clear from FIG.

  Accordingly, the difference between the highest threshold value and the lowest threshold value in regions having different threshold values is the difference between the maximum threshold value of the written cell and the potential applied to the selected word line at the time of reading (for example, 0 V ) In other words, in the case of a NAND flash EEPROM, the potential applied to the control gate electrode of the selected memory cell in the NAND string and the potential applied to the other control gate electrodes If the potential difference is set to be greater than or equal to the potential difference, it can be turned off when 0 V is applied to the gate during reading.

  Further, in the memory cell transistor in the erased state, the current-voltage characteristic shown in FIG. 13 becomes a characteristic that is horizontally shifted to the negative side as it is, and therefore 0 V higher than the threshold voltage is applied to the control gate electrode at the time of reading. Will turn on.

  Since the off state of the cell transistor shown in this embodiment is obtained by the resistance value of the active region (channel), unlike hole blocking by the pn junction, the resistivity of the active region needs to be as high as possible. There is. If the cell current at the time of reading is about several μA, in order to obtain an on / off ratio of about four digits, the off current must be several tens of nA or less.

In addition, when the active region thickness is about 100 nm and 1 V is applied to the drain, the resistivity is required to be about 1 × 10 ⁵ Ωcm. In the case of n-type silicon, this is a case where the impurity density is 1 × 10 ¹² cm ⁻³ or less.

  In the present embodiment, the active region between the source and drain of the cell transistor is configured with two regions having different threshold voltages. However, the active region between the source and drain of the cell transistor has a threshold voltage of You may comprise in three or more different area | regions. As an example, FIG. 14 shows a case where the active region is composed of three regions having different threshold voltages.

  In this case, it is not necessary to fix one of the two diffusion layers 18 as a source and the other as a drain, and either diffusion layer 18 can be used as a source or a drain. That is, a MOS transistor capable of flowing a current in both directions can be provided.

  As described above, the potential difference applied between the source and drain of the memory cell is about the bit line potential (for example, 1 V) at the time of reading, but about 8 V is applied to the select gate transistor. In addition, the select gate transistor is required to have a very small leakage current in order to suppress a through current between the bit line and the source line at the time of writing. Therefore, it cannot be used in the current-voltage characteristics of the memory cell as shown in this embodiment.

  In the embodiment shown in FIGS. 4 to 6, the active region (substrate surface) where the select gate transistor is formed is p-type as in the conventional bulk silicon transistor, and the n-type diffusion layer and p-type active region are formed. In this structure, the hole current is blocked by a pn junction formed by the above. On the other hand, the active region (substrate surface) where the memory cell is formed is n-type, and the diffusion layer is also n-type. In other words, the active region of the select gate transistor and the active region of the memory cell are opposite in polarity, the active region of the select gate transistor is opposite in polarity to its diffusion layer, and the active region of the memory cell is the same as its diffusion layer. Polarity.

  Note that a peripheral circuit (MOS transistor) for driving the memory cell can also be formed on the SOI region. An n-channel MOS transistor used in a CMOS circuit uses a p-type active region and an n-type diffusion layer, similarly to a select gate transistor, and an n-type active region and p-type diffusion layer in a p-channel MOS transistor used in a CMOS circuit. May be used.

  Further, it is possible to select a threshold value according to a desired set value, and the memory cell can be formed on a bonded SOI substrate, a SIMOX substrate, or an insulating substrate. You may form in the epitaxial layer by solid layer growth. The material of the active region is not limited to single crystal silicon, but may be polycrystalline silicon or amorphous silicon, or may be other than a silicon-based material.

  Further, the insulating material may be three-dimensionally integrated using an interlayer insulating film. Alternatively, it may be formed on a transparent insulating substrate such as a glass substrate and formed on-chip with a display device or the like.

  As shown in FIG. 11, as a method of forming two regions having different threshold values in the active region, for example, a method of partially changing the channel ion implantation amount, or a method of partially changing the gate insulating film thickness. Although the method of changing etc. can be considered, it is not limited to this.

  An example of a method for manufacturing the NAND flash EEPROM shown in FIGS. 4 to 6 will be described below.

  First, a low impurity concentration silicon film which becomes an active layer is formed on an insulating material (for example, an insulating layer on a silicon substrate) to form an SOI substrate. Note that the insulating material of the SOI substrate can be formed, for example, by thermally oxidizing the surface of the silicon substrate or by depositing an insulating film such as a silicon dioxide film or a silicon nitride film on the silicon substrate. In addition to the above, the SOI substrate itself may be a bonding method, a SIMOX substrate, or the like.

  Next, phosphorus (P) or boron (in the region where the impurity concentration of the silicon film on the insulating material is to be increased, for example, the region where the peripheral circuit (MOS transistor) is formed or the region where the select gate transistor is formed. Impurities such as B) are ion-implanted by a desired dose.

  In order to form at least two regions having different threshold values in the channel region of the memory cell, for example, at least two ion implantations are performed, and at least two regions having different impurity concentrations are formed in the channel region of the memory cell. Form.

  Subsequently, a mask having a lattice pattern is formed on the silicon film by using a lithography technique. In this lattice pattern, there is no problem even if the pitch of a plurality of line patterns extending in the column direction is reduced to the limit of lithography. Then, using this lattice pattern mask, the silicon film on the insulating material is etched to form a lattice-like active layer.

  Next, using an insulating material such as a TEOS film or a silicon nitride film, the trench between the active layers is filled, and using CMP or RIE, the surface of the insulating material is flattened to complete element isolation. Let

  A gate oxide film (tunnel oxide film) is formed on the surface of the active layer by thermal oxidation, and a conductor to be a floating gate electrode is formed on the gate oxide film by LPCVD. After forming a slit-like groove in the conductor to be a floating gate electrode, an insulating film such as an ONO (Silicon oxide-Silicon nitride-Silicon oxide) film is formed on this conductor, and further, an insulating film is formed by LPCVD. A conductor to be a control gate electrode is formed thereon.

  Next, a line pattern mask extending in the row direction is formed by a lithography process. Then, using this line pattern mask, each conductor is etched to form a control gate electrode and a floating gate electrode. Further, using these gates as masks, impurities (for example, phosphorus, arsenic, etc.) having the same polarity as the silicon film are ion-implanted into the silicon film (active layer) to form source / drain diffusion layers.

  A memory cell is formed by the above process. After this, normal processes such as interlayer film formation and wiring formation are performed.

  The present invention is not limited to the embodiments described above. For example, the block flash erase for the NAND flash EEPROM shown in FIGS. 4 to 6 is not performed, and data may be erased sequentially for each memory cell in the NAND string. That is, the present invention can be implemented with various modifications without departing from the scope of the invention.

  The effects of the present invention are as follows.

  First, a NAND flash EEPROM is formed on an SOI substrate, and an element region (active layer) has a lattice pattern, and a groove between the element regions is embedded with an insulating material. That is, the elements in the row direction are completely separated from each other by an insulating material, and the distance between lines extending in the column direction (elements in the row direction) can be set to a minimum width that can be achieved in the lithography process. As a result, it is possible to provide a NAND flash EEPROM in which elements can be miniaturized and highly integrated, have excellent element isolation capability, and have reduced parasitic resistance and parasitic capacitance.

  Secondly, as described above, when a NAND flash EEPROM is formed on an SOI substrate, it is desired to enable collective block erasure that simultaneously erases data in memory cells in a block. Therefore, the channel of each memory cell constituting the NAND string is composed of at least two regions having different threshold values. This makes it possible to realize collective block erasing, which is a feature of the flash EEPROM, while taking advantage of the first effect (feature by SOI).

  The second effect is not limited to the SOI structure or the NAND flash EEPROM. That is, for example, it is meaningful to develop a novel MIS transistor having the characteristics shown in FIG.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying each component without departing from the scope of the invention. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a plan view of a nonvolatile semiconductor memory device according to an embodiment of the present invention. Sectional drawing which follows the II-II line | wire of FIG. Sectional drawing which follows the III-III line of FIG. 1 is a plan view of a nonvolatile semiconductor memory device according to an embodiment of the present invention. Sectional drawing which follows the VV line | wire of FIG. Sectional drawing which follows the VI-VI line of FIG. FIG. 6 is a diagram showing a voltage relationship in each mode of the nonvolatile semiconductor memory device of the present invention. FIG. 6 shows current-voltage characteristics of the nonvolatile semiconductor memory device of the present invention. FIG. 7 is a cross-sectional view illustrating the structure of the memory cell transistor of FIGS. FIG. 10 is a diagram showing current-voltage characteristics of the memory cell transistor of FIG. 9. FIG. 3 is a cross-sectional view illustrating a structure of a memory cell transistor of the present invention. FIG. 12 shows an equivalent circuit of the memory cell transistor of FIG. 11. FIG. 12 is a diagram showing current-voltage characteristics of the memory cell transistor of FIG. 11. FIG. 12 is a cross-sectional view showing a modification of the memory cell transistor of FIG. 11. Sectional drawing which shows the memory cell of the conventional non-volatile semiconductor memory device. Sectional drawing which shows the memory cell of the conventional non-volatile semiconductor memory device. The figure which shows the conventional non-volatile semiconductor memory device by the self-alignment trench element isolation | separation.

Explanation of symbols

10, 101: Silicon substrate,
11: Insulating layer,
12: Silicon thin film,
13: Insulating material,
14, 104: Gate oxide film,
15, 105: floating gate electrode,
16, 106: Insulating film,
17, 107: control gate electrode,
18, 108: diffusion layer,
18-S: source diffusion layer,
18-D: drain diffusion layer,
19: drain contact portion,
20: Interlayer insulating film,
102: Field oxide film,
103: Channel stopper.

Claims (7)

Comprising a memory cell transistor;
The memory cell transistor is
In the relationship between the voltage Vg applied to the gate electrode and the cell current Id flowing at that time, the positive voltage region where the voltage Vg is higher than the reference voltage and the negative voltage region where the voltage Vg is lower than the reference voltage It has the door, on-current in the region of the area and the negative voltage of the positive voltage, the voltage Vg is not less than by 10 ⁴ times the off-state current flows when the reference voltage,
The channel of the memory cell transistor is
Consisting of at least two regions with substantially different thresholds,
The at least two regions are:
It is composed of a high threshold region and two low threshold regions, and the high threshold region is sandwiched between the two low threshold regions,
The conductivity type of the diffusion layer constituting the drain and source of the memory cell transistor is
A non-volatile semiconductor memory device having the same polarity as the conductivity type of the substrate surface on which the memory cell transistor is formed.   A plurality of the memory cell transistors are connected in series to form a NAND string, and the potential difference between the highest threshold value and the lowest threshold value in the at least two regions is selected among the NAND strings at the time of data reading. 2. The nonvolatile semiconductor memory device according to claim 1, wherein a potential difference between a potential applied to the gate electrode of the memory cell transistor and a potential applied to the gate electrode of the other memory cell transistor is larger.   2. The nonvolatile memory according to claim 1, wherein when the memory cell transistor is in a write state, the reference voltage is equal to a read voltage applied to a gate electrode of the memory cell transistor selected at the time of data reading. Semiconductor memory device.   A predetermined voltage in the first region is applied to the gate electrode of the memory cell transistor at the time of data writing, and a predetermined voltage in the second region is applied to the gate electrode of the memory cell transistor at the time of data erasing. The nonvolatile semiconductor memory device according to claim 1. The nonvolatile semiconductor memory device according to claim 4, wherein an impurity concentration of a substrate surface on which the memory cell transistor is formed is 1 × 10 ¹² cm ⁻³ or less.   6. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell transistor includes a charge storage layer that exchanges charges with a channel of the memory cell transistor. 7.   7. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell transistor is formed in an active layer on an insulating layer.

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