CN115881798A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 73
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 206
- 238000000034 method Methods 0.000 claims abstract description 51
- 230000002093 peripheral effect Effects 0.000 claims abstract description 51
- 238000003860 storage Methods 0.000 claims abstract description 51
- 230000015654 memory Effects 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims description 311
- 239000011229 interlayer Substances 0.000 claims description 68
- 239000004020 conductor Substances 0.000 claims description 43
- 239000003989 dielectric material Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000003384 imaging method Methods 0.000 claims 1
- 230000002349 favourable effect Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000009286 beneficial effect Effects 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
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Abstract
The present disclosure relates to a semiconductor structure and a method of fabricating the same. The semiconductor structure includes: a substrate, a memory cell, and peripheral circuitry. The substrate is provided with an array area and a peripheral area positioned on at least one side of the array area. The memory cell is located in the array region and comprises: a first gate structure and a storage gate structure. The storage gate structure includes: a floating gate and a control gate are arranged in a stack. The peripheral circuit is positioned in the peripheral area and comprises a second grid structure. The surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are located on the same plane. The total heights of the gate structures in the array region and the peripheral region are the same. Therefore, the semiconductor structure and the preparation method thereof can reduce the preparation process flow of the semiconductor structure so as to improve the production efficiency and the production yield, are favorable for increasing the preparation process window and improve the process stability of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
With the continuous development of semiconductor technology, nonvolatile memories are widely used in various embedded systems to store data when the system is powered off.
Currently, the mainstream nonvolatile memory includes flash memory. Flash memories are increasingly developed and applied due to the characteristics of high writing speed, high integration and the like. In development and application of flash memory, it is a research focus of flash memory to reduce the manufacturing process of the device and improve the stability of the device.
Therefore, how to reduce the manufacturing process flow of the memory is a problem to be solved.
Disclosure of Invention
Accordingly, there is a need for a semiconductor structure and a method for fabricating the same, which effectively reduces the process flow of the memory to improve the production efficiency and yield, and is beneficial to increase the process window to improve the process stability of the device.
In one aspect, some embodiments of the present disclosure provide a semiconductor structure, including: the array structure comprises a substrate, a first substrate and a second substrate, wherein the substrate is provided with an array area and a peripheral area positioned on at least one side of the array area; the memory cell, lie in the array region, include: the first plane transistor and the storage transistor are connected; the first planar transistor comprises a first gate structure; the storage transistor includes a storage gate structure; the storage gate structure includes: a floating gate and a control gate arranged in a stacked manner; the peripheral circuit is positioned in the peripheral area and comprises a second planar transistor; the second planar transistor comprises a second gate structure; the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are located on the same plane.
In the semiconductor structure, the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are located on the same plane, that is, the total heights of the gate structures located in the array region and the peripheral region are the same. Therefore, in the semiconductor structure, the grid structures positioned in the array area and the peripheral area are beneficial to being synchronously formed by adopting the same process, so that the preparation process flow of the semiconductor structure is reduced, and the production efficiency and the production yield are improved. And in addition, the preparation process window is favorably enlarged so as to improve the process stability of the device.
In some embodiments of the present disclosure, the first gate structure includes: the first gate dielectric layer is arranged on one side of the substrate; the first grid electrode is arranged on the surface of the first grid dielectric layer, which is deviated from the substrate; the first contact layer is arranged on the surface of the first grid electrode, which is deviated from the first grid dielectric layer; and the first side wall is arranged on the side walls of the first grid electrode and the first contact layer and is positioned on the surface of the first grid dielectric layer deviating from the substrate.
In some embodiments of the present disclosure, the second gate structure includes: the second gate dielectric layer is arranged on one side of the substrate; the second grid electrode is arranged on the surface of the second grid dielectric layer, which is deviated from the substrate; the second contact layer is arranged on the surface, away from the second gate dielectric layer, of the second gate electrode; and the second side wall is arranged on the side walls of the second grid electrode and the second contact layer and is positioned on the surface of the second grid dielectric layer deviating from the substrate.
In some embodiments of the present disclosure, the control gate is located on a side of the floating gate facing away from the substrate; the storage gate structure further includes: the interlayer dielectric layer is positioned between the floating grid and the control grid; the orthographic projections of the floating grid, the interlayer dielectric layer and the control grid on the substrate are superposed. Therefore, the floating gate, the interlayer dielectric layer and the control gate can be formed by patterning through a one-time composition process, the use of masks is reduced, and cost saving is facilitated.
In some embodiments of the present disclosure, the storage gate structure further comprises: the third gate dielectric layer is arranged between the substrate and the floating gate; the third contact layer is arranged on the surface of the control grid electrode, which is deviated from the interlayer dielectric layer; and the third side wall is arranged on the side walls of the floating grid electrode, the interlayer dielectric layer, the control grid electrode and the third contact layer and is positioned on the surface of the third grid dielectric layer, which deviates from the substrate.
The semiconductor structure is characterized in that the gate structures in the array area and the peripheral area are formed synchronously by the same process, and the first contact layer, the third contact layer and the second contact layer in the array area and the peripheral area can be formed synchronously by the same process. Therefore, the preparation process flow of the semiconductor structure can be further reduced, so that the production efficiency and the production yield are improved. And in addition, the preparation process window is favorably enlarged so as to improve the process stability of the device.
In another aspect, some embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate is provided with an array area and a peripheral area positioned on at least one side of the array area; respectively forming a first gate structure and a storage gate structure on the part of the substrate located in the array region, and forming a second gate structure on the part of the substrate located in the peripheral region; the storage grid structure comprises a floating grid and a control grid which are arranged in a stacked mode; the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are located on the same plane.
In the preparation method of the semiconductor structure, the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are positioned on the same plane, namely, the total height of the gate structure formed on the array region of the substrate is the same as that of the gate structure formed on the peripheral region of the substrate. Therefore, in the semiconductor structure, the grid structures formed on the substrate in the array area and the substrate in the peripheral area are beneficial to being synchronously formed by adopting the same process, so that the preparation process flow of the semiconductor structure is reduced, and the production efficiency and the production yield are improved. And in addition, the method is also beneficial to enlarging the preparation process window so as to improve the process stability of the device.
In some embodiments of the present disclosure, the control gate is located on a side of the floating gate facing away from the substrate; the storage gate structure further includes: an interlayer dielectric layer between the floating gate and the control gate; forming a first gate structure and a storage gate structure on a portion of the substrate in the array region, respectively, and forming a second gate structure on a portion of the substrate in the peripheral region, including: sequentially forming a first conductive material layer and an interlayer dielectric material layer on one side of a substrate; patterning the interlayer dielectric material layer to form an initial interlayer dielectric layer; forming a second conductive material layer, wherein the second conductive material layer covers the initial interlayer dielectric layer and the surface of the first conductive material layer which is not covered by the initial interlayer dielectric layer; and patterning the second conductive material layer, the initial interlayer dielectric layer and the first conductive material layer to form a first grid electrode of the first grid structure and a floating grid electrode, an interlayer dielectric layer and a control grid electrode of the storage grid structure on the part of the substrate positioned in the array area respectively, and form a second grid electrode of the second grid structure on the part of the substrate positioned in the peripheral area.
In the preparation method of the semiconductor structure, the second conductive material layer, the initial interlayer dielectric layer and the first conductive material layer are patterned so as to form the first grid electrode, the floating grid electrode, the interlayer dielectric layer and the control grid electrode on the part of the substrate, which is positioned in the array area, respectively, and form the second grid electrode on the part of the substrate, which is positioned in the peripheral area. Therefore, the first grid electrode, the floating grid electrode, the interlayer dielectric layer, the control grid electrode and the second grid electrode can be formed in a patterning mode through a one-time composition process, the use of masks is reduced, and cost saving is facilitated.
In some embodiments of the present disclosure, forming an interlayer dielectric material layer on a substrate includes: and sequentially forming a first oxide material layer, a nitride material layer and a second oxide material layer on the surface of the first conductive material layer, which is far away from the substrate.
In some embodiments of the present disclosure, forming a first gate structure and a storage gate structure on a portion of the substrate in the array region, and forming a second gate structure on a portion of the substrate in the peripheral region respectively, further includes: forming a first contact layer on the surface of the first grid electrode, which is far away from the substrate, and forming a first side wall on the side wall of the first grid electrode and the first contact layer; forming a second contact layer on the surface of the second grid electrode, which is far away from the substrate, and forming a second side wall on the side wall of the second grid electrode and the second contact layer; and forming a third contact layer on the surface of the control grid electrode, which is deviated from the interlayer dielectric layer, and forming a third side wall on the side walls of the floating grid electrode, the interlayer dielectric layer, the control grid electrode and the third contact layer.
In some embodiments of the present disclosure, before forming the first conductive material layer on the substrate side, the method further includes: forming a gate dielectric material layer on the surface of the substrate; the first conductive material layer is also formed on the surface of the gate dielectric material layer, which is far away from the substrate; before the first side wall, the second side wall and the third side wall are formed, the preparation method further comprises the following steps: patterning the gate dielectric material layer to form a first gate dielectric layer between the substrate and the first gate, a second gate dielectric layer between the substrate and the second gate, and a third gate dielectric layer between the substrate and the floating gate; the first side wall is further formed on the surface, away from the substrate, of the first gate dielectric layer, the second side wall is further formed on the surface, away from the substrate, of the second gate dielectric layer, and the third side wall is further formed on the surface, away from the substrate, of the third gate dielectric layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required to be used in the description of the embodiments are briefly introduced below, and it is apparent that the drawings in the description below are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings may be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present application;
fig. 2 (a) is a schematic cross-sectional view illustrating a first gate structure in a semiconductor structure according to an embodiment of the present application; fig. 2 (b) is a schematic cross-sectional view illustrating a second gate structure in a semiconductor structure according to an embodiment of the present application; fig. 2 (c) is a schematic cross-sectional view illustrating a memory gate structure in a semiconductor structure according to an embodiment of the present application;
FIG. 3 is a flow chart of a method of fabricating a semiconductor structure provided in an embodiment of the present application;
fig. 4 is a schematic cross-sectional structure diagram of a structure obtained after step S10 in the method for manufacturing a semiconductor structure provided in an embodiment of the present application;
FIG. 5 is a flow chart illustrating the formation of a first gate structure, a memory gate structure, and a second gate structure in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 6 is a schematic cross-sectional structure diagram of a structure obtained after step S21 in a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 7 is a schematic cross-sectional view of a structure obtained after step S22 in a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 8 is a schematic cross-sectional view illustrating a structure obtained after step S23 in a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 9 is a schematic cross-sectional structure diagram of a structure obtained after step S24 in a method for fabricating a semiconductor structure provided in an embodiment of the present application;
fig. 10 is a schematic cross-sectional view of another structure obtained after step S24 in a method for fabricating a semiconductor structure according to an embodiment of the present application;
fig. 11 is a schematic cross-sectional structure view of another structure obtained after step S24 in a method for manufacturing a semiconductor structure according to an embodiment of the present application.
Description of reference numerals:
1-a substrate; 11-shallow trench isolation structures; a-an array region; b-a peripheral zone;
200-a first layer of conductive material; 201-interlayer dielectric material layer; 202-a layer of gate dielectric material; 203-initial interlayer dielectric layer; 204-a second layer of conductive material;
21-a first gate structure; 211-a first gate dielectric layer; 212-first gate; 213 — first contact layer; 214-first side wall;
22-a storage gate structure; 221-floating gate; 222-a control gate; 223-interlayer dielectric layer; 224-a third gate dielectric layer; 225-third contact layer; 226-third side wall;
231 — first doped contact layer; 232-second doped contact layer; 233-third doped contact layer;
31-a second gate structure; 311-a second gate dielectric layer; 312-a second gate; 313-a second contact layer; 314-second side wall; 41-a first pad; 42-a second pad; 43-a third pad; 44-a first doped pad; 45-second doped pad; 46-a third doped pad;
vd-drain voltage; vs-source voltage; vsg — first gate voltage; vcg-control gate voltage; vsub-ground voltage; vdd-operating voltage.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Embodiments of the present disclosure are presented in the drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein in the description of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein may be combined with other embodiments.
In the description of the embodiments of the present disclosure, the terms "upper", "lower", "left", "right", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the embodiments of the present disclosure and simplifying the description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the embodiments of the present disclosure.
In addition, in order to clearly show the plurality of layers and regions in the drawings, the thicknesses of the layers and the regions in the drawings are exaggerated to clearly illustrate the relative positions between the layers and the distribution of the regions. When a portion referred to as a layer, film, region, plate, or the like is "on" or "over" another portion, the description includes not only the case where "directly" over the other portion but also the case where another layer is present therebetween.
With the continuous development of semiconductor technology, nonvolatile memories are widely used in various embedded systems to store data when the system is powered off.
Currently, the mainstream nonvolatile memory includes flash memory. Flash memories are increasingly developed and applied due to the characteristics of high writing speed, high integration and the like. In development and application of flash memories, reducing the process flow of device manufacturing and improving the stability of the device are a key research point of the flash memories at present.
Therefore, how to reduce the manufacturing process flow of the memory is a problem to be solved.
Accordingly, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to effectively reduce the manufacturing process flow of the memory, to improve the production efficiency and the production yield, and to facilitate increasing the manufacturing process window, so as to improve the process stability of the device.
Referring to fig. 1, some embodiments of the present disclosure provide a semiconductor structure, including: a substrate 1, memory cells and peripheral circuitry. The substrate 1 has an array region a and a peripheral region B on at least one side of the array region a. The memory cell is located in the array area A and comprises: a first planar transistor and a memory transistor connected. The first planar transistor includes a first gate structure 21; the memory transistor includes a memory gate structure 22; the storage gate structure 22 includes: a floating gate 221 and a control gate 222 are stacked. The peripheral circuit is located in the peripheral area B and comprises a second planar transistor. The second planar transistor comprises a second gate structure 31. The surfaces of the first gate structure 21, the storage gate structure 22 and the second gate structure 31 departing from the substrate 1 are located on the same plane.
In the semiconductor structure, the surfaces of the first gate structure 21, the storage gate structure 22 and the second gate structure 31 departing from the substrate 1 are located on the same plane, that is, the total heights of the gate structures located in the array region a and the peripheral region B are the same. Therefore, in the semiconductor structure, the grid structures positioned in the array area A and the peripheral area B are beneficial to being synchronously formed by adopting the same process, so that the preparation process flow of the semiconductor structure is reduced, and the production efficiency and the production yield are improved. And in addition, the preparation process window is favorably enlarged so as to improve the process stability of the device.
Illustratively, the substrate 1 may be formed using a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 may have a single-layer structure or a multilayer structure. For example, the substrate 1 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate 1 may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator (SiGe).
Illustratively, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Optionally, the substrate 1 is a sapphire substrate, a silicon germanium substrate, or a silicon carbide substrate.
In some examples, with continued reference to fig. 1, the substrate 1 further includes a shallow trench isolation structure 11, and the shallow trench isolation structure 11 separates a plurality of active regions. Illustratively, the shallow trench isolation structure 11 may be an oxide isolation structure, such as silicon oxide (SiO) 2 ) And an isolation structure.
In some examples, the active region includes a P-well region or an N-well region. Illustratively, the active region located in the array region a is a P-well region; the active region in the peripheral region B is an N-well region.
In some embodiments of the present disclosure, referring to fig. 1 and fig. 2 (a), the first gate structure 21 includes: the first gate dielectric layer 211, the first gate electrode 212, the first contact layer 213 and the first sidewall spacers 214. The first gate dielectric layer 211 is disposed on one side of the substrate 1. The first gate electrode 212 is disposed on a surface of the first gate dielectric layer 211 away from the substrate 1. The first contact layer 213 is disposed on a surface of the first gate electrode 212 away from the first gate dielectric layer 211. The first sidewall 214 is disposed on the sidewalls of the first gate 212 and the first contact layer 213, and is located on the surface of the first gate dielectric layer 211 away from the substrate 1.
Here, it should be noted that the thickness of the first gate structure 21 is the sum of the thicknesses of the first gate dielectric layer 211, the first gate electrode 212 and the first contact layer 213.
In some examples, the first gate dielectric layer 211 includes a silicon oxide layer. The first gate 212 includes a polysilicon layer. The first contact layer 213 includes a metal silicide layer, for example, the first contact layer 213 may be cobalt silicide (CoSi) 2 ) A layer for reducing electrical resistance, thereby improving electrical performance of the semiconductor structure. The first sidewall 214 comprises a silicon nitride layer.
In some examples, the first gate 212 includes a select gate.
In some examples, a surface of the first contact layer 213 facing away from the first gate electrode 212 is further provided with a first pad 41, the first pad 41 includes a metal line, and for example, the first pad 41 may be a tungsten line.
In some embodiments of the present disclosure, with continued reference to fig. 1 and (b) of fig. 2, the second gate structure 31 includes: a second gate dielectric layer 311, a second gate 312, a second contact layer 313 and second sidewalls 314. The second gate dielectric layer 311 is disposed on one side of the substrate 1. The second gate 312 is disposed on a surface of the second gate dielectric layer 311 away from the substrate 1. The second contact layer 313 is disposed on a surface of the second gate 312 away from the second gate dielectric layer 311. The second sidewall spacers 314 are disposed on the sidewalls of the second gate 312 and the second contact layer 313, and are located on the surface of the second gate dielectric layer 311 away from the substrate 1.
Here, it should be noted that the thickness of the second gate structure 31 is the sum of the thicknesses of the second gate dielectric layer 311, the second gate 312 and the second contact layer 313.
In some examples, the second gate dielectric layer 311 includes a silicon oxide layer. The second gate 312 includes a polysilicon layer. The second contact layer 313 includes a metal silicide layer, for example, the second contact layer 313 may be cobalt silicide (CoSi) 2 ) And a layer for reducing electrical resistance, thereby improving electrical performance of the semiconductor structure. The second sidewalls 314 comprise a silicon nitride layer.
In some examples, a surface of the second contact layer 313 facing away from the second gate 312 is further provided with a second pad 42, and the second pad 42 includes a metal line, for example, the second pad 42 may be a tungsten line.
In some embodiments of the present disclosure, referring to fig. 1 and fig. 2 (c), the control gate 222 is located on a side of the floating gate 221 away from the substrate 1. The storage gate structure 22 further includes: and an interlayer dielectric layer 223 between the floating gate 221 and the control gate 222. The orthographic projections of the floating gate 221, the interlayer dielectric layer 223 and the control gate 222 on the substrate 1 are superposed. Therefore, the floating gate, the interlayer dielectric layer and the control gate can be formed by patterning through a one-time composition process, the use of masks is reduced, and cost saving is facilitated.
In some examples, the interlayer dielectric layer 223 includes an Oxide-Nitride-Oxide (Oxide-Nitride-Oxide, or ONO) layer. For example, the interlayer dielectric layer 223 may be silicon oxide (SiO) 2 ) Silicon nitride (Si) 3 N 4 ) Silicon oxide (SiO) 2 ) And (3) a layer.
In some embodiments of the present disclosure, the storage gate structure 22 further includes: a third gate dielectric layer 224, a third contact layer 225, and third sidewalls 226. Wherein, the third gate dielectric layer 224 is disposed between the substrate 1 and the floating gate 221. The third contact layer 225 is disposed on a surface of the control gate 222 away from the interlayer dielectric layer 223. The third sidewall 226 is disposed on the sidewalls of the floating gate 221, the interlayer dielectric 223, the control gate 222, and the third contact layer 225, and is located on a surface of the third gate dielectric 224 facing away from the substrate 1.
Here, it should be noted that the thickness of the storage gate structure 22 is the sum of the thicknesses of the third gate dielectric layer 224, the floating gate 221, the interlayer dielectric layer 223, the control gate 222 and the third contact layer 225.
In some examples, the third gate dielectric layer 224 includes a silicon oxide layer. The floating gate 221 includes a polysilicon layer. Control gate 222 comprises a layer of polysilicon. The third contact layer 225 includes a metal silicide layer, for example, the third contact layer 225 may be cobalt silicide (CoSi) 2 ) Layer for reducing resistance, therebyAnd the electrical performance of the semiconductor structure is improved. The third sidewall 226 includes a silicon nitride layer.
In some examples, a surface of the third contact layer 225 facing away from the control gate 222 is further provided with a third pad 43, the third pad 43 includes a metal line, for example, the third pad 43 may be a tungsten line.
The above-mentioned semiconductor structures, the gate structures located in the array region a and the gate structures located in the peripheral region B are advantageously formed simultaneously by using the same process, that is, the first gate 212, the floating gate 221 and the control gate 222 located in the array region a, and the second gate 312 located in the peripheral region B may be formed simultaneously by using the same process; the first contact layer 213, the third contact layer 225 in the array region a, and the second contact layer 313 in the peripheral region B may be simultaneously formed by the same process. Therefore, the preparation process flow of the semiconductor structure can be further reduced, so that the production efficiency and the production yield are improved. And in addition, the preparation process window is favorably enlarged so as to improve the process stability of the device.
In some examples, with continued reference to fig. 1, an N-type doped region is formed within the P-well region and a P-type doped region or a PN-type doped region is formed within the N-well region.
Illustratively, an N-type doped region is formed in the P-well region exposed outside the first gate structure 21 and the storage gate structure 22. Based on this, the N-type doped region located in the P-well region between the first gate structure 21 and the storage gate structure 22 can be shared by the first planar transistor and the storage transistor, that is: the electrical connection between the first planar transistor and the memory transistor may be achieved using the common N-type doped region.
Illustratively, a P-type doped region and a PN-type doped region are formed in the N-well region exposed outside the second gate structure 31. That is, a P-type doped region and a PN-type doped region are formed in the N-well region exposed outside the second planar transistor.
Furthermore, the surface of the N-doped region facing away from the substrate 1 is provided, by way of example, with a first doped contact layer 231. The surface of the P-doped region facing away from the substrate is provided with a second doped contact layer 232. The surface of the PN-doped region facing away from the substrate is provided with a third doped contact layer 233. First doped contact layer 231, secondThe second doped contact layer 232 or the third doped contact layer 233 includes a metal silicide layer, for example, the first doped contact layer 231, the second doped contact layer 232 or the third doped contact layer 233 may be cobalt silicide (CoSi) 2 ) A layer for reducing electrical resistance, thereby improving electrical performance of the semiconductor structure.
Illustratively, the surface of the first doped contact layer 231 facing away from the N-type contact region is further provided with a first doped pad 44. The surface of the second doped contact layer 232 facing away from the P-type contact region is also provided with a second doped pad 45. The surface of the third doped contact layer 233 facing away from the PN-type contact region is also provided with a third doped pad 46. First doped pad 44, second doped pad 45, or third doped pad 46 includes a metal line, for example, first doped pad 44, second doped pad 45, or third doped pad 46 may be a tungsten line.
Some embodiments of the present disclosure also provide a method for fabricating a semiconductor structure, which is used to fabricate the semiconductor structure as described in some embodiments above. Referring to fig. 3, the preparation method includes the following steps.
S10: a substrate is provided, and the substrate is provided with an array area and a peripheral area positioned on at least one side of the array area.
S20: respectively forming a first gate structure and a storage gate structure on the part of the substrate located in the array region, and forming a second gate structure on the part of the substrate located in the peripheral region; the storage grid structure comprises a floating grid and a control grid which are arranged in a stacked mode; the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are positioned on the same plane.
In the preparation method of the semiconductor structure, the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are positioned on the same plane, namely, the total height of the gate structure formed on the array region of the substrate is the same as that of the gate structure formed on the peripheral region of the substrate. Therefore, in the semiconductor structure, the grid structures formed on the substrate in the array area and the substrate in the peripheral area are beneficial to being synchronously formed by adopting the same process, so that the preparation process flow of the semiconductor structure is reduced, and the production efficiency and the production yield are improved. And in addition, the preparation process window is favorably enlarged so as to improve the process stability of the device.
In order to more clearly illustrate the method for manufacturing the semiconductor structure provided by the embodiments of the present disclosure, some embodiments are described in detail below with reference to the semiconductor structure shown in fig. 1 as an example.
In step S10, referring to fig. 4, a substrate 1 is provided, where the substrate 1 has an array region a and a peripheral region B located at least one side of the array region a.
Illustratively, the substrate 1 may be formed using a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 may have a single-layer structure or a multilayer structure. For example, the substrate 1 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate 1 may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator (SiGe).
Illustratively, the substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Optionally, the substrate 1 is a sapphire substrate, a silicon germanium substrate, or a silicon carbide substrate.
In some examples, after providing the substrate 10, further comprising: forming a shallow trench isolation structure 11 in the substrate 1, and separating an active region from the shallow trench isolation structure 11. The specific method for forming the sti structure 11 in the substrate 1 is known to those skilled in the art and will not be described herein.
Illustratively, the shallow trench isolation structure 11 may be an oxide isolation structure, such as silicon oxide (SiO) 2 ) And an isolation structure.
In some examples, with continued reference to fig. 4, after forming the shallow trench isolation structure 11 in the substrate 1, the method further includes: the active region of the substrate 10 is ion implanted to form a corresponding type of well region. Illustratively, P-type ion implantation is performed on an active region located in the array region A to form a P well region (PW); n-type ion implantation is performed on the active region in the peripheral region B to form an N well region (NW).
In step S20, referring to fig. 5 to 11, a first gate structure 21 and a storage gate structure 22 are respectively formed on a portion of the substrate 1 located in the array region a, and a second gate structure 31 is formed on a portion of the substrate 1 located in the peripheral region B. The memory gate structure 22 includes a floating gate 221 and a control gate 222 stacked together; the surfaces of the first gate structure 21, the storage gate structure 22 and the second gate structure 31, which face away from the substrate 1, are located on the same plane.
Here, it should be specifically noted that the control gate 222 is located on a side of the floating gate 221 facing away from the substrate 1; the storage gate structure 22 further includes: an interlayer dielectric layer 223 between the floating gate 221 and the control gate 222.
In some embodiments of the present disclosure, referring to fig. 5, the step S20 of forming the first gate structure 21 and the storage gate structure 22 on the portion of the substrate 1 located in the array region a and forming the second gate structure 31 on the portion of the substrate 1 located in the peripheral region B respectively includes the following steps:
s21: a first conductive material layer and an interlayer dielectric material layer are sequentially formed on one side of a substrate.
S22: and patterning the interlayer dielectric material layer to form an initial interlayer dielectric layer.
S23: and forming a second conductive material layer, wherein the second conductive material layer covers the initial interlayer dielectric layer and the surface of the first conductive material layer which is not covered by the interlayer dielectric layer.
S24: and patterning the second conductive material layer, the initial interlayer dielectric layer and the first conductive material layer to form a first grid electrode of the first grid structure and a floating grid electrode, an interlayer dielectric layer and a control grid electrode of the storage grid structure on the part of the substrate positioned in the array area respectively, and form a second grid electrode of the second grid structure on the part of the substrate positioned in the peripheral area.
In the method for manufacturing the semiconductor structure, the second conductive material layer, the initial interlayer dielectric layer and the first conductive material layer are patterned to form the first gate 212, the floating gate 221, the interlayer dielectric layer 223 and the control gate 222 on the portion of the substrate 1 in the array region a, and form the second gate 312 on the portion of the substrate 1 in the peripheral region B. Thus, the first gate 212, the floating gate 221, the interlayer dielectric layer 223, the control gate 222 and the second gate 312 can be formed by patterning through a one-time composition process, so that the use of masks is reduced, and the cost is saved.
In step S21, referring to fig. 6, a first conductive material layer 200 and an interlayer dielectric material layer 201 are sequentially formed on one side of the substrate 1.
Alternatively, a deposition process may be employed to form the first conductive material layer 200 and the interlayer dielectric material layer 201.
In some examples, forming an interlayer dielectric material layer 201 on a substrate 1 includes: a first oxide material layer (not shown), a nitride material layer (not shown) and a second oxide material layer (not shown) are sequentially formed on the surface of the first conductive material layer 200 away from the substrate 1.
In some examples, before forming the first conductive material layer 200 on the substrate 1 side in step S21, the preparation method further includes: forming a gate dielectric material layer 202 on the surface of the substrate 1; the first conductive material layer 200 is further formed on a surface of the gate dielectric material layer 202, which faces away from the substrate 1.
Optionally, forming the gate dielectric material layer 202 on the surface of the substrate 1 includes forming the gate dielectric material layer 202 on the surface of the substrate 1 by a deposition process.
In step S22, referring to fig. 7, the interlayer dielectric material layer 201 is patterned to form an initial interlayer dielectric layer 203.
In step S23, referring to fig. 8, a second conductive material layer 204 is formed, wherein the second conductive material layer 204 covers the initial interlayer dielectric layer 203 and the surface of the first conductive material layer 200 not covered by the initial interlayer dielectric layer 203.
Optionally, forming the second conductive material layer 204 includes forming the second conductive material layer 204 using a deposition process.
In step S24, referring to fig. 9, the second conductive material layer 204, the initial interlayer dielectric layer 203 and the first conductive material layer 200 are patterned to form the first gate 212 of the first gate structure 21 and the floating gate 221, the interlayer dielectric layer 223 and the control gate 222 of the storage gate structure 22 on the portion of the substrate 1 in the array region a, and form the second gate 312 of the second gate structure 31 on the portion of the substrate 1 in the peripheral region B, respectively.
In some embodiments of the present disclosure, referring to fig. 10, forming a first gate structure 21 and a storage gate structure 22 on a portion of the substrate 1 located in the array region a, and forming a second gate structure 31 on a portion of the substrate 1 located in the peripheral region B, further includes: a first contact layer 213 is formed on the surface of the first gate 212 away from the substrate 1, and a first sidewall 214 is formed on the sidewalls of the first gate 212 and the first contact layer 213. A second contact layer 313 is formed on the surface of the second gate 312 opposite to the substrate 1, and a second sidewall 314 is formed on the sidewalls of the second gate 312 and the second contact layer 313. A third contact layer 225 is formed on the surface of the control gate 222 away from the interlayer dielectric layer 223, and a third sidewall 226 is formed on the sidewalls of the floating gate 221, the interlayer dielectric layer 223, the control gate 222 and the third contact layer 225.
In some examples, the first contact layer 213, the second contact layer 313, and the third contact layer 225 may be formed through a deposition process and may also be formed through a silicon metallization process.
Optionally, a sidewall process may be used to form the first sidewall 214, the second sidewall 314, and the third sidewall 226.
In some examples, the first sidewall 214, the second sidewall 314, and the third sidewall 226 may be a single-layer structure or a multi-layer structure. For example, the first, second and third sidewalls 214, 314 and 226 may be formed of a stacked structure of silicon oxide, silicon nitride and silicon oxide.
In some examples, with continued reference to fig. 10, before forming the first sidewall 214, the second sidewall 314, and the third sidewall 226, the preparation method further includes: the gate dielectric material layer 202 is patterned to form a first gate dielectric layer 211 between the substrate 1 and the first gate electrode 212, a second gate dielectric layer 311 between the substrate 1 and the second gate electrode 312, and a third gate dielectric layer 224 between the substrate 1 and the floating gate electrode 221. The first sidewall 214 is further formed on the surface of the first gate dielectric layer 211 away from the substrate 1, the second sidewall 314 is further formed on the surface of the second gate dielectric layer 311 away from the substrate 1, and the third sidewall 226 is further formed on the surface of the third gate dielectric layer 224 away from the substrate 1.
Here, it should be noted that the thickness of the first gate structure 21 is the sum of the thicknesses of the first gate dielectric layer 211, the first gate electrode 212 and the first contact layer 213. The thickness of the storage gate structure 22 is the sum of the thicknesses of the third gate dielectric layer 224, the floating gate 221, the interlayer dielectric layer 223, the control gate 222 and the third contact layer 225. The thickness of the second gate structure 31 is the sum of the thicknesses of the second gate dielectric layer 311, the second gate 312 and the second contact layer 313.
In some examples, referring to fig. 11, after forming the first, second, and third sidewalls 214, 314, 226, the method further includes: the portions of the substrate 1 exposed outside the first, second, and third sidewalls 214, 314, and 226 are ion-implanted to form contact regions.
Illustratively, the P-well region exposed outside the first gate structure 21 and the storage gate structure 22 is subjected to N-type ion implantation to form an N-type doped region. P-type ions and N-type ions are implanted into the N-well exposed outside the second gate structure 31 to form a P-type doped region and a PN-type doped region.
In some examples, a surface of the first contact layer 213 facing away from the first gate 212 is also provided with a first pad 41. The surface of the second contact layer 313 facing away from the second gate 312 is also provided with a second pad 42. The surface of the third contact layer 225 facing away from the control gate 222 is also provided with a third pad 43. Alternatively, the first, second, and third pads 41, 42, and 43 include metal lines, for example, the first, second, and third pads 41, 42, and 43 may be tungsten lines.
Furthermore, the surface of the N-doped region facing away from the substrate 1 is provided, by way of example, with a first doped contact layer 231. The surface of the P-doped region facing away from the substrate is provided with a second doped contact layer 232. The surface of the PN-doped region facing away from the substrate is provided with a third doped contact layer 233. The first, second, or third doped contact layers 231, 232, 233 include a metal silicide layer, for example, the first, second, or third doped contact layers 231, 232, 233 may be cobalt silicide (CoSi) 2 ) And a layer for reducing electrical resistance, thereby improving electrical performance of the semiconductor structure.
Illustratively, a surface of the first doped contact layer 231 facing away from the N-type contact region is also provided with a first doped pad 44. The surface of the second doped contact layer 232 facing away from the P-type contact region is also provided with a second doped pad 45. The surface of the third doped contact layer 233 facing away from the PN-type contact region is also provided with a third doped pad 46. First doped pad 44, second doped pad 45, or third doped pad 46 includes a metal line, for example, first doped pad 44, second doped pad 45, or third doped pad 46 may be a tungsten line.
In some embodiments of the present disclosure, referring to table 1 and fig. 11, the method for fabricating the semiconductor structure can be applied to fabricate a flash memory. That is, the semiconductor structure provided in the embodiments of the present application may be, for example, a flash memory. The embodiment of the disclosure exemplarily illustrates the operation process of the memory cell in the flash memory, which is described in detail as follows.
The operation process of a flash memory generally includes three phases, a data write phase, a data read phase and a data erase phase. In a semiconductor structure provided by the embodiment of the present disclosure, a first gate electrode 212 in a memory cell is connected to a first gate voltage terminal through a first pad 41; the control gate 222 is connected to the control gate voltage terminal through the third pad 43; a source (not shown) is connected to a source voltage terminal through one of the first doped pads 44; the drain (not shown) is connected to a drain voltage terminal through one of the first doped pads 44.
In the data writing phase, the control gate voltage terminal applies a voltage to the control gate 222, so that the voltage Vcg of the control gate is a Positive High Voltage (PHV). The ground voltage Vsub is 0. The source voltage terminal is grounded, and a source voltage Vs is provided to the source, so that the voltage Vs at the source is 0. The drain voltage terminal is grounded, and a drain voltage Vd is provided to the drain, so that the voltage Vd of the drain is 0. The first gate voltage terminal is grounded, and the first gate voltage Vsg is provided to the first gate 212, so that the voltage Vsg of the first gate is 0.
In the data erasing phase, the control gate voltage terminal reversely applies a voltage to the control gate 222, so that the voltage Vcg of the control gate is a Negative High Voltage (NHV). The source voltage Vs and the drain voltage Vd are both floating. The ground voltage Vsub is 0. The first gate voltage terminal is grounded, and the first gate voltage Vsg is provided to the first gate 212, so that the voltage Vsg of the first gate is 0.
In the data read phase, the ground voltage Vsub is 0. The source voltage terminal is grounded, and a source voltage Vs is provided to the source, so that the voltage Vs at the source is 0. The drain voltage terminal, the first gate voltage terminal and the control gate voltage terminal all provide a working voltage Vdd, such that the drain voltage Vd is the working voltage Vdd, the first gate voltage Vsg is the working voltage Vdd, and the control gate voltage Vsg is the working voltage Vdd.
TABLE 1 working principle of flash memory
| Operation of | Vsub | Vs | Vd | Vsg | Vcg |
| Writing in | 0 | 0 | 0 | 0 | PHV |
| Erasing | 0 | Float in the air | Float in air | 0 | NHV |
| Reading | 0 | 0 | Vdd | Vdd | Vdd |
In the description of the present specification, various technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features of the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present disclosure, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the concept of the present disclosure, and these changes and modifications are all within the scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the appended claims.
Claims (10)
1. A semiconductor structure, comprising:
the array structure comprises a substrate, a first electrode and a second electrode, wherein the substrate is provided with an array area and a peripheral area positioned on at least one side of the array area;
a memory cell located in the array region, comprising: a first planar transistor and a memory transistor connected; the first planar transistor comprises a first gate structure; the memory transistor includes a memory gate structure; the storage gate structure includes: a floating gate and a control gate arranged in a stacked manner;
and a peripheral circuit located in the peripheral region and including a second planar transistor; the second planar transistor comprises a second gate structure;
the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are located on the same plane.
2. The semiconductor structure of claim 1, wherein the first gate structure comprises:
the first gate dielectric layer is arranged on one side of the substrate;
the first grid electrode is arranged on the surface of the first grid dielectric layer, which is deviated from the substrate;
the first contact layer is arranged on the surface of the first grid electrode, which is deviated from the first grid dielectric layer;
and the first side wall is arranged on the side walls of the first grid electrode and the first contact layer and is positioned on the surface of the first grid dielectric layer deviating from the substrate.
3. The semiconductor structure of claim 2, wherein the second gate structure comprises:
the second gate dielectric layer is arranged on one side of the substrate;
the second grid electrode is arranged on the surface of the second grid dielectric layer, which is deviated from the substrate;
the second contact layer is arranged on the surface, away from the second gate dielectric layer, of the second gate electrode;
and the second side wall is arranged on the side walls of the second grid electrode and the second contact layer and is positioned on the surface of the second grid dielectric layer deviating from the substrate.
4. The semiconductor structure according to any one of claims 1 to 3, wherein the control gate is located on a side of the floating gate away from the substrate; the storage gate structure further includes:
the interlayer dielectric layer is positioned between the floating grid and the control grid;
and orthographic projections of the floating grid, the interlayer dielectric layer and the control grid on the substrate are superposed.
5. The semiconductor structure of claim 4, wherein the memory gate structure further comprises:
the third gate dielectric layer is arranged between the substrate and the floating gate;
the third contact layer is arranged on the surface of the control grid electrode, which is deviated from the interlayer dielectric layer;
and the third side wall is arranged on the side walls of the floating gate, the interlayer dielectric layer, the control gate and the third contact layer and is positioned on the surface of the third gate dielectric layer deviating from the substrate.
6. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with an array area and a peripheral area positioned on at least one side of the array area;
respectively forming a first gate structure and a storage gate structure on the part of the substrate, which is positioned in the array area, and forming a second gate structure on the part of the substrate, which is positioned in the peripheral area;
the storage gate structure comprises a floating gate and a control gate which are arranged in a stacked mode; the surfaces of the first gate structure, the storage gate structure and the second gate structure, which deviate from the substrate, are located on the same plane.
7. The method of fabricating a semiconductor structure according to claim 6, wherein the control gate is located on a side of the floating gate facing away from the substrate; the storage gate structure further includes: an interlayer dielectric layer positioned between the floating gate and the control gate;
the forming a first gate structure and a storage gate structure on the portion of the substrate located in the array region, and forming a second gate structure on the portion of the substrate located in the peripheral region respectively includes:
sequentially forming a first conductive material layer and an interlayer dielectric material layer on one side of the substrate;
imaging the interlayer dielectric material layer to form an initial interlayer dielectric layer;
forming a second conductive material layer covering the initial interlayer dielectric layer and the surface of the first conductive material layer not covered by the initial interlayer dielectric layer;
and patterning the second conductive material layer, the initial interlayer dielectric layer and the first conductive material layer to form a first gate of the first gate structure and the floating gate, the interlayer dielectric layer and the control gate of the storage gate structure on the part of the substrate in the array region, and form a second gate of the second gate structure on the part of the substrate in the peripheral region.
8. The method of fabricating a semiconductor structure according to claim 7, wherein forming the interlayer dielectric material layer on the substrate comprises:
and sequentially forming a first oxide material layer, a nitride material layer and a second oxide material layer on the surface of the first conductive material layer, which is far away from the substrate.
9. The method of claim 7, wherein the forming a first gate structure and a memory gate structure on the portion of the substrate in the array region and a second gate structure on the portion of the substrate in the peripheral region respectively, further comprises:
forming a first contact layer on the surface of the first grid electrode, which is far away from the substrate, and forming a first side wall on the side walls of the first grid electrode and the first contact layer;
forming a second contact layer on the surface of the second grid electrode, which is far away from the substrate, and forming a second side wall on the side wall of the second grid electrode and the second contact layer;
and forming a third contact layer on the surface of the control grid electrode deviating from the interlayer dielectric layer, and forming a third side wall on the side walls of the floating grid electrode, the interlayer dielectric layer, the control grid electrode and the third contact layer.
10. The method of fabricating a semiconductor structure according to claim 9,
before forming the first conductive material layer on one side of the substrate, the preparation method further comprises: forming a gate dielectric material layer on the surface of the substrate; the first conductive material layer is further formed on the surface, away from the substrate, of the gate dielectric material layer;
before the first side wall, the second side wall and the third side wall are formed, the preparation method further comprises the following steps: patterning the gate dielectric material layer to form a first gate dielectric layer between the substrate and the first gate, a second gate dielectric layer between the substrate and the second gate, and a third gate dielectric layer between the substrate and the floating gate; the first side wall is further formed on the surface, away from the substrate, of the first gate dielectric layer, the second side wall is further formed on the surface, away from the substrate, of the second gate dielectric layer, and the third side wall is further formed on the surface, away from the substrate, of the third gate dielectric layer.
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