JPH1084051A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the manufacturing steps in a whole erasable semiconductor non-volatile memory wherein the transistors comprising memory cells are arranged in parallel with one another so that the adjacent memory cells, mutual sources and drains may be commonly connected. SOLUTION: The second insulating film 11 is molded before the formation of floating gate electrodes 8 and then apertures 12 are formed on the positions to be the channel regions 6 of the transistor of the second insulating film 11 next, the impurity ions for the formation of the impurity semiconductor regions 4, 5 to be source and drain are obliquely implanted so as to form the floating gate electrodes 8 later.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique which is effective when applied to an electrically erasing semiconductor nonvolatile memory device (hereinafter, referred to as a flash memory). Things.

[0002]

2. Description of the Related Art When a field effect transistor (MOSFET) having a MOS structure is manufactured, a source / drain region can be formed in a self-aligned manner with respect to a gate electrode. The formation is performed by using an ion implantation method after forming the gate electrode. Similarly, in an electrically rewritable read-only memory (EEPROM),
Processing the floating gate (floating gate electrode)
After the formation, a photoresist step and an impurity ion implantation step are generally performed.

[0003] For example, IEE
EE) issued, IEDM 92 (IEDM)
92), a flash memory described in p991, that is, a flash memory in which transistors forming a memory cell are arranged in parallel so that an adjacent memory cell and a source region and a drain region are connected to each other in common For example, Japanese Patent Application Laid-Open No.
As described in JP-A-92-92, a manufacturing method in which an impurity semiconductor region is formed after a gate electrode is formed as described above is employed.

In such a flash memory, the floating gate has a two-layer structure because of the necessity of further increasing the capacitance between the floating gate and a control gate (control gate electrode). A structure is employed in which the gate film is extended to above the source region and the drain region.

Because of the necessity of adopting the two-layer floating gate structure, an oxide film is required to ensure insulation between the electrode film forming the second layer of the floating gate and the impurity semiconductor region which is the source / drain region. Becomes
This oxide film is formed by performing high-concentration ion implantation using the first-layer gate as a mask after the formation of the first-layer gate, and selectively oxidizing the surface of the semiconductor substrate on which the ion implantation has been performed. That is, a selective oxidation step for forming an oxide film on the impurity semiconductor region that is the source / drain region is added.

Further, in the above flash memory, the impurity concentration distributions of the source region and the drain region of the transistor are different from each other due to the necessity of injecting charges into the floating gate through the tunnel insulating film and preventing the transistor from punching through. For this reason, a manufacturing method has been adopted in which the steps of implanting ions into the source region and the drain region are separated, and a photoresist forming step is separately added to separately form the photoresist.

[0007]

In the flash memory described above, the floating gate has a two-layer structure, a step of selectively oxidizing an impurity semiconductor region, and two impurities for making the impurity concentration of a source region and a drain region different. It is necessary to go through many complicated and complicated steps such as an injection step.

[0008] Such an increase in the number and complexity of the steps not only increases the manufacturing cost due to an increase in the number of steps, but also causes dimensional variations of members formed in each step, misalignment, or characteristics of the formed members. This causes variations in the performance of the semiconductor integrated circuit device, which causes a reduction in product yield and a reduction in product reliability.

An object of the present invention is to reduce the number of steps in manufacturing a semiconductor integrated circuit device having a nonvolatile memory cell, to reduce the manufacturing cost, to improve the product yield, and to further improve the semiconductor integrated circuit device. It is an object of the present invention to provide a structure of a nonvolatile memory cell capable of improving the performance of the device and a method of manufacturing the same.

Another object of the present invention is to provide a nonvolatile memory cell having a simple structure which does not require the floating gate to have a two-layer structure and can secure a capacity between the floating gate and the control gate. And a semiconductor integrated circuit device having the same.

Still another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which can easily form a semiconductor integrated circuit device having a nonvolatile memory cell having a simple structure as described above in a small number of steps. To provide.

Still another object of the present invention is to provide a semiconductor integrated circuit device having a nonvolatile memory cell capable of easily obtaining different impurity concentration distributions in a source region and a drain region of a transistor constituting the nonvolatile memory cell. It is to provide a manufacturing method of.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device of the present invention is formed in an element isolation region formed on a main surface of a semiconductor substrate, an active region surrounded by the element isolation region, and in the vicinity of the main surface of the active region. A source region and a drain region; a tunnel insulating film formed on a channel region located between the source region and the drain region; a floating gate electrode formed on the tunnel insulating film; A semiconductor integrated circuit device having a nonvolatile memory cell including a control gate electrode formed with an insulating film interposed therebetween, wherein a tunnel insulating film is formed on a second insulating film formed on a main surface of the semiconductor substrate. The floating gate electrode is formed on the main surface of the bottom of the opening, and the floating gate electrode is formed on the tunnel insulating film and the second insulating film and formed of a single-layer film or a laminated film having a substantially uniform thickness. It is intended to be made.

According to such a semiconductor integrated circuit device,
Second tunnel insulating film is formed on the main surface of the semiconductor substrate.
Is formed on the main surface of the bottom of the opening formed in the insulating film, and the floating gate electrode is formed on the tunnel insulating film and the second insulating film. Therefore, the area of the floating gate electrode is reduced by the capacitance with the control gate electrode. Area can be ensured enough to secure

Further, since the floating gate electrode is composed of a single layer film or a laminated film having a substantially uniform thickness, the floating gate electrode is formed on the tunnel insulating film by two lithography steps like a conventional two-layer structure film. In addition, there is no need to form a floating gate electrode over the second insulating film, and the floating gate electrode can be formed by one lithography step.

Thus, it is possible to secure a capacitance between the floating gate electrode and the control gate electrode and to provide a nonvolatile memory cell structure in which the manufacturing process can be easily simplified.

(2) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (1), wherein the channel region is formed in a central region of the opening, and the source region and the drain region are formed in the opening. Are formed in the end region of the.

According to such a semiconductor integrated circuit device,
Since the upper layers of the source region and the drain region are covered with the tunnel insulating film and the second insulating film formed by the CVD method, the source region and the drain region are covered with the selective oxide film as in the conventional structure. No need. Therefore, it is possible to avoid the complexity of the manufacturing process due to the use of the selective oxide film, to improve the yield and reliability of the semiconductor integrated circuit device, and to reduce the variation in the element characteristics. The performance of the integrated circuit device can be improved.

That is, in the conventional structure, the source / drain regions are formed after the formation of the floating gate electrode,
After that, the selective oxidation method was used to form a selective oxide film on the source / drain regions. However, if the alignment of the floating gate electrode is misaligned with the element isolation region, it is inevitable from the principle of the selective oxidation method. This results in a variation in the film thickness. This variation in film thickness causes variation in device characteristics, resulting in lower yield and lower reliability. However, in the present invention, the selective oxide film is not used, and the source insulating film is formed by the second insulating film formed by the CVD method.
Since the drain region and the floating gate electrode are insulated from each other, the second film thickness does not vary even if the opening position is shifted with respect to the device isolation region, and the device characteristics vary, the reliability and the yield increase. Does not cause a decline.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (1) or (2), wherein the width of the opening is at least twice the thickness of the floating gate electrode. Things.

According to such a semiconductor integrated circuit device,
Since the width of the opening is at least twice the film thickness of the floating gate electrode, the capacitance between the control gate electrode and the floating gate electrode can be further increased.

That is, when the width of the opening is twice or more the thickness of the floating gate electrode, the floating gate electrode covers the inside of the opening along its shape. In such a case, The area of the floating gate electrode can be increased by an area corresponding to the side surface of the opening, and the increase in the area directly increases the capacitance between the control gate electrode and the floating gate electrode. As a result, a large coupling capacitance can be obtained with a small area, and it is possible to cope with miniaturization of a semiconductor integrated circuit device.

(4) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1) to (3),
A source region or a drain region of a plurality of nonvolatile memory cells is shared as a single source region or a drain region, so that the nonvolatile memory cells have an AND type memory cell block structure in which the nonvolatile memory cells are connected in parallel; In addition, the information stored in the nonvolatile memory cells is electrically erased collectively.

Such a semiconductor integrated circuit device is generally called an AND type flash memory.
The semiconductor integrated circuit devices described in (1) to (3) are suitable for use in the structure of an AND type flash memory.

That is, an opening on the slit is formed in the second insulating film, a plurality of nonvolatile memory cells are arranged along the opening, and one memory cell corresponds to a 1-bit storage element. . In this case, the control gate electrode and the floating gate electrode are arranged in a direction perpendicular to the direction of the slit, and the source region and the drain region between the memory cells are formed along one end of the bottom surface of the slit-shaped opening. is there.

According to such a semiconductor integrated circuit device,
It has a simple structure, can be easily manufactured,
An AND-type flash memory which can easily cope with high integration can be obtained.

(5) The semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to any one of (1) to (4), wherein (a) an element isolation region is formed on a main surface of the semiconductor substrate. Forming a second insulating film over the entire surface of the semiconductor substrate; and (b) selectively forming a region to be a channel region of the nonvolatile memory cell and a region between adjacent nonvolatile memory cells sandwiched between the regions. (C) forming one impurity semiconductor region serving as a source region or a drain region near one end of the bottom of the opening, and forming one end of the bottom of the opening bottom; Forming another impurity semiconductor region serving as a source region or a drain region in the vicinity of the other end side opposite to the side, (d) forming a tunnel insulating film on the main surface of the semiconductor substrate at the bottom of the opening, and (e). A single layer on the entire surface of the semiconductor substrate Forms a first conductive film pattern of a preceding stage to be a floating gate electrode on a surface of a second insulating film including an opening by depositing a stacked first conductive film and patterning the first conductive film (F) sequentially depositing an insulating film serving as a first insulating film and a second conductive film serving as a control gate electrode on the entire surface of the semiconductor substrate on which the first conductive film pattern is formed; Patterning an insulating film to be a first insulating film to form a control gate electrode; and (g) patterning a first conductive film pattern to form a floating gate electrode.

According to such a method of manufacturing a semiconductor integrated circuit device, an opening is formed in the second insulating film formed on the main surface of the semiconductor substrate, and the source and the source are formed near the opposite edges of the bottom surface of the opening. Since a tunnel insulating film is formed after providing a drain region, and then a single-layer or simple stacked floating gate electrode is provided, a source / drain region is provided after a first-layer floating gate electrode is provided as in the conventional case. To form
The floating gate has a sufficiently large coupling capacitance between the floating gate electrode and the control gate electrode without going through a complicated manufacturing process of forming a selective oxide film on the source / drain region and further forming a second floating gate electrode. A gate electrode can be formed.

As a result, the formation of the floating gate electrode can be simplified, the manufacturing process can be simplified, and the yield and reliability of the semiconductor integrated circuit device can be improved and the manufacturing cost can be reduced.

(6) The semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to the above (5), wherein the impurity semiconductor region in the step (c) is formed in such a manner that the semiconductor substrate has a direction of incidence of ions. Installed at an angle to the second
Is formed by an oblique ion implantation method formed in a self-aligned manner using the opening of the insulating film as a mask.

According to such a method of manufacturing a semiconductor integrated circuit device, since the impurity semiconductor region is formed by oblique ion implantation using the opening of the second insulating film as a mask, self-alignment can be performed without using a mask. And can easily cope with miniaturization of the semiconductor integrated circuit device.

In the oblique ion implantation, since the formation of the source region and the formation of the drain region are performed separately, the dose of each region can be controlled independently, and the dose to the floating gate electrode via the tunnel insulating film can be controlled. The charge injection efficiency and the countermeasures against punch-through can be easily optimized.

Further, since the incident angle of the impurity ions is controlled by changing the installation angle of the semiconductor substrate, it is possible to optimize the formation position of the impurity semiconductor region. In this case, the formation position of the impurity semiconductor region is geometrically determined by the incident angle of the impurity ions and the width and depth of the opening. As described above, being uniquely determined geometrically has an advantage that ion implantation conditions can be easily set.

In the impurity semiconductor region, a first ion implantation step in which the channel region and the other end are masked with a photoresist and ion implantation is performed near one end, and the channel region and the one end are formed in the impurity semiconductor region. It may be formed through a second ion implantation step of masking with a photoresist and implanting ions near other edges.

In such a case, the impurity ions are not necessarily implanted obliquely but may be implanted directly above. Therefore, other conditions can be set without being restricted by the condition of the incident angle of the impurity ions.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1A is a top view showing an example of a flash memory according to an embodiment of the present invention with respect to its memory cell region, and FIG. 1B and FIG. 1C.
FIG. 2 is a cross-sectional view taken along line bb and line cc in FIG.

The flash memory according to the present embodiment has a plurality of nonvolatile memory cells in an active region 3 formed on a semiconductor substrate 1 and surrounded by a field insulating film 2 made of, for example, a LOCOS oxide film. The source region of the transistor forming the memory cell is shared by the impurity semiconductor region 4, and the drain region is also shared by the impurity semiconductor region 5 to form an AND cell structure in which the memory cells are connected in parallel. Have

One nonvolatile memory cell has an active region 3
The impurity semiconductor region 4 which is a source region and the impurity semiconductor region 5 which is a drain region, and the tunnel insulating film 7 which is formed in an upper layer of a channel region 6 interposed between a source region and a drain region. It comprises a floating gate electrode 8 formed and a control gate electrode 10 formed on the floating gate electrode 8 via a first insulating film 9.

The impurity semiconductor region 4 and the impurity semiconductor region 5 formed in the active region 3 are shared by a plurality of memory cells as described above, and a memory block is constituted by the plurality of linearly arranged memory cells. Thus, impurity semiconductor region 4 and impurity semiconductor region 5 function as bit lines (data lines) in the memory block.
The bit line is connected to the select MOSFET at the end of the memory block.
Connected to T.

The tunnel insulating film 7 is formed on the bottom surface of the opening 12 of the second insulating film 11 formed on the semiconductor substrate 1. The opening 12 is formed in a slit shape in a direction parallel to the bit line, and is formed along an array of a plurality of memory cells. That is, the memory cells in one memory block are arranged along the opening 12. The second insulating film 11
For example, a silicon oxide film formed by a CVD method or an SOG method can be used.

The floating gate electrode 8 is formed along the opening 12, a part of which is on the tunnel insulating film 7, and a part of which is
It is formed on the upper surface of the insulating film 11. The floating gate electrode 8 is formed of a single layer, for example, a polycrystalline silicon film. Thus, the floating gate electrode 8 is
Not only the upper surface but also the upper surface of the second insulating film 11 or the opening 12
Are formed also on the side surfaces of the opening, so that the coupling capacitance with the control gate electrode 10 can be increased.
Is formed in a single layer along, so that a plurality of masks can be used to separate the lower floating gate electrode and the upper floating gate electrode using a plurality of masks as in the conventional process, and can be formed without going through a complicated process. . As will be described later, the floating gate electrode 8 can be formed by simply depositing a thin film and processing it by a known etching technique. The floating gate electrode 8 is not processed using a sophisticated and delicate manufacturing process. It can be formed by an easy process. Note that the floating gate electrode 8 may be a stacked film in which a plurality of uniform thin films are stacked. However, the laminated film in this case includes a laminated film formed by a complicated process in which the lower floating gate electrode is formed by a mask process and then the upper floating gate electrode is formed by a mask process as in the conventional process. Rather, it refers to a stacked film in which single-layer films are simply stacked.

The control gate electrode 10 is made of, for example, a polycrystalline silicon film and extends perpendicular to the bit line. The control gate electrode 10 extends to a different memory block and functions as a word line of the flash memory.

According to such a flash memory, the floating gate electrode 8 forms the tunnel insulating film 7 and the second insulating film 1
1, the area of the floating gate electrode 8 can be made sufficient to secure the capacitance with the control gate electrode 10.

Further, since the floating gate electrode 8 is composed of a single-layer film or a laminated film having a substantially uniform film thickness, a sufficient area can be obtained by two lithography steps like a conventional two-layer structure film. The floating gate electrode 8 need not be formed, and can be formed in one lithography step.

Thus, the coupling capacitance between the floating gate electrode 8 and the control gate electrode 10 can be ensured, and the manufacturing process can be simplified.

Furthermore, since the upper layers of impurity semiconductor regions 4 and 5, which are the source and drain regions, are covered with tunnel insulating film 7 and second insulating film 11, the source and drain regions are formed as in the conventional structure. There is no need to cover the region with a selective oxide film. Therefore, the complexity of the manufacturing process can be avoided, the yield and the reliability of the semiconductor integrated circuit device can be improved, and the performance of the semiconductor integrated circuit device can be improved by reducing the variation in element characteristics. Can be planned.

In the flash memory according to the present embodiment, the width of the opening 12 is set to be equal to the thickness of the floating gate electrode 8.
More than double. In such a case, the capacitance between the control gate electrode 10 and the floating gate electrode 8 can be increased, which is advantageous for miniaturization of the element.

Next, a method of manufacturing the flash memory according to the present embodiment will be described with reference to FIGS.

First, as shown in FIG.
The field insulating film 2 is formed on the main surface of the semiconductor substrate 1 by the S method.
To form The semiconductor substrate 1 is a storage MOS of a memory cell.
When forming an n-type MOSFET as an FET,
A p-type substrate doped with a p-type impurity, for example, boron, can be used.

Next, as shown in FIG.
Is formed on the entire surface of the semiconductor substrate 1. This second insulating film 1
1 has two roles. The first role is a role as an ion shielding film in a later-described oblique ion implantation process, and the second role is a role as an insulating film between a floating gate electrode 8 to be formed later and the substrate. It is. The second insulating film 11 can be formed by using, for example, a low-pressure CVD silicon oxide film.

Next, as shown in FIG. 4, an opening 12 is formed in a portion where a tunnel insulating film 7 is to be formed later by a known photoresist process and etching process.

Although the shape of the opening 12 is drawn vertically in FIG. 4, the opening 12 may have a slight inclination. In this case, the control gate electrode 10 is processed by an easier technique at a later time. The advantage of being possible exists.

Next, as shown in FIG. 5, impurity ions 13 are implanted into the source forming portion and the drain forming portion of the transistor by oblique ion implantation. The impurity is, for example, n
When forming a type transistor, arsenic, phosphorus, or the like can be used.

When it is desired to adjust the ion implantation location to obtain desired transistor characteristics, the ion implantation angle θ, the thickness of the second insulating film 11, or both are set to appropriate values. It can be carried out. However, it should be noted that the thickness of the second insulating film 11 affects the capacitance between the floating gate electrode 8 and the control gate electrode 10 as described later.

When ion implantation for adjusting the threshold value of the transistor is required, ion implantation can be performed in this state, and this is the best method for minimizing the number of steps. It is needless to say that the ion implantation is not necessarily performed obliquely, but may be performed in a vertical direction.

After the implantation of the impurity ions, it is necessary to activate or diffuse the impurity ions by performing a heat treatment. This step may be performed immediately after this step, or may be combined with a heat treatment step performed later. I do not care. The position of the step is arbitrary.

Next, as shown in FIG. 6, a tunnel insulating film 7 is formed. Generally, this tunnel insulating film 7 can be formed by thermally oxidizing or oxynitriding the substrate.

Next, as shown in FIG. 7, a conductive film 14 to be the floating gate electrode 8 is formed. As a material of the conductive film 14, for example, polycrystalline silicon by a CVD method can be used. The thickness of this film affects the capacitance between the floating gate electrode 8 and the control gate electrode 10. This effect will be described later.

Next, as shown in FIG. 8, a floating gate electrode 8 is formed by a known photoresist process and etching process. Floating gate electrode 8 and control gate electrode 1
In order to secure a larger capacity between 0 and 0, it is desirable to determine the pattern so as to have the largest area that can be processed.

Next, as shown in FIG. 9, a first insulating film between the floating gate electrode 8 and the control gate electrode 10 is formed.
An insulating film 9 is formed. As the first insulating film 9, a film having a small leakage current and a large dielectric constant is suitable. For example, a silicon oxide film, a silicon nitride film, or a laminated film thereof can be used. A silicon oxide film, a silicon nitride film, or a stacked film thereof can be formed by a known CVD method or the like.

Next, as shown in FIG. 10, a conductive film 15 to be the control gate electrode 10 is formed. In the conductive film 15,
For example, polycrystalline silicon or the like can be used.

Next, a control gate electrode 10 is formed by performing a photoresist step and an etching step. First, the conductive film 15 serving as the control gate electrode 10 is etched, and then the first insulating film 9 is etched.
Finally, the conductive film 14 to be the floating gate electrode 8 is etched. Thereby, the flash memory shown in FIG. 1 is almost completed.

According to such a method of manufacturing a flash memory, the opening 12 is formed in the second insulating film 11 formed on the main surface of the semiconductor substrate 1, and the opening 12 is formed in the vicinity of the opposite side of the bottom surface of the opening 12. Since the tunnel insulating film 7 is formed after the impurity semiconductor regions 4 and 5 serving as source / drain regions are provided, and then the single-layer or simple stacked floating gate electrode 8 is provided, the first layer Without forming a source / drain region after forming the floating gate electrode, forming a selective oxide film on the source / drain region, and forming a second-layer floating gate electrode. , Floating gate electrode 8 and control gate electrode 10
A floating gate electrode having a sufficiently large coupling capacitance with the floating gate electrode can be formed.

As a result, the formation of the floating gate electrode 8 can be simplified, the manufacturing process can be simplified, and the yield and reliability of the flash memory can be improved and the manufacturing cost can be reduced.

The formation of the impurity semiconductor regions 4 and 5 is as follows.
Since the etching is performed by the oblique ion implantation method using the opening 12 of the second insulating film 11 as a mask, it can be performed in a self-aligned manner without using a mask, and it is possible to easily cope with miniaturization.

In the oblique ion implantation, since the formation of the source region and the formation of the drain region are performed separately, the dose of each region can be controlled independently.
, The efficiency of charge injection into the floating gate electrode 8 and the measure against punch-through can be easily optimized.

Further, since the angle θ at which the impurity ions 13 are implanted is controlled by changing the installation angle of the semiconductor substrate 1, it is possible to optimize the positions where the impurity semiconductor regions 4 and 5 are formed.

Incidentally, a comparison between the number of steps required for manufacturing a conventional flash memory and the number of steps of the present invention is as follows.

In the prior art, a tunnel insulating film forming step, a first film forming step for a floating gate electrode film, a silicon nitride film forming step, a photoresist step for forming a first layer floating gate electrode, a first layer floating gate electrode Processing step, source part ion implantation photoresist step, source part ion implantation step, drain part ion implantation photoresist step, drain part ion implantation step, insulating film deposition step,
Insulating film etch back process, selective oxidation ion implantation process, selective oxidation, silicon nitride film removing process, floating gate electrode film second layer forming process, second layer floating gate electrode forming photoresist process, second layer floating Twenty-one steps are required: a gate electrode processing step, a capacitor insulating film forming step, a control gate electrode film forming step, a control gate electrode forming photoresist step, and a control gate electrode processing step.

On the other hand, in the case of the embodiment of the present invention, for example, an insulating film forming step, an insulating film opening photoresist step, an insulating film opening processing step, an oblique ion implantation step, a tunnel insulating film forming Process, floating gate electrode film formation process, floating gate electrode formation photoresist process, floating gate electrode processing process, capacitance insulating film formation process, control gate electrode film formation process, control gate electrode formation photoresist process , A control gate electrode processing step.

Accordingly, in the manufacture of the flash memory according to the present embodiment, there is an effect that the number of steps can be greatly reduced as compared with the prior art.

Referring to FIG. 11, the dimensions (r) of opening 12, the thickness (h) of second insulating film 11, the thickness (t) of control gate electrode 10, and the processing dimensions of control gate electrode 10 ( The relationship between each value of L) and the capacitance (C) between the floating gate electrode 8 and the control gate electrode 10 will be described. Since the capacitance (C) is proportional to the area between the floating gate electrode 8 and the control gate electrode 10, the following equation holds.

(1) In the case of t <r / 2 C∝2t + L + 2h (2) In the case of t> = r / 2 C∝2t + L Therefore, in order to secure the capacity (C) as much as possible while suppressing the machining step (1) It is understood that each value should be determined so as to satisfy the condition of ()).

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above-described embodiment, an example has been described in which impurity semiconductor regions 4 and 5 are formed by oblique ion implantation. However, as shown in FIGS. The ion implantation may be performed by masking, and the ion implantation may be similarly performed by masking with the photoresist 16 of the other impurity semiconductor region to form the impurity semiconductor regions 4 and 5 independently.

In such a case, the implantation of the impurity ions 13 is not limited to being performed obliquely as shown in FIG. Therefore, other conditions can be set without being restricted by the condition of the incident angle of the impurity ions.

[0080]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In manufacturing a semiconductor integrated circuit device having nonvolatile memory cells, not only the number of steps is reduced and the manufacturing cost is reduced, but also the product yield is improved and the performance of the semiconductor integrated circuit device is further improved. Can be improved.

(2) A structure that does not require the floating gate electrode to have a two-layer structure and that can ensure the capacitance between the floating gate electrode and the control gate electrode can be simply realized.

(3) A semiconductor integrated circuit device having a nonvolatile memory cell with a simple structure can be easily formed with a small number of steps.

(4) Different impurity concentration distributions can be easily obtained in the source region and the drain region of the transistor constituting the nonvolatile memory cell.

[Brief description of the drawings]

FIG. 1A is a top view showing an example of a flash memory according to an embodiment of the present invention and a memory cell region thereof, and FIGS. 1B and 1C are each a view in FIG. It is sectional drawing which followed the bb line and the cc line.

FIG. 2 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention with respect to a memory cell region.

FIG. 3 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention with respect to a memory cell region.

FIG. 4 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention with respect to a memory cell region.

FIG. 5 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention with respect to a memory cell region thereof.

FIG. 6 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention for a memory cell region.

FIG. 7 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention with respect to a memory cell region.

FIG. 8 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention with respect to a memory cell region thereof.

FIG. 9 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention with respect to a memory cell region.

FIG. 10 is a cross-sectional view showing an example of a manufacturing process of a flash memory according to an embodiment of the present invention for a memory cell region thereof.

FIG. 11 is a cross-sectional view showing an example of a flash memory according to an embodiment of the present invention with respect to a memory cell region.

FIG. 12 is a cross-sectional view showing another example of the manufacturing process of the flash memory according to the embodiment of the present invention with respect to a memory cell region;

FIG. 13 is a cross-sectional view showing another example of the manufacturing process of the flash memory according to the embodiment of the present invention with respect to a memory cell region.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field insulating film 3 active region 4 impurity semiconductor region 5 impurity semiconductor region 6 channel region 7 tunnel insulating film 8 floating gate electrode 9 first insulating film 10 control gate electrode 11 second insulating film 12 opening 13 impurity ions 14 conductivity Film 15 conductive film 16 photoresist θ angle

Claims (7)

[Claims] An element isolation region formed on a main surface of a semiconductor substrate and an active region surrounded by the element isolation region; a source region and a drain region formed near the main surface of the active region; A tunnel insulating film formed on a channel region located between the source region and the drain region; a floating gate electrode formed on the tunnel insulating film; and a first insulating film on the floating gate electrode. A semiconductor integrated circuit device having a non-volatile memory cell including a control gate electrode formed therethrough, wherein the tunnel insulating film has an opening in a second insulating film formed on a main surface of the semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film and the second insulating film, and has a single-layer film or a substantially uniform film thickness. The semiconductor integrated circuit device, characterized in that a laminated film is intended to be configured to have. 2. The semiconductor integrated circuit device according to claim 1, wherein the channel region is formed in a central region of the opening, and the source region and the drain region are formed in end regions of the opening. And a semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the width of the opening is at least twice the thickness of the floating gate electrode. 4. The semiconductor integrated circuit device according to claim 1, wherein the source region or the drain region of the plurality of nonvolatile memory cells is shared as a single source region or a drain region. Thereby, the nonvolatile memory cells have an AND-type memory cell block structure in which the nonvolatile memory cells are connected in parallel, and information stored in the nonvolatile memory cells is electrically erased collectively. Semiconductor integrated circuit device. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein: (a) forming an element isolation region on a main surface of the semiconductor substrate;
Forming the second insulating film over the entire surface of the semiconductor substrate; (b) a region to be the channel region of the nonvolatile memory cell, and a region between the adjacent nonvolatile memory cells sandwiched between the regions. Forming an opening in the second insulating film by selectively removing the region, and (c) forming one impurity semiconductor region serving as a source region or a drain region near one end of the bottom surface of the opening. Forming another impurity semiconductor region serving as a source region or a drain region in the vicinity of the other end of the bottom of the opening opposite to the one end; (d) tunneling to the main surface of the semiconductor substrate at the bottom of the opening Forming an insulating film; (e) depositing a single-layer or laminated first conductive film on the entire surface of the semiconductor substrate and patterning the first conductive film to form the second conductive film including the opening. Excellence A step of forming a first conductive film pattern in the preceding stage to be the floating gate electrode on the surface of the edge film; (f) forming the first insulating film on the entire surface of the semiconductor substrate on which the first conductive film pattern is formed An insulating film and a second conductive film serving as the control gate electrode are sequentially deposited;
(G) patterning the insulating film to be the first insulating film to form the control gate electrode, and (g) patterning the first conductive film pattern to form a floating gate electrode. A method for manufacturing a semiconductor integrated circuit device, comprising: 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein in the impurity semiconductor region in the step (c), the semiconductor substrate is disposed obliquely with respect to an ion incident direction. 2. A method of manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is formed by an oblique ion implantation method formed in a self-aligned manner using an opening of the second insulating film as a mask. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein in the impurity semiconductor region in the step (c), the channel region and the other end are masked with a photoresist. A first ion implantation step of performing ion implantation in the vicinity of one of the edges and a second ion implantation step of performing ion implantation in the vicinity of the other edge while masking the channel region and the one edge with a photoresist. A method of manufacturing a semiconductor integrated circuit device, wherein the method is performed through the following steps.