KR100309139B1 - Method for fabricating non-volatile memory device - Google Patents

Abstract

PURPOSE: A method for fabricating a non-volatile memory(NVM) device is provided to reduce resistance of a control gate and improve a coupling ratio between the control gate and a floating gate by connecting control gates of adjacent cells sharing a bit line in the entire memory cell array except a bit line contact part while using one wire. CONSTITUTION: After an active region(A) and an inactive region(B) are defined in a silicon substrate, a field oxide layer is grown. A tunnel oxide layer and the first polysilicon layer are formed. The first polysilicon layer is patterned through an etch process. A drain and a drain connecting diffusion layer are simultaneously formed to form a bit line(C) through an impurity ion implantation process. An interlayer dielectric and the second polysilicon layer are formed. The first polysilicon layer and the second polysilicon layer are etched to form a control gate through a self-align etch process wherein the control gate is formed as a common control gate in an adjacent cell sharing the bit line. A source line is formed through an impurity ion implantation process. A select transistor is formed through a conventional process.

Description

Non-volatile memory device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a control gate of an adjacent cell sharing a drain bit line in a memory cell fabrication having electrical and program characteristics. The resistance of the control gate is reduced by connecting one line across the entire memory cell array except for the bit line contacts, and the drain bit line forms a diffusion layer for drain connection at the same time as the drain of each unit cell is formed. In addition to increasing reliability, non-volatile memories can improve device performance and yield by improving the program and erase characteristics of the device by increasing the coupling ratio between the floating gate and the control gate by utilizing the side of the floating gate. It relates to a method for manufacturing a device.

In the non-volatile memory device, there are electrically programmed and erased characteristics such as EPROM, EEPROM, and Flash EEPROM. In general, a buried diffusion layer (Buried n ⁺ Layer: BN ⁺ layer) is mainly used to form a bit line.

Since the buried diffusion layer forming step is formed before the field oxide and tunnel oxide growth process steps, the characteristics of the tunnel oxide film having a great influence on the reliability and yield of the device are deteriorated, and the buried diffusion layer is a high temperature thermal process like the field oxide growth process. As a result, side diffusion occurs, causing a punch through.

FIG. 1 is a layout diagram of a conventional nonvolatile memory device, and FIGS. 1A and 1B are cross-sectional views of devices cut along the lines XX 'and Y-Y' of FIG. 1, with reference to these drawings. The method and the problem are described as follows.

After forming a well in the silicon substrate 1, the active region A and the inactive region B are determined, and a predetermined portion of the bit line region C is subjected to BN ⁺ mask and BN ⁺ ion implantation process. ^{After the} diffusion layer 2 is formed, the field oxide film 3 is formed in the inactive region B through a high temperature oxidation process. At this time, the BN ⁺ diffusion layer 2 under the field oxide film 3 is laterally diffused to cause punch through (when the cell area is not large enough). Thereafter, the tunnel oxide film 4 is grown, and this tunnel oxide film 4 is formed after the formation of the BN ⁺ diffusion layer 2, thereby causing a problem in that its characteristics become poor.

After the tunnel oxide layer 4 is formed, the floating gate 5 is formed in the floating gate region D, and the interlayer insulating layer 6 is formed thereon, and each unit is arranged with the bit line region C interposed therebetween. The control gate 7 is formed in the control gate region E that overlaps the floating gate 5 of the cell.

After the process step, a source / drain mask and a source 9 of each unit cell are formed by a source / drain mask and an N + ion implantation process. The non-volatile memory device is manufactured by forming a gate.

In the above, the control gate 7 becomes a main bit line to which a high voltage equal to or higher than an operating voltage is applied during programming and erasing, and the train bit line C consists of a drain 9 and a BN ⁺ diffusion layer 2. Line F is made at the time of forming the source 8 of each unit cell.

As mentioned above, although the conventional technology has various problems, the reason for using the BN ⁺ layer is that the self-alignment for forming the floating gate and the control gate when forming the bit line as the active region is required. Not only does it have a problem that it is difficult to overcome the damage of the exposed silicon substrate during the self align etching, but even if the minimum width of the floating gate is further reduced, the device characteristics are not adversely affected. The disadvantage is that it cannot be reduced below the minimum feature size. In addition, most of the conventional methods for manufacturing a cell of a nonvolatile memory device are coupled by a planar capacitor using an insulating layer between the lower end of the control gate and the upper end of the floating gate, thereby lowering the efficiency of voltage induction of the floating gate by the control gate.

Accordingly, the present invention achieves a three-dimensional structure that enables not only the use of planar capacitors but also the capacitors on the side of the floating gate, thereby enabling a coupling ratio of 20% to 50% higher than the conventional coupling method, and substrate damage occurs. Protects the part with a polysilicon layer for the control gate, enabling the formation of bit lines by the active region, eliminating the use of a BN ⁺ layer that degrades device characteristics, and reducing the width of the floating gate below the minimum possible line width of the exposure apparatus. It is an object of the present invention to provide a method of manufacturing a nonvolatile memory device that can be arbitrarily formed in size.

In order to achieve the above object, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention may include forming a tunnel oxide film and a first polysilicon layer after determining an active region and an inactive region on a silicon substrate, and forming a tunnel oxide layer and an etching process. Patterning the first polysilicon layer, forming a bit line by simultaneously forming a drain and drain connection diffusion layer by an impurity ion implantation process, and forming an interlayer insulating layer and a second polysilicon layer and then self-aligning Forming a control gate by etching the first polysilicon layer and the second polysilicon layer by an etching process, and forming the control gate as a common control gate in an adjacent cell sharing the bit line; Forming a source line, and forming a select transistor in a conventional process Characterized in that consists of.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2, 3, and 4 are layout views showing process steps according to the present invention, and FIGS. 2A and 2B are cross-sectional views of devices cut along lines XX 'and Y-Y' of FIG. 2, and FIGS. Sectional drawing of the element cut along the XX 'and Y-Y' line | wire of FIG. 3, and FIG. 4A and 4B are sectional drawing of the element cut along the line XX 'and Y-Y' of FIG.

After the wells are formed in the second and the second or second silicon substrates 11, the portions of the transistors to be the channel G, the bit line C and the source line F become active regions A. Shows a state in which a portion of is defined as an inactive region B to form a field oxide film (not shown).

After the tunnel oxide film 12 is grown in the third, third and third active regions A, the first polysilicon layer 13 is deposited to a predetermined thickness on the entire structure, and the photoresist film 14 is deposited on the entire structure. After coating, the photosensitive film 14 is patterned to sufficiently cover the remaining active region A except for the bit line region C, and the first polysilicon is etched using the patterned photosensitive film 14 as an etch barrier layer. After the layer 13 is first etched, an impurity ion implantation process forms a drain 15 of each unit cell and a drain connection diffusion layer 15A connecting the drains 15 to form a bit line of the device. The state which formed (C) is shown.

4, 4A, and 4B, the interlayer insulating film 16 is formed after removing the photosensitive film 14, and the second polysilicon layer 17 is deposited to a predetermined thickness on the entire structure, and then the second layer is subjected to a self-aligned etching process. The polysilicon layer 17 and the first etched first polysilicon layer 13 are etched to form the control gate 17 in the floating gate 13 and the control gate region E in the floating gate region D. The state is shown.

The interlayer insulating layer 16 may be formed in an oxide-nitride-oxide (ONO) structure. After depositing the first polysilicon layer 13, a lower oxide layer and a nitride layer are formed, and then before the second polysilicon layer 17 is deposited. An upper oxide layer may be formed to form the interlayer insulating layer 16.

The control gate 17 is formed to be a common control gate in an adjacent cell sharing the bit line (C). That is, the control gate 17 of the adjacent cell sharing the bit line C is formed to be connected by one line over the entire memory cell array except for the bit line contact portion (not shown).

Subsequently, a mask operation is performed to open the source line region F and a source 18 of each unit cell is formed by an impurity ion implantation process, and a source connection diffusion layer connecting the sources 18 is formed and selected. A gate oxide film and a select gate are formed to manufacture the nonvolatile memory device of the present invention.

As can be seen by comparing FIGS. 1A and 4A, in the present invention, not only the upper end of the floating gate 13 but also one side wall is sufficiently covered by the control gate 17 in the present invention, between the interlayers. Since the insulating film 16 is present, the capacitance between the two layers has a larger value than that of the conventional method, thereby enabling an increase in program and erase efficiency. Here, the control gate completely covers the bit line, which is a structure in which two adjacent control gates sharing one bit line are connected as compared with a conventional cell, but these are logically identical lines (common control gates) during cell operation. As it is recognized, it does not matter. When the second polysilicon layer for the control gate is etched through a photo process, a self-aligned etching process in which the first polysilicon layer for etching the floating gate is etched at the same time is performed. The bit line is a control gate (second polysilicon). Layer) can be sufficiently protected from substrate damage. In addition, although the minimum width of the floating gate formed of the first polysilicon layer is conventionally determined by the minimum possible line width of the exposure apparatus, in the present invention, one side of the floating gate is first-etched of the first polysilicon (floating gate). Defining at the time and determining the other side by self-aligned etching enables the formation of a floating gate having a size smaller than the minimum possible line width of the exposure apparatus.

In addition, since the drain formation of each unit cell is formed independently unlike conventionally formed at the same time as the source, it is possible to more easily optimize the erase characteristics which are greatly influenced by the drain structure.

Moreover, in the conventional method, since the drains for each cell cannot be connected in a layout, bit lines are formed using the BN ⁺ layer. However, in the present invention, a drain connection diffusion layer connecting the drains at the same time as the drains for the individual cells is formed. Not only can a bit line be formed at a time, but also a natural mask layer is formed for the photolithography process of the first polysilicon layer and the implantation of the drain impurity by the field oxide film. Simplify

Hereinafter, the operation of the nonvolatile memory cell will be described with reference to FIGS. 4, 4 (a) and 4 (b) of the present invention.

In FIG. 4A, the channel is formed on the surface of the semiconductor substrate 11 between the source line 15 and the bit line 18 (hereinafter, referred to as a 'channel region'). Although not shown in the drawings, a select gate oxide film and a select gate for the select transistor are sequentially formed on the channel region where the floating gate 13 is not formed. The process of forming the select gate oxide film and the select gate is generally made of a conventional process known in the art. By forming the select transistor, a region where the select gate is formed in the upper portion of the channel region becomes a channel region of the select transistor, and a channel is formed according to a bias applied to the select gate. In addition, in the region where the floating gate 13 is formed in the upper portion of the channel region, the channel is formed by the bias applied to the control gate 17, and at the same time, the charge flows in or out (program / erase) to the floating gate 13. . At this time, the bias is applied to the control gate 17 does not necessarily program / erase operation. In order to perform the program / erase operation, a channel must be formed between the bit line C and the source line F to be electrically connected. In order to form channels in the bit lines C and the source lines F, not only a bias is applied to the control gate 17 but also a bias is also applied to the select gate of the select transistor to form a channel under the select transistor. do. When a bias is applied to the select gate and a bias is applied to the control gate 17 to form a channel over the entire channel region, the bit line C and the source line F are electrically connected, and in this state, the bit line is electrically connected. When a predetermined bias is applied to (C), electrons move, and electric charges flow into the floating gate 13 due to the electric field effect, and the cell is programmed.

In other words, in order to perform a program / erase operation of a memory cell including the floating gate 13, the interlayer insulating layer 16, and the control gate 17, a bias is applied to the control gate 17 and the bit line C. A bias must be applied to the select gate to form a channel.

In the above-described process of the present invention, the drain 15 is connected by the drain connection diffusion layer 15A to form the bit line region C, and the control gate 17 of the memory cell sharing the bit line region C. ) Are also connected to each other to form the control gate region (E). Therefore, unlike the conventional cell structure, when a bias is applied to the control gate 17, the bias is applied to the control gate 17 of all the memory cells included in the control gate region E. FIG.

In general, when a predetermined voltage is applied to the control gate and the bit line in the memory cell, the memory cell operates. However, in the present invention, the memory cell does not operate unless the channel is formed using the select transistor. One such select transistor is configured for each memory cell, and a desired memory cell may be selected using the select transistor. Therefore, even when the drain and the control gate are connected to each other, since only one memory cell is selected using the select transistor, the circuit operates normally without any problem.

Effects of the present invention based on the above can improve the reliability and yield of the device due to the removal of the BN + layer, it is possible to improve the characteristics of the device according to the reduction of the resistance of the control gate (second polysilicon layer), process Simplified production cost and increased net die number due to reduced cell area. Also, differentiation of in-source process allows easy optimization of program / erase characteristics. The device characteristics can be greatly improved by improving the program and erase characteristics according to the increase of.

1 is a layout diagram of a conventional nonvolatile memory device.

Sectional drawing of the element cut | disconnected along the X-X 'and Y-Y' line | wire of FIG. 1A and 1B.

2, 3, and 4 are layout views showing process steps according to the present invention.

Sectional drawing of the element cut | disconnected along the X-X 'and Y-Y' line | wire of FIG. 2A and 2B or FIG.

3A and 3B are cross-sectional views of the element taken along lines X-X 'and Y-Y' of FIG.

4A and 4B are cross-sectional views of the element taken along lines X-X 'and Y-Y' of FIG.

Explanation of symbols on the main parts of the drawings

11: silicon substrate 12: tunnel oxide film

13: first polysilicon (floating gate)

14 photosensitive film 15 drain

15A: Diffusion layer 16: Interlayer insulating film for drain connection

17: second polysilicon (control gate)

18: source

A: active zone B: inactive zone

C: bit line D: floating gate region

E: control gate region F: source line region

G: channel area

Claims (9)

Forming an active region and an inactive region on the silicon substrate and growing a field oxide film, forming a tunnel oxide film and a first polysilicon layer; Patterning the first polysilicon layer by an etching process; Forming a bit line by simultaneously forming a diffusion layer for drain and drain connection by an impurity ion implantation process; After the interlayer insulating layer and the second polysilicon layer are formed, a control gate is formed by etching the first polysilicon layer and the second polysilicon layer by a self-aligned etching process, wherein the control gate shares an adjacent cell with the bit line. Forming a common control gate in, Forming a source line by an impurity ion implantation process, A method of manufacturing a nonvolatile memory device, comprising forming a select transistor in a conventional process. The method of claim 1, And the active region is defined as a portion to be a channel, a drain bit line, and a source line of the transistor. The method of claim 1, And the control gate is formed as one line across the entire memory cell array except for the bit line contact portion. The method of claim 1, The first polysilicon layer is non-volatile, characterized in that one side of the first etching process to open the bit line region, and the other side is determined through a self-aligned etching process to form a floating gate of the device Memory device manufacturing method. The method of claim 4, wherein And the line width of the floating gate is determined by a self-aligned etching process performed after the patterning process of the first polysilicon layer. The method of claim 1, The active region exposed by the patterning process of the first polysilicon layer is prevented from damaging the self-aligned etching process by the second polysilicon layer. The method of claim 1. And a drain side surface of the first polysilicon layer formed by the patterning process of the first polysilicon layer is covered with the second polysilicon layer. The method of claim 7. A method of manufacturing a nonvolatile memory device, characterized in that an interlayer insulating film is formed between the first polysilicon layer and the second polysilicon layer. The method of claim 1. And forming a bit line independently of the source line without an additional photo process by an ion implantation process followed by an active region exposed by the patterning process of the first polysilicon layer.