KR100485502B1 - Nonvolatile memory device and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to a nonvolatile memory device and a method of manufacturing the same. In particular, the method of manufacturing the present invention includes forming a first insulating thin film and a first conductive film pattern on a semiconductor substrate and forming a common source of a cell transistor in the substrate; And sequentially stacking the second insulating thin film and the second conductive film on the entire surface of the resultant, patterning the stacked second conductive film to the first insulating thin film to form a multi-layer gate electrode of the selection transistor, and having a common source therebetween. Forming a cell transistor having two floating gates of the first conductive film pattern and a single control gate covering the floating gates and in contact with a common source; forming a drain and a source in a substrate between the cell transistor and the selection transistor And masking the cell transistor region to form a second conductive film and a first transistor of the selection transistor. 2 removing the insulating thin film. Therefore, the present invention can prevent malfunction on the device through the selection transistor by adding one selection transistor to the cell transistor and integrating two adjacent cell transistors into two separate floating gates having a common source and a single control gate. A pair of cell transistors can integrate the size of the effective cell.

Description

NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to malfunction of a memory by arranging one-select transistors and two-cell transistors in which a selection transistor is added to cells of a simple stacked structure of a flash memory device. The present invention relates to a technology capable of reducing the area on a cell array while preventing the damage.

In general, non-volatile memory has the advantage that the stored data is not lost even if the power is interrupted, so it is widely used for data storage of PC Bios, set-top box, printer, and network server. It is used a lot.

Among such nonvolatile memories, an electrically erasable programmable read-only memory (EEPROM) type flash memory device that has a function of electrically erasing data of memory cells in a batch or sector-by-sector is a channel column electronic device on a drain side during programming. The threshold voltage of the cell transistor is increased by forming hot electrons to accumulate electrons in the floating gate. On the other hand, the erase operation of the flash memory device lowers the threshold voltage of the cell transistor by generating a high voltage between the source / substrate and the floating gate to release electrons accumulated in the floating gate.

A typical cell structure of an EEPROM type flash memory device is classified into an ETOX cell having a simple stack structure and a split gate type cell composed of two transistors per cell. The ETOX cell structure is a structure in which a floating gate constituting a gate and a control gate to which a driving power is applied are stacked, whereas the split gate cell structure includes a selection transistor and a cell transistor 2. Using a dog with one control gate, a portion of the control gate overlaps the floating gate and another portion of the control gate is disposed horizontally on the substrate surface.

1 is a vertical cross-sectional view showing an ETOX cell structure of a conventional nonvolatile memory device.

Referring to FIG. 1, the conventional ETOX cell transistor has a structure as follows. A tunnel oxide 12, a floating gate 14, an inter-gate insulating film 16, and a control gate 18 that are sequentially stacked thereon are formed on an active region of the semiconductor substrate 10. The source / drain 20 spaced apart from each other with a channel region under the floating gate 14 in the semiconductor substrate 10 is formed therebetween.

The flash memory device having the ETOX cell structure applies a programming voltage through a word line connected to the control gate 18 and a bit line connected to the drain 20 during programming. Then, the electrons of the drain 20 are injected into the floating gate 14 through the tunnel oxide layer 12 in a hot carrier manner to perform a program of the cell transistor. On the other hand, during data erasing, an erase voltage is applied through a source line connected to the source 20. Then, the electrons injected into the floating gate 14 are again emitted to the channel through the tunnel oxide layer 12, and the erase is performed by lowering the threshold voltage of the cell transistor.

Although the ETOX cell of flash memory, which is such a simple stacked structure, can realize a small cell size, the effective cell size is increased because a drain contact must be formed along the bit line. There is a problem in that it is necessary to control the possibility of malfunction and to adjust the phenomenon of interference during programming.

2 is a vertical cross-sectional view illustrating a split cell structure of a conventional nonvolatile memory device. Referring to FIG. 2, a cell of a flash memory device having a channel split split gate structure has the following structure.

Between the tunnel oxide film 32 formed on the semiconductor substrate 30, the floating gate 34 formed on the tunnel oxide film 32, and the gate formed to overlap on the semiconductor substrate 30 including the floating gate 34. An insulating film 36, a control gate 38 formed over the inter-gate insulating film 36, and a semiconductor substrate 30 below one side of the control gate 38 and one side of the floating gate 34, respectively. It consists of a source / drain 40.

The programming and erasing operations of the split gate type flash memory device configured as described above are the same as the above-described ETOX structure, and thus the description thereof will be omitted.

The cell of the conventional split gate type flash memory device as described above has a structure in which a select transistor without a floating gate and a cell transistor overlapping a floating gate and a control gate are integrated. The addition of a select transistor per cell makes the unit cell size somewhat larger, but has the following advantages in terms of devices. That is, even if the cell transistor is over-erased due to the use of the select transistor, the cell transistor is turned off by the select transistor, thereby preventing cell malfunction due to the over-erasing. Since the program does not occur, program disturb can be prevented.

However, in the conventional split gate type flash memory device, the control gate needs to be patterned so as to overlap both the floating gate and the substrate. At this time, the floating gate is excessively etched, thereby deteriorating the electrical characteristics of the cell.

An object of the present invention is to add one select transistor to a cell transistor and to float two adjacent cell transistors having a common source, a single control gate, and two separate floating circuits to solve a problem that may occur in a conventional ETOX structure flash memory cell. The present invention provides a nonvolatile memory device capable of preventing malfunctions on a device through selection transistors and integrating effective cell sizes with a pair of cell transistors.

Another object of the present invention is to provide a method of manufacturing a nonvolatile memory device for forming a cell composed of one selection transistor and a pair of cell transistors.

In order to achieve the above object, the present invention provides a cell array of a nonvolatile memory device, comprising: a selection transistor comprising a gate, a source, and a drain, a word line for applying driving power to the cell, and a bit line for applying data information to the cell And a single control gate connected to the source of the selection transistor, a bit line connected to the drain, a word line connected to the word line, two floating gates separated under the control gate, and two separated floating gates. A pair of cell transistors composed of a common source formed therebetween is provided.

In accordance with another aspect of the present invention, there is provided a cell manufacturing method of a nonvolatile memory device, wherein the first insulating film and the first conductive film are sequentially stacked on a semiconductor substrate, and the first conductive film and the first insulating thin film are exposed. Patterning and forming a common source of the cell transistor in the substrate, sequentially laminating the second insulating thin film and the second conductive film on the entire surface of the resultant, and etching by using the cell selection transistor and the gate mask of the cell transistor. Patterning the second conductive film to the first insulating thin film to form a multi-layered gate electrode of the selection transistor, and at the same time, covering the two floating gates and the floating gate formed of the first conductive film pattern with a common source therebetween, Forming a cell transistor having a single control gate in contact with the cell transistor; And a rotor and forming a drain and a source in the substrate between the select transistors, the method comprising: masking a cell transistor region, and removing the second conductive film and the second insulating film of the selection transistor.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a cell layout diagram of a nonvolatile memory device according to the present invention. Referring to FIG. 3, a cell array of a flash memory device of the present invention may include a select transistor 200, a word line W / L, a bit line B / L, a source line S / L, It consists of a pair of cell transistors 300. Here, the select transistor 200 is composed of a gate, a source, and a drain, similar to a general MOS transistor, whereas the cell transistor 300 proposed by the present invention has a drain connected to a source of the select transistor 300. A bit line (B / L) is connected to the drain, and is formed between a single control gate connected to the word line (W / L), two floating gates separated under the control gate, and two separate floating gates. The line S / L includes a common source to which it is connected.

The cell of the flash memory device of the present invention performs a programming or erasing operation as follows.

During programming, when the select transistor 200 to be programmed is driven and a driving voltage is supplied to the word line W / L, the cell transistor 300 connected to the select transistor 200 is activated. At the same time, the voltage of the word line W / L is applied to the single control gate and the programming voltage supplied through the bit line B / L is transferred to the drain of the cell transistor 300. Electrons in the drain are injected into the floating gate through the tunnel oxide film, and the corresponding cell transistors are programmed.

When the select transistor 200 is driven and the driving voltage is supplied to the word line W / L during erasing, the cell transistor 300 connected to the select transistor 200 is activated. At the same time, the voltage of the word line W / L is applied to the single control gate, and the erase voltage supplied through the source line S / L is transferred to the common source of the cell transistor 300. Then, the electrons injected into the floating gate exit the channel through the tunnel oxide layer and the data of the cell transistor is erased.

4 is a vertical cross-sectional view illustrating a cell structure of a nonvolatile memory device according to the present invention. Referring to FIG. 4, in the flash memory cell of the present invention, a select transistor 200 having a single-layer gate 104a and a source and a drain 112 is formed on the semiconductor substrate 100 like a general MOS transistor. In the semiconductor substrate 100, a pair of cell transistors 300 shared with the drain or the source 112 of the selection transistor 200 and having two channels are also formed.

In the pair of cell transistors 300 of the present invention, a common source 106 is formed on a substrate 100, and tunnel oxide films 102b and floating gates 104b are stacked on both substrates of the common source 106, respectively. The inter-gate insulating film 108b is formed on the separated floating gate 104b and the tunnel oxide film 102b and the common source 106 surface, and the floating gate 104b is disposed on the inter-gate insulating film 108b. And a single control gate 110b is formed which is aligned with both ends of each floating gate 104b.

Thus, the present invention includes a pair of cell transistors 300 and select transistors 200 for driving each of these cell transistors 300, wherein the pair of cell transistors 300 is a common source 106 and a single control. Since two channels are formed in two floating gates 104b formed by the gate 110b and separated from each other, the size of the entire cell array can be integrated.

5A to 5F are flowcharts illustrating a method of manufacturing a cell of a nonvolatile memory device according to the present invention, and the manufacturing process of the present invention will be described with reference to them.

First, as shown in FIG. 5A, an oxide film as the first insulating thin film 102 is formed on a silicon substrate as the semiconductor substrate 100, and a doped polysilicon film or a metal film is deposited thereon as the first conductive film 104. do. In this case, the first insulating thin film 102 is used as a tunnel oxide of a cell, and the first conductive film 104 is then used as a gate of a selection transistor and a floating gate of a cell transistor.

The substrate surface is exposed by patterning the stacked first conductive film 104 and the first insulating thin film 102 by performing a photo process and an etching process using a common source mask of the cell transistor. A source dopant, eg, an n + ion implantation process, is then performed to form a common source 106 of cell transistors in the substrate 100.

As shown in FIG. 5B, the second insulating thin film 108 and the second conductive film 110 are sequentially stacked on the entire surface of the resultant in which the common source 106 is formed. At this time, the second insulating thin film 108 is made of any one of an oxide film, a nitride film, and a high dielectric film to be used as the inter-gate insulating film of the cell transistor. For example, the second insulating thin film 108 may use oxide Nitride Oxide (ONO) or a high dielectric material Ta2O5 in which an oxide film, a nitride film, and an oxide film are sequentially stacked. The second conductive film 110 is used as a single control gate of the cell transistor, and a doped polysilicon film or a metal film is used as the material.

Subsequently, as shown in FIG. 5C, a photo transistor and a photolithography process using a cell selection transistor and a cell transistor gate mask are performed to pattern the stacked second conductive film 110 to the first insulating thin film 102 to select a selection transistor ( The multilayer gate electrodes 110a, 108a, 104a of the 200 are formed. At the same time, two floating gates 104b formed of the first conductive film pattern with the common source 106 interposed therebetween, an inter-gate insulating film 108b surrounding the floating gate 104b and contacting the common source 106, The cell transistor 300 having a single control gate 110b formed over the inter-gate insulating film 108b is completed.

Then, as shown in FIG. 5D, dopant ion implantation, for example, an n + ion implantation process, is performed to drain and source 112 into substrate 100 between cell transistor 300 and select transistor 200. Form.

Subsequently, as shown in FIGS. 5E and 5F, the cell transistor region is masked with the photoresist pattern 114, and the second conductive film 110a and the second insulating thin film 108a of the selection transistor 200 are removed. The selection transistor 200 is formed in a MOS transistor structure having a single layer gate electrode. Then, the photoresist pattern 114 is removed.

Although not shown in the drawings, an interlayer insulating film is formed on the entire surface of the entire product and then contact and wiring processes are performed to fabricate word lines and bit lines connected to the cell transistors or the selection transistors, thereby completing the cell array of the present invention.

As described above, the present invention eliminates malfunction on the device through the selection transistor by adding one selection transistor to the cell transistor and integrating two adjacent cell transistors into two separate floating gates having a common source and a single control gate. There is an advantage in that the effective cell size can be integrated with a pair of cell transistors.

In addition, the present invention can protect the lower floating gate from the etching process by self-aligning a single control gate over two separate floating gates in the process of manufacturing a pair of cell transistors, thereby simplifying the overall process. .

On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.

1 is a vertical cross-sectional view showing an ETOX cell structure of a conventional nonvolatile memory device;

2 is a vertical sectional view showing a split cell structure of a nonvolatile memory device according to the prior art;

3 is a cell layout diagram of a nonvolatile memory device according to the present invention;

4 is a vertical sectional view showing a cell structure of a nonvolatile memory device according to the present invention;

5A to 5F are flowcharts illustrating a cell manufacturing method of a nonvolatile memory device according to the present invention.

Claims (5)

In a cell array of a nonvolatile memory device, A selection transistor consisting of a gate, a source, and a drain; A word line for applying driving power to the cell; A bit line for applying data information to the cell; And A drain of one cell is connected to a source of the select transistor, and the bit line is connected to the drain, and a single control gate is connected to the word line, two floating gates separated under the control gate, and the separated A nonvolatile memory device comprising a pair of cell transistors composed of a common source formed between two floating gates. In the cell manufacturing method of a nonvolatile memory device, Sequentially stacking a first insulating film and a first conductive film on a semiconductor substrate, patterning the first conductive film and the first insulating thin film to expose the substrate surface, and forming a common source of a cell transistor in the substrate; Sequentially stacking a second insulating thin film and a second conductive film on the entire surface of the resultant product; In the etching process using the select transistor of the cell and the gate mask of the cell transistor, the multilayered second conductive film to the first insulating thin film are patterned to form a multi-layer gate electrode of the select transistor, and the common source is interposed therebetween. Forming a cell transistor having two floating gates formed of a first conductive film pattern and a single control gate covering the floating gate and in contact with the common source; Forming a drain and a source in the substrate between the cell transistor and the selection transistor; And Masking the cell transistor region and removing a second conductive film and a second insulating thin film of the selection transistor. The method of claim 2, wherein the first insulating thin film is an oxide film. The method of claim 2, wherein the second insulating thin film is one of an oxide film, a nitride film, and a high dielectric film. The method of claim 2, wherein the first and second conductive films are a doped polysilicon film or a metal film.