KR0150047B1 - Manufacturing method of non-volatile memory devices - Google Patents
Manufacturing method of non-volatile memory devicesInfo
- Publication number
- KR0150047B1 KR0150047B1 KR1019940022560A KR19940022560A KR0150047B1 KR 0150047 B1 KR0150047 B1 KR 0150047B1 KR 1019940022560 A KR1019940022560 A KR 1019940022560A KR 19940022560 A KR19940022560 A KR 19940022560A KR 0150047 B1 KR0150047 B1 KR 0150047B1
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- polysilicon layer
- bit line
- control gate
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 239000010410 layer Substances 0.000 claims description 64
- 238000000034 method Methods 0.000 claims description 38
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 35
- 229920005591 polysilicon Polymers 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 비휘발성 메모리 소자의 제조방법에 관한 것으로, 전기적으로 프로그램(Program) 및 소거(Erase) 특성을 갖는 메모리 셀 제조에서 비트라인(Bit Line)을 공유하는 인접 셀의 컨트롤 게이트를 비트라인 콘택부를 제외한 전체 메모리 셀 어레이(Array)에 걸쳐 하나의 선으로 연결하므로써 컨트롤 게이트의 저하를 줄이고, 비트라인은 각 단위 셀의 드레인을 형성할 때 동시에 드레인 연결용 확산층을 형성하므로써 소자의 신뢰성 및 수율을 향상시킬 수 있는 비휘발성 메모리 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device, wherein the control gate of a neighboring cell sharing a bit line is a bit line contact in a memory cell fabrication having electrically programmed and erased characteristics. One line across the entire memory cell array excluding negatives reduces control gate degradation, while the bit lines form a drain connection diffusion layer at the same time as draining each unit cell, thereby improving device reliability and yield. A method of manufacturing a nonvolatile memory device that can be improved.
Description
제1도는 종래 비휘발성 메모리 소자의 레이아웃도.1 is a layout diagram of a conventional nonvolatile memory device.
제1a, 1b 및 1c도는 제1도의 X-X', Y-Y' 및 X''-X'''선을 따라 절단한 소자의 단면도.1A, 1B, and 1C are cross-sectional views of elements cut along the lines X-X ', Y-Y', and X ''-X '' 'of FIG.
제2,3,4도는 본 발명에 따라 공정단계별로 도시한 레이아웃도.2, 3, and 4 are layout views showing process steps according to the present invention.
제2a 및 2b도는 제2도의 X-X' 및 Y-Y'선을 따라 절단한 소자의 단면도.2A and 2B are sectional views of the element taken along the lines X-X 'and Y-Y' of FIG.
제3a 및 3b도는 제3도의 X-X' 및 Y-Y'선을 따라 절단한 소자의 단면도.3A and 3B are sectional views of the element cut along the lines X-X 'and Y-Y' of FIG.
제4a 및 4b도는 제4도의 X-X' 및 Y-Y'선을 따라 절단한 소자의 단면도.4A and 4B are sectional views of the element cut along the lines X-X 'and Y-Y' of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 실리콘 기판 12 : 터널 산화막11 silicon substrate 12 tunnel oxide film
13 : 제 1 폴리실리콘(플로팅 게이트) 14 : 감광막13: 1st polysilicon (floating gate) 14: photosensitive film
15 : 드레인 15A : 드레인 연결용 확산층15 drain 15A diffusion layer for drain connection
16 : 층간 절연막 17 : 제 2 폴리실리콘(컨트롤 게이트)16: interlayer insulating film 17: second polysilicon (control gate)
18 : 소오스 A : 활성영역18: source A: active area
B : 비활성영역 C : 비트라인 영역B: Inactive area C: Bitline area
D : 플로팅 게이트 영역 E : 컨트롤 게이트 영역D: floating gate area E: control gate area
F : 소오스 라인 영역 G : 채널 영역F: source line region G: channel region
본 발명은 비휘발성 메모리 소자의 제조방법에 관한 것으로, 특히 전기적으로 프로그램(Program) 및 소거(Erase) 특성을 갖는 메모리 셀 제조에서 비트라인(Bit Line)을 공유하는 인접 셀의 컨트롤 게이트를 비트라인 콘택부를 제외한 전체메모리 셀 어레이(Array)에 걸쳐 하나의 선으로 연결하므로써 컨트롤 게이트의 저항을 줄이고, 비트라인은 각 단위 셀의 드레인을 형성할 때 동시에 드레인 연결용 확산층을 형성하므로써 소자의 신뢰성 및 수율을 향상시킬 수 있는 비휘발성 메모리소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a bit line of a control gate of an adjacent cell sharing a bit line in a memory cell fabrication having electrically programmable and erase characteristics. Reducing the resistance of the control gate by connecting one line across the entire memory cell array except for the contact portion, and forming the diffusion layer for drain connection at the same time as forming the drain of each unit cell. The present invention relates to a method of manufacturing a nonvolatile memory device capable of improving the number of times.
비휘발성 메모리 소자에서 전기적으로 프로그램 및 소거 특성을 갖는 것으로 EPROM, EEPROM, Plash EEPROM 등이 있는데, 일반적으로 비트라인을 형성할 때 매립 확산층(Buried N+Layer:BN+층)을 주로 사용하고 있다. 매립확산층 형성단계는 필드 산화막 및 터널 산화막 성장공정 단계 이전에 형성되어지므로 인하여 소자의 신뢰성 및 수율에 커다란 영향을 미치는 터널 산화막의 특성을 악화시킴은 물론 매립 확산층이 필드 산화막 성장공정과 같이 고온 열공정으로 측면 확산이 일어나 펀치 쓰루(Punch Through)를 유발시키는 문제가 있다.In the nonvolatile memory device, there are electrically programmed and erased characteristics such as EPROM, EEPROM, and Plash EEPROM. In general, a buried diffusion layer (Buried N + Layer: BN + layer) is mainly used to form a bit line. Since the buried diffusion layer forming step is formed before the field oxide and tunnel oxide growth process steps, the characteristics of the tunnel oxide film having a great influence on the reliability and yield of the device are deteriorated, and the buried diffusion layer is a high temperature thermal process like the field oxide growth process. As a result, side diffusion occurs, causing a punch through.
제 1a, 1b 및 1c도는 제 1 도의 X-X', Y-Y' 및 X''-X'''선을 따라 절단한 소자의 단면도로써, 이들 도면을 참조하여 종래 비휘발성 메모리 소자의 제조방법 및 문제점을 설명하면 다음과 같다.1A, 1B, and 1C are cross-sectional views of devices cut along the lines X-X ', YY', and X ''-X '' 'of FIG. 1, with reference to these drawings. The problem is explained as follows.
실리콘 기판(1)에 웰(Well)을 형성한 후 활성영역(A)과 비활성영역(B)을 확정하고, 비트라인 영역(C)의 소정부분을 BN+마스크 및 BN+이온주입공정으로 BN+확산층(2)을 형성한 후 고온 산화공정을 통하여 비활성영역(B)에 필드 산화막(3)을 형성한다. 이때 필드 산화막(3) 하부의 BN+확산층(2)이 측면확산되어 펀치쓰루를 유발시킨다(셀 면적이 충분히 넓지 않을 때). 이후 터널 산화막(4)을 성장시키는데, 이 터널 산화막(4)은 BN+확산층(2) 형성 이후에 형성되므로 인하여 그 특성이 열악해지는 문제를 초래한다.After forming a well in the silicon substrate 1, the active region A and the inactive region B are determined, and a predetermined portion of the bit line region C is subjected to BN + mask and BN + ion implantation process. After the diffusion layer 2 is formed, the field oxide film 3 is formed in the inactive region B through a high temperature oxidation process. At this time, the BN + diffusion layer 2 under the field oxide film 3 is laterally diffused to cause punch-through (when the cell area is not large enough). Thereafter, the tunnel oxide film 4 is grown, and this tunnel oxide film 4 is formed after the formation of the BN + diffusion layer 2, resulting in a problem in that its characteristics are poor.
상기 터널 산화막(4) 형성후 플로팅 게이트 영역(D)에 플로팅 게이트(5)를 형성하고, 그 상부에 층간 절연막(6)을 형성한 후 비트라인 영역(C)을 사이에 두고 배열된 각 단위셀의 플로팅 게이트(5)와 겹치도록 된 컨트롤 게이트 영역(E)에 컨트롤 게이트(7)를 형성한다.After the tunnel oxide layer 4 is formed, the floating gate 5 is formed in the floating gate region D, and the interlayer insulating layer 6 is formed thereon, and each unit is arranged with the bit line region C interposed therebetween. The control gate 7 is formed in the control gate region E that overlaps the floating gate 5 of the cell.
상기 공정단계를 거친 후 소오스/드레인 마스크 및 N+이온주입공정으로 각 단위 셀의 소오스(8) 및 드레인(9)을 형성하고, 도면에는 도시하지 않았지만 일반적인 공정으로 층간 절연막, 실렉트 게이트 산화막 및 실렉트 게이트를 형성하는 단계로 비휘발성 메모리 소자를 제조한다.After the above process steps, the source 8 and the drain 9 of each unit cell are formed by a source / drain mask and an N + ion implantation process, and although not shown in the drawings, an interlayer insulating film, a select gate oxide film, The non-volatile memory device is manufactured by forming a select gate.
상기에서, 컨트롤 게이트(7)는 워드라인이 되며, 비트라인(C)은 드레인(9)과 BN+확상층(2)으로 이루어지며, 소오스 라인(F)은 각 단위셀의 소오스(8) 형성시 이루어진다.In the above, the control gate 7 is a word line, the bit line C is composed of a drain 9 and a BN + expansion layer 2, and the source line F is the source 8 of each unit cell. Is formed upon formation.
상기에서 언급한 바와 같이 종래 기술은 여러 가지 문제점을 안고있지만 이러한 문제점이 있음에도 불구하고 BN+층을 사용하는 이유는 다음과 같다. 활성영역으로 비트라인을 형상하고자 할 경우,플로팅 게이트 및 컨트롤 게이트를 형성하기 위하여 순차적으로 콘트롤 게이트용 제 2 폴리실리콘층, 층간 절연막 및 플로팅 게이트용 제 1 폴리실리콘층을 하나의 마스크로 식각하는 자기정렬 식각(Selfalign Etch)공정을 실시한다. 그런데 비트라인이 활성 영역으로 되어있고 플로팅 게이트용 제 1 폴리실리콘층으로 덮혀있지 않다면, 두께가 얇은 터널 산화막은 층간 절연막 식각시 충분히 제거될 수 있다. 따라서 플로팅 게이트용 제 1 폴리실리콘층이 식각될 시점에서는 터널 산화막이 제거되어 실리콘 기판이 노출되므로, 플로팅 게이트용 제 1 폴리실리콘층 식각시 실리콘 기판의 손상을 피할 수 없게 된다.As mentioned above, although the prior art has various problems, the reason for using the BN + layer despite the problem is as follows. In order to form a bit line as an active region, a magnetic layer sequentially etching a second polysilicon layer for a control gate, an interlayer insulating layer, and a first polysilicon layer for a floating gate with one mask to form a floating gate and a control gate. Perform a Selfalign Etch process. However, if the bit line is an active region and is not covered with the first polysilicon layer for the floating gate, the thin tunnel oxide film may be sufficiently removed during the interlayer insulating layer etching. Therefore, when the first polysilicon layer for the floating gate is etched, the tunnel oxide film is removed to expose the silicon substrate, so that the silicon substrate may not be damaged during the etching of the first polysilicon layer for the floating gate.
이를 방지하기 위한 종래 방법은 이 부분에 층간 절연막 식각 후에도 충분한 절연 물질이 남아있도록 필드 산화막을 형성하고, 이로 인해 연결이 끊어지는 비트라인을 연결시킬수 있도록 필드 산화막 형성 이전 제 N+층을 형성하는 것이다.The conventional method to prevent this is to form a field oxide film in this part so that sufficient insulating material remains after the interlayer insulating film etching, and thus form the N + layer before forming the field oxide film so as to connect the disconnected bit line. .
한편, 플로팅 게이트의 최소 폭을 줄이더라도 소자 특성에 나쁜 영향을 미치지는 않지만, 현대의 노광 장치로는 최소 가능 선폭 (Minimum Feature Size)에 한계가 있기 때문에 이 선폭에 의해 플로팅 게이트의 최소 폭이 결정될 수 밖에 없다.Although reducing the minimum width of the floating gate does not adversely affect device characteristics, the minimum width of the floating gate may be determined by the line width because the minimum feature size is limited in modern exposure apparatus. There is no choice but to.
따라서, 본 발명은 기판 손상이 발생하는 부분을 컨트롤 게이트용 폴리실리콘층으로 보호하여 활성영역에 의한 비트라인의 형성을 가능하게 하고, 소자 특성을 열화시키는 BN+층 사용을 배제시키며, 플로팅 게이트의 폭을 노광장치의 최소 가능선폭 이하 크기로도 임의로 형성시킬 수 있는 비휘발성 메모리 소자 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention protects the portion where the substrate damage occurs with the polysilicon layer for the control gate to enable the formation of the bit line by the active region, and eliminates the use of the BN + layer to deteriorate device characteristics, It is an object of the present invention to provide a method for manufacturing a nonvolatile memory device, in which the width can be arbitrarily formed even below the minimum possible line width of the exposure apparatus.
이러한 목적을 달성하기 위한 본 발명의 비휘발성 메모리 소자 제조방법은 실리콘 기판에 활성영역과 비활성영역을 확정한 후 필드 산화막을 성장시키고, 터널 산화막과 제 1 폴리실리콘층을 형성하는 단계와, 상기 제 1 폴리실리콘층을 1차 식각한 후 불순물 이온주입공정으로 비트라인을 형상하는 단계와, 상기 단계로부터 층간 절연막 및 제 2 폴리실리콘층을 형성한 후 자기정렬 식각공정으로 상기 1차 식각된 제1폴리실리콘층과 제2폴리실리콘층을 식각하는 단계와, 상기 단계로부터 불순물 이온주입공정으로 소오스를 형성하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention may include: forming a tunnel oxide film and a first polysilicon layer after determining an active region and an inactive region on a silicon substrate, and forming a tunnel oxide film First etching the polysilicon layer and forming a bit line by an impurity ion implantation process; forming an interlayer insulating film and a second polysilicon layer from the step; and then forming the first line by the self-aligned etching process. And etching the polysilicon layer and the second polysilicon layer, and forming a source through the impurity ion implantation process from the step.
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2,3,4도는 본 발명에 따라 공정단계별로 도시한 레이아웃도이고, 제2a 및 2b 도는 제2도의 X-X' 및 Y-Y'선을 따라 절단한 소자의 단면도이며, 제 3a 및 3b 도는 제3도의 X-X' 및 Y-Y'선을 따라 전단한 소자의 단면도이고, 제 4a 및 4b 도는 제4도의 X-X' 및 Y-Y'선을 따라 절단한 소자의 단면도이다.2, 3, and 4 are layout views of process steps according to the present invention, and FIGS. 2A and 2B are cross-sectional views of elements cut along lines XX 'and Y-Y' of FIG. 2, and FIGS. Sectional drawing of the element sheared along the line XX 'and Y-Y' of FIG. 3, and FIG. 4A and 4b are sectional drawing of the element cut along the line XX 'and Y-Y' of FIG.
제2,2a 및 2b도는 실리콘 기판(11)에 웰을 형성한 후, 트랜지스터의 채널(G) 비트라인(C) 및 소오스라인(F)이 되어질 부분을 활성영역(A)이 되게하고, 그 이외의 부분을 비활성영역(B)으로 확정하여 필드 산화막(도시안됨)을 형성한 상태를 도시한 것이다.2, 2a and 2b show that the wells are formed in the silicon substrate 11, and then the portions to be the channel (G) bit lines (C) and the source lines (F) of the transistors become active regions (A). The state where other portions are determined as inactive regions B to form a field oxide film (not shown) is shown.
제3,3a 및 3b도는 활성영역(A)에 터널 산화막(12)을 성장시킨 후 전체구조 상부에 제 1 폴리실리콘층(13)을 증착하고, 전체구조 상부에 감광막(14)을 도포한 후 비트라인영역(C)을 제외한 나머지 활성영역(A)이 충분히 엎히도록 감광막(14)을 패턴화하고, 패턴화된 감광막(14)을 식각 장벽층으로한 식각공정으로 제 1 폴리실리콘층(13)을 1차로 식각한 후 불순물 이온주입공정으로 각 단위 셀의 드레인(15)을 형성함과 동시에 이 드레인(15)들을 연결해주는 드레인 연결용 확산층(15A)을 형성하여 소자의 비트라인(C)을 형성한 상태를 도시한 것이다.3, 3a, and 3b show that after the tunnel oxide film 12 is grown in the active region A, the first polysilicon layer 13 is deposited on the entire structure, and the photoresist film 14 is coated on the entire structure. The first polysilicon layer 13 is patterned by etching the photoresist layer 14 so that the remaining active region A except for the bit line region C is sufficiently exposed, and using the patterned photoresist layer 14 as an etching barrier layer. ) Is first etched, and the impurity ion implantation process forms a drain 15 of each unit cell and at the same time forms a drain connection diffusion layer 15A connecting the drains 15 to the bit line C of the device. It shows a state formed.
제4,4a 및 4b도는 상기 감광막(14)을 제거한 후 층간 절연막(16)을 형성하고, 전체구조 상부에 제 2 폴리실리콘층(17)을 증착한 후 자기정렬 식각공정으로 제 2 폴리실리콘층(17)과 1차로 식각된 제 1 폴리실리콘층(13)을 식각하여 플로팅게이트 영역(D)에 플로팅 게이트(13) 및 컨트롤 게이트 영역(E)에 컨트롤 게이트(17)을 형성한 상태를 도시한 것이다.4, 4a and 4b show that the photoresist film 14 is removed, the interlayer insulating film 16 is formed, the second polysilicon layer 17 is deposited on the entire structure, and the second polysilicon layer is formed by a self-aligned etching process. 1 and the first polysilicon layer 13 etched primarily to etch to form a control gate 17 in the floating gate 13 and the control gate region (E) in the floating gate region (D). It is.
상기 층간 절연막(16)은 ONO(Oxide-Nitride_Oxide)구조로 형성시킬 수 있는데, 제 1 폴리실리콘층(13) 증착후 하부산화막과 질화막을 형성한 다음 제 2 폴리실리콘층(17) 증착전에 상부 산화막을 형성하여 층간 절연막(16)을 형성할 수 있다.The interlayer insulating layer 16 may be formed of an oxide-nitride_oxide (ONO) structure. After depositing the first polysilicon layer 13, a lower oxide layer and a nitride layer are formed, and then an upper oxide layer is deposited before the second polysilicon layer 17 is deposited. Can be formed to form the interlayer insulating film 16.
상기 컨트롤 게이트(17)는 비트라인(C)을 공유하는 인접 셀에 공통 컨트롤 게이트가 되도록 형성한다. 즉, 비트라인(C)을 공유하는 인접 셀의 컨트롤 게이트(17)를 비트라인 콘택부(도시안됨)를 제외한 전체 메모리 셀 어레이에 걸쳐 하나의 선으로 연결되도록 형성한다.The control gate 17 is formed to be a common control gate in the adjacent cell sharing the bit line (C). That is, the control gate 17 of the adjacent cell sharing the bit line C is formed to be connected by one line over the entire memory cell array except the bit line contact portion (not shown).
이후 소오스라인 영역(F)이 개방되도록 마스크 작업을 실시하고 불순물 이온주입공정으로 각 단위셀의 소오스(18)를 형성함과 동시에 이 소오스(18)들을 연결해주는 소오스 연결용 확산층을 형성하고, 실렉트 게이트 산화막 및 실렉트 게이트를 형성하여 본 발명의 비휘발성 메모리 소자가 제조된다.Subsequently, a mask operation is performed to open the source line region F, and a source connection diffusion layer connecting the sources 18 is formed at the same time as the source 18 of each unit cell is formed by an impurity ion implantation process. The non-volatile memory device of the present invention is manufactured by forming a direct gate oxide film and a select gate.
본 발명에 의하면, 비트라인을 컨트롤 게이트(제 2 폴리실리콘층)에 의해 충분히 덮는데, 종래의 셀 구조에서 하나의 비트라인을 공유하는 인접한 두 개의 컨트롤 게이트는 셀 동작시 애초에 논리적으로 동일한 선(공통 콘트롤 게이트)으로 인식되어지므로, 본 발명과 같이 비트라인을 덮는 하나의 컨트롤 게이트를 형성하여도 소자의 동작은 종래와 달라지지 않는다. 그리고 컨트롤 게이트용 제 2 폴리실리콘층을 사진공정을 통해 식각할 때 1차로 식각된 플로팅 게이트용 제 1 폴리실리콘층이 동시에 식각되는 자기정렬 식각공정을 실시하면 비트라인은 컨트롤 게이트(제 2 폴리실리콘층)에 의해 기판 손상으로부터 충분히 보호받을 수 있게된다. 뿐만 아니라 제 1 폴리실리콘층으로 형성되는 플로팅 게이트의 최소폭이 종래에는 노광장치의 최소 가능 선폭에 의해 결정되었지만, 본 발명에서는 플로팅 게이트의 한쪽 측면을 제 1 폴리실리콘(플로팅 게이트)의 1차 식각때 확정(Define)하고 다른쪽 측면을 자기정렬 식각에 의해 확정하므로써 노광장치의 최소 가능 선폭 이하 크기의 플로팅 게이트 형성을 가능하게 한다.According to the present invention, a bit line is sufficiently covered by a control gate (second polysilicon layer). In a conventional cell structure, two adjacent control gates that share one bit line are logically identical lines (the first time) during cell operation. Since it is recognized as a common control gate, even if one control gate is formed to cover the bit line as in the present invention, the operation of the device is not different from the prior art. When the second polysilicon layer for the control gate is etched through a photo process, the self-aligned etching process in which the first polysilicon layer for the floating gate, which is primarily etched, is simultaneously etched is performed, and the bit line is the control gate (the second polysilicon). Layer) can be sufficiently protected from substrate damage. In addition, although the minimum width of the floating gate formed of the first polysilicon layer is conventionally determined by the minimum possible line width of the exposure apparatus, in the present invention, one side of the floating gate is first etched by the first polysilicon (floating gate). Defining and defining the other side by self-aligned etching enable the formation of a floating gate having a size smaller than the minimum possible line width of the exposure apparatus.
또한, 각 단위 셀의 드레인 형성은 종래에 소오스와 동시에 형성되는 것과는 달리 독립적으로 형성되므로 드레인 구조에 커다란 영향을 받는 소거특성을 보다 쉽게 최적화시킬 수 있다.In addition, since the drain formation of each unit cell is formed independently unlike conventionally formed at the same time as the source, it is possible to more easily optimize the erase characteristics which are greatly influenced by the drain structure.
더우기, 종래의 방법에서는 각 셀에 대한 드레인이 레이아웃상으로 연결될수 없어 BN+층을 이용하여 비트라인을 형성하였으나, 본 발명에서는 개별 셀에 대한 드레인 형성과 동시에 이들 드레인을 연결해주는 드레인 연결용 확산층이 형성되어 있으므로 사진공정 및 감광막 제거공정이 필요하지 않으므로 공정이 단순해진다.Moreover, in the conventional method, since the drains for each cell cannot be connected in a layout, bit lines are formed using the BN + layer. However, in the present invention, a drain connection diffusion layer for connecting the drains at the same time as the drains for the individual cells is formed. Since the photo process and the photosensitive film removal process are not necessary, the process is simplified.
상술한 바에 의거한 본 발명의 효과는 BN+층 제거로 인한 소자의 신뢰성 및 수율을 향상시킬 수 있으며, 컨트롤 게이트(제 2 폴리실리콘층)의 저항감소에 따른 소자의 특성을 향상시킬 수 있으며, 공정 단순화에 따른 생산단가절감 및 셀 면적의 감소에 따른 네트 다이(Net Die) 수 증가를 이룰 수 있으며, 또한 드레인과 소오스 형성 공정의 차별화로 프로그램/소거특성을 최적화시키는 것이 용이하다.Effects of the present invention based on the above can improve the reliability and yield of the device due to the removal of the BN + layer, it is possible to improve the characteristics of the device according to the resistance of the control gate (second polysilicon layer), It is possible to reduce the production cost by reducing the process and increase the number of net dies by decreasing the cell area, and it is easy to optimize the program / erase characteristics by differentiating the drain and source forming process.
Claims (7)
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