CN100343981C

CN100343981C - Method for producing embedded flash memory

Info

Publication number: CN100343981C
Application number: CNB2004100664649A
Authority: CN
Inventors: 杨左娅; 金达
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2004-09-16
Filing date: 2004-09-16
Publication date: 2007-10-17
Anticipated expiration: 2024-09-16
Also published as: CN1750254A

Abstract

The present invention relates to a method for producing an embedded type flash memory, which is used for manufacturing a device with three different thickness gate oxide layers. The method adopts a conventional dry type etching mode and / or a wet type etching mode by a few times to respectively remove the ONO (silicon oxide-silicon nitride-silicon oxide) layer of a specified region on base materials. Each step does not use hydrofluoric acid and no light covering step is added. The method of the present invention can avoid shallow track isolation (STI) caused by the hydrofluoric acid or influence on other transistor parameters, simultaneously have the advantages of low cost and easy implementation.

Description

A kind of method of making embedded flash memory

Technical field

The present invention relates to a kind of manufacture method of embedded flash memory, especially make a kind of device with grid oxic horizon of three different-thickness.

Summary of the invention

The present invention attempts to solve above-mentioned the problems of the prior art, provides a kind of and avoids using hydrofluoric acid, and the not too high again manufacture method of cost, is used to make the device of three kinds of different-thickness grid oxide layers of needs, specifically, and embedded flash memory.

The present invention has adopted extra dry-etching and wet etch step, can finish above-mentioned purpose cheaply.Manufacture method of the present invention is such:

Semi-conductive substrate at first is provided, is distributed with logic cells area and memory cell area on this substrate, deposit ONO (silica-silicon-nitride and silicon oxide) on it; First area on it, second area, the 3rd zone need three different operating voltages from low to high respectively, and wherein the 3rd zone is for the highest;

Remove the ONO on the 3rd zone: carry out the ONO etching with the light masking method, remove the ONO on the 3rd zone;

Carry out the GOX first time (Gate Oxide, grid oxic horizon) growth: the thickest grid oxic horizon of long one deck on the 3rd zone;

Remove the ONO on the second area: adopt ONO engraving method commonly used, both avoided having used hydrofluoric acid, also reduce STI oxide layer disappearance;

Carry out the GOX growth second time, on second area, form grid oxic horizon, this oxide layer thin than on the 3rd zone;

Remove the oxide on the first area: adopt ONO engraving method commonly used, remove the ONO on the first area 21, both avoided having used hydrofluoric acid, also reduce STI oxide layer disappearance;

Carry out GOX growth for the third time, form grid oxic horizon on the first area, this oxide layer is for the thinnest, because the operating voltage that should require is minimum;

Carry out the grid polycrystalline silicon deposition;

And other subsequent techniques identical with conventional method.

The present invention can reach duplicate result than existing conventional technology, avoids again because use hydrofluoric acid STI performance or other transistor parameter being affected.Simultaneously, the present invention both cost is low, convenient again enforcement.

Description of drawings

Fig. 1 is the later memory unit structure schematic diagram of the ONO deposition step of common process and technology of the present invention,

Fig. 2 a is the memory unit structure schematic diagram after the ONO of common process is etched with,

Fig. 2 b is the memory unit structure schematic diagram after ONO of the present invention is etched with,

Fig. 3 a is the later memory unit structure schematic diagram of the GOX growth first time of common process,

Fig. 3 b is the later memory unit structure schematic diagram of the GOX growth first time of the present invention,

Fig. 4 a is the memory unit structure schematic diagram after the HVO of common process is etched with,

Fig. 4 b is the memory unit structure schematic diagram after HVO of the present invention is etched with,

Fig. 5 a is the later memory unit structure schematic diagram of the GOX growth second time of common process,

Fig. 5 b is the later memory unit structure schematic diagram of the GOX growth second time of the present invention,

Fig. 6 a is the memory unit structure schematic diagram after the DG of common process is etched with,

Fig. 6 b is the memory unit structure schematic diagram after DG of the present invention is etched with,

Fig. 7 a is the later memory unit structure schematic diagram of the growth of GOX for the third time of common process,

Fig. 7 b is the later memory unit structure schematic diagram of the growth of GOX for the third time of the present invention,

Fig. 8 a is the later memory unit structure schematic diagram of grid polycrystalline silicon deposition of common process,

Fig. 8 b is the later memory unit structure schematic diagram of grid polycrystalline silicon deposition of the present invention.

Description of reference numerals is as follows:

1-Semiconductor substrate (semiconductor substrate)

11,11 '-tunnel oxide (tunnel oxidation layer) 12,12 '-ONO 3,3 '-floating grid

21,21 '-first grid oxide layer zone 22,22 '-second grid oxide layer zone

23, the grid oxic horizon of 23 '-Di, three gate oxidation layer regions 401, the 401 '-growth first time

402,402 '-for the second time grid oxic horizon of growth

The grid oxic horizon of 403,403 '-for the third time growth

501,501 '-grid polycrystalline silicon

DG (Dual Gate; Double grid)

Specific embodiment

Describe content of the present invention in detail below in conjunction with accompanying drawing.

In order to describe technical process of the present invention and explanation advantage of the present invention better, the structure of especially that the present invention and existing common process key step is later mnemon compares, again can be short and sweet so that fully understand the present invention.

As shown in Figure 1, be the later memory unit structure schematic diagram of the ONO deposition step of common process and technology of the present invention, wherein this device needs three different operating voltages, respectively, first area 21 required voltages are 1.8V, second area is 3.3V, and the 3rd zone is the high voltage district, generally reaches as high as 18V.Correspondingly, we can know that the thickness of the grid oxic horizon that above-mentioned three zones need is that the first area is the thinnest, and the 3rd zone is the thickest, shown in Fig. 8 a and Fig. 8 b.

Method of the present invention is such:

Semi-conductive substrate 1 at first is provided, is distributed with logic cells area and memory cell area on this substrate, deposit ONO (silica-silicon-nitride and silicon oxide) on it, its structural representation such as Fig. 1;

Carry out the ONO etching with the light masking method, Fig. 2 a is the memory unit structure schematic diagram after the ONO of common process is etched with, ONO on the gate oxidation layer region 21 ', 22 ', 23 ' is Removed All, Fig. 2 b is the memory unit structure schematic diagram after ONO of the present invention is etched with, and has only the ONO on the 3rd zone 23 to be removed;

Carry out the GOX first time (Gate Oxide, grid oxic horizon) growth, Fig. 3 a is the later memory unit structure schematic diagram of the GOX growth first time of common process, has all grown the oxide layer 401 ' of a bed thickness on the gate oxidation layer region 21 ', 22 ', 23 '; Fig. 3 b is the later memory unit structure schematic diagram of the GOX growth first time of the present invention, has only the oxide layer 401 of having grown a bed thickness on the 3rd zone 23;

Carry out HVO (High Voltage Oxide, high voltage oxide layer) etching, Fig. 4 a is the memory unit structure schematic diagram after the HVO of common process is etched with, and adopts photomask to carry out the HVO etching, and the thick oxide layer on the second area 22 ' is removed; Fig. 4 b is the memory unit structure schematic diagram after HVO of the present invention is etched with, and employing ONO engraving method commonly used removes the ONO on the second area 22, has both avoided having used hydrofluoric acid, also reduces STI oxide layer disappearance;

Carry out the GOX growth second time, Fig. 5 a is the later memory unit structure schematic diagram of the GOX growth second time of common process, and grid oxic horizon 402 ' to 401 ' will approach; Fig. 5 b is the later memory unit structure schematic diagram of the GOX growth second time of the present invention, and similarly, grid oxic horizon 402 to 401 is thin;

Remove the oxide on the first area, Fig. 6 a is the memory unit structure schematic diagram after the DG of common process is etched with, and adopts the DG photomask, and HF soaks, and etches away the thick oxide layer 401 ' on the first area 21 '; Fig. 6 b is the memory unit structure schematic diagram after DG of the present invention is etched with, and employing ONO engraving method commonly used removes the ONO on the first area 21, has both avoided having used hydrofluoric acid, also reduces STI oxide layer disappearance;

Carry out GOX growth for the third time, Fig. 7 a is the later memory unit structure schematic diagram of the 403 ' growth of GOX for the third time of common process, and oxide layer 403 ' is for the thinnest, because the operating voltage that first area 21 ' requires is minimum; Fig. 7 b is the later memory unit structure schematic diagrames of 403 growths of GOX for the third time of the present invention, and similarly, oxide layer 403 is for the thinnest, because the operating voltage that this first area 21 requires is minimum;

The grid polycrystalline silicon deposition, Fig. 8 a is the later memory unit structure schematic diagram of grid polycrystalline silicon 501 ' deposition of common process; Fig. 8 b is the later memory unit structure schematic diagrames of grid polycrystalline silicon 501 depositions of the present invention.

Referring to Fig. 8 a and Fig. 8 b, can find that the present invention than existing conventional technology, can reach duplicate result, avoid again STI performance or other transistor parameter being affected because use hydrofluoric acid.Simultaneously,, but do not increase the step of photomask because just increased the step of dry-etching and Wet-type etching, so both cost was low in the present invention, convenient again enforcement.

More than show and described basic principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; the present invention also has various changes and modifications without departing from the spirit and scope of the present invention, and these changes and improvements all fall in the claimed scope of the present invention.The scope of protection of present invention is defined by appending claims and equivalent thereof.

Claims

1. method of making embedded flash memory, this flash memory has the grid oxic horizon of three different-thickness, it is characterized in that comprising following steps:

A) provide semi-conductive substrate, the first area that distributes on this substrate, second area, the 3rd zone need three different operating voltages respectively, and wherein the 3rd zone is for the highest;

B) remove ONO on the 3rd zone;

C) carry out the gate oxidation layer growth first time, the thickest grid oxic horizon of long one deck on the 3rd zone;

D) remove ONO on the second area;

E) carry out the gate oxidation layer growth second time, on second area, form grid oxic horizon;

F) remove ONO on the first area;

G) carry out gate oxidation layer growth for the third time, on the first area, form grid oxic horizon;

H) carry out the grid polycrystalline silicon deposition.

2. manufacture method as claimed in claim 1 is characterized in that, described steps d, and f does not adopt hydrofluoric acid dips technology.

3. manufacture method as claimed in claim 2 is characterized in that, described steps d, and f adopts etch process.

4. manufacture method as claimed in claim 3 is characterized in that, described steps d, and the etch process that f adopts is a dry-etching.

5. manufacture method as claimed in claim 3 is characterized in that, described steps d, and the etch process that f adopts is that dry-etching is in conjunction with Wet-type etching.