CN103137453B - Growth is used for the method for the thick grid oxic horizon of high-voltage metal oxide semiconductor device - Google Patents
Growth is used for the method for the thick grid oxic horizon of high-voltage metal oxide semiconductor device Download PDFInfo
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- CN103137453B CN103137453B CN201110382884.8A CN201110382884A CN103137453B CN 103137453 B CN103137453 B CN 103137453B CN 201110382884 A CN201110382884 A CN 201110382884A CN 103137453 B CN103137453 B CN 103137453B
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Abstract
The present invention discloses the method for a kind of growth for the thick grid oxic horizon of high-voltage metal oxide semiconductor device; Before the thick grid oxic horizon growth of high tension apparatus occurs in shallow trench isolation, by silicon nitride layer as hard mask. The present invention avoids low-voltage device electrical characteristic and reliability performance change in high pressure gate oxidation process, reduces risk, and technique is simple simultaneously, photolithography plate number remains unchanged.
Description
Technical field
The present invention relates to ic manufacturing technology.
Background technology
Along with the development of unicircuit, system-on-a-chip is integrated becomes trend. This just needs to have on one chip the intelligent control circuit of MCU and simulation or high pressure circuit simultaneously.
But in the technique of reality, the thick grid oxic horizon growth of high tension apparatus can introduce the long-time thermal process of extra high temperature and wet etching process, correlated particle is caused to inject the change of condition, the lattice imperfection that silicon substrate STRESS VARIATION is brought out occurs and surface silicon consumption, thus causes electrical characteristic and the reliability performance change of serious low-voltage device. Existing solution all concentrates on after the thick grid oxic horizon growth of high tension apparatus is occurred in shallow trench isolation (STI), before Low-Voltage Logic Devices grid oxic horizon is grown up. The change caused by the growth of thick grid oxic horizon of high tension apparatus is made up by the adjustment of particle injection condition. So just there is the dangerous high disadvantage of complex process.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method at middle grow thick grid oxic horizon, and it can avoid low-voltage device and non-volatile memory device electrical characteristic and reliability performance change in high pressure gate oxidation process.
In order to solve above technical problem, the present invention provides a kind of method at middle grow thick grid oxic horizon; Before the thick grid oxic horizon growth of high tension apparatus occurs in shallow trench isolation, by silicon nitride layer as hard mask.
The useful effect of the present invention is: avoids low-voltage device and non-volatile memory device electrical characteristic and reliability performance change in high pressure gate oxidation process, reduces risk, and technique is simple simultaneously, photolithography plate number remains unchanged.
The above-mentioned a kind of method being used for the thick grid oxic horizon of high-voltage metal oxide semiconductor device in growth; Comprise the following steps:
The thick grid oxic horizon SiO2 of growth high tension apparatus;
Utilize the method for photoetching and wet etching to be removed by the thick grid oxic horizon of Low-Voltage Logic Devices, expose silicon substrate;
Form sacrificial oxide layer.
Utilize the thick grid oxic horizon of high tension apparatus as alignment fiducials, carry out high tension apparatus trap injection and thermal process;
Form the silicon nitride layer being used for channel isolation hard mask effect;
The method of photoetching and dry plasma corrosion is utilized to form channel isolation;
Place zone of oxidation and cmp in deposition channel isolation;
Peel off silicon nitride layer;
Form the hard mask silicon nitride layer of the thick grid oxic horizon provide protection being used for high tension apparatus;
Utilize the method for photoetching and dry plasma corrosion to be removed by the hard mask silicon nitride layer in Low-Voltage Logic Devices region, expose sacrificial oxide layer;
Low voltage CMOS trap injects and cut-in voltage of being correlated with regulates injection;
Utilize the method for wet etching to be removed by the sacrificial oxide layer in Low-Voltage Logic Devices region, expose silicon substrate;
Utilize the method for wet etching to be removed by the hard mask silicon nitride layer in high tension apparatus region, expose the thick grid oxic horizon of high tension apparatus;
Utilize the method growth low pressure grid oxic horizon of thermooxidizing.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is thick grid oxic horizon (SiO2 is 1.) the growth schematic diagram of high tension apparatus.
Fig. 2 utilizes photoetching (mask plate be Mask 1.) and the method for wet etching to be removed by the thick grid oxic horizon in Low-Voltage Logic Devices region, exposes the schematic diagram of silicon substrate.
Fig. 3 is the schematic diagram that sacrificial oxide layer (SiO2 is 2.) is formed.
Fig. 4 utilizes the thick grid oxic horizon of high tension apparatus as alignment fiducials (AlignmentKey), carries out the schematic diagram of high tension apparatus trap injection and thermal process.
Fig. 5 is the schematic diagram that the silicon nitride layer for channel isolation (STI) hard mask effect (SiN is 1.) is formed;
Fig. 6 is the schematic diagram utilizing the method for photoetching and dry plasma corrosion to form channel isolation (STI).
Fig. 7 is the schematic diagram of place oxide deposition and cmp (CMP) in channel isolation.
Fig. 8 is the schematic diagram that silicon nitride layer (SiN is 1.) is peeled off.
Fig. 9 is the schematic diagram that the hard mask silicon nitride layer (SiN is 2.) of the thick grid oxic horizon provide protection for high tension apparatus is formed.
Figure 10 utilizes the method for photoetching (mask plate still for Mask 1.) and dry plasma corrosion to be removed by the hard mask silicon nitride layer (SiN is 2.) in Low-Voltage Logic Devices region, exposes the schematic diagram of sacrificial oxide layer (SiO2 is 2.).
Figure 11 is that low voltage CMOS trap injects and cut-in voltage of being correlated with regulates the schematic diagram injected.
Figure 12 utilizes the method for wet etching to be removed by the sacrificial oxide layer (SiO2 is 2.) in Low-Voltage Logic Devices region, exposes the schematic diagram of silicon substrate.
Figure 13 utilizes the method for wet etching to be removed by the hard mask silicon nitride layer (SiN is 2.) in high tension apparatus region, exposes the schematic diagram of the thick grid oxic horizon (SiO2 is 1.) of high tension apparatus.
Figure 14 utilizes the schematic diagram of the method growth low pressure grid oxic horizon of thermooxidizing.
Embodiment
Before the present invention proposes that the thick grid oxic horizon growth of high tension apparatus is occurred in shallow trench isolation (STI) first, by silicon nitride layer as hard mask, while guaranteeing thick grid oxic horizon thickness, this kind of method can avoid low-voltage device and non-volatile memory device electrical characteristic and reliability performance change in high pressure gate oxidation process, reducing risk, simultaneously technique is simple, photolithography plate number remains unchanged. Idiographic flow is as follows:
Protecting grows up the thick grid oxic horizon of high tension apparatus occurs in before shallow trench isolation (STI) formed, by the related process flow process of silicon nitride layer as hard mask. Specific as follows:
As shown in Figure 1, (1) the thick grid oxic horizon (SiO2 is 1.) of high tension apparatus is grown up.
As shown in Figure 2, (2) utilize photoetching (mask plate be Mask 1.) and the method for wet etching to be removed by the thick grid oxic horizon of Low-Voltage Logic Devices, expose silicon substrate.
As shown in Figure 3, (3) formation of sacrificial oxide layer (SiO2 is 2.).
(4) as shown in Figure 4, utilize the thick grid oxic horizon of high tension apparatus as alignment fiducials (AlignmentKey), substitute alignment (zerolayer) and carry out high tension apparatus trap injection and thermal process. A photo mask board can be saved like this.
As shown in Figure 5, (5) silicon nitride layer (SiN is 1.) for channel isolation (STI) hard mask effect is formed.
As shown in Figure 6, (6) method of photoetching and dry plasma corrosion is utilized to form channel isolation (STI).
As shown in Figure 7, (7) place oxide deposition and cmp (CMP) in channel isolation.
As shown in Figure 8, (8) silicon nitride layer (SiN is 1.) is peeled off.
As shown in Figure 9, (9) for high tension apparatus thick grid oxic horizon provide protection hard mask silicon nitride layer (SiN is 2.) formed.
(10) as shown in Figure 10, utilize the method for photoetching (mask plate still for Mask 1.) and dry plasma corrosion to be removed by the hard mask silicon nitride layer (SiN is 2.) in Low-Voltage Logic Devices region, expose sacrificial oxide layer (SiO2 is 2.).
As shown in figure 11, (11) low voltage CMOS trap injects and cut-in voltage adjustment injection of being correlated with.
As shown in figure 12, (12) utilize the method for wet etching to be removed by the sacrificial oxide layer (SiO2 is 2.) in Low-Voltage Logic Devices region, expose silicon substrate.
As shown in figure 13, (13) utilize the method for wet etching that the hard mask silicon nitride layer (SiN is 2.) in high tension apparatus region is exposed the thick grid oxic horizon (SiO2 is 1.) of high tension apparatus.
As shown in figure 14, (14) the method growth low pressure grid oxic horizon of thermooxidizing is utilized.
Subsequent process steps is consistent with traditional technology. Owing to the thick grid oxic horizon growth of high tension apparatus is the initial process of whole technical process, the alignment fiducials (AlignmentKey) of subsequent optical carving technology therefore can be used as. So just save a conventional alignment fiducials mask plate (AlignmentKeymask). Meanwhile, in order to accurately control the thickness of thick grid oxic horizon, 1. Mask to be utilized second time, as the graphic definition of hard mask silicon nitride layer (SiN is 2.). So, total photo mask board number remains unchanged.
Owing to the thick grid oxic horizon growth of high tension apparatus is the initial process of whole technical process, the alignment fiducials (AlignmentKey) of subsequent optical carving technology therefore can be used as. So just save a conventional alignment fiducials mask plate (AlignmentKeymask). Meanwhile, in order to accurately control the thickness of thick grid oxic horizon, 1. Mask to be utilized second time, as the graphic definition of hard mask silicon nitride layer (SiN is 2.). So, total photo mask board number remains unchanged.
The present invention is not limited to enforcement mode discussed above. Above the description of embodiment is intended to describe and the technical scheme that the present invention relates to is described. Apparent conversion or replacement based on the present invention's enlightenment also should be considered to fall into protection scope of the present invention. Above embodiment is used for disclosing the best implementation method of the present invention, so that the those of ordinary skill of this area can apply the numerous embodiments of the present invention and multiple alternative to reach the object of the present invention.
Claims (1)
1. one kind grows the method being used for high-voltage metal oxide semiconductor device grids zone of oxidation; It is characterized in that, the grid oxic horizon growth of high tension apparatus by silicon nitride layer as hard mask, comprises the following steps before occurring in shallow trench isolation:
The grid oxic horizon SiO of growth high tension apparatus2;
Utilize the method for photoetching and wet etching to be removed by the grid oxic horizon of Low-Voltage Logic Devices, expose silicon substrate;
Form sacrificial oxide layer;
Utilize the grid oxic horizon of high tension apparatus as alignment fiducials, carry out high tension apparatus trap injection and thermal process;
Form the silicon nitride layer being used for shallow trench isolation hard mask effect;
The method of photoetching and dry plasma corrosion is utilized to form shallow trench isolation;
Place zone of oxidation and cmp in deposition shallow trench isolation;
Peel off silicon nitride layer;
Form the hard mask silicon nitride layer of the grid oxic horizon provide protection being used for high tension apparatus;
Utilize the method for photoetching and dry plasma corrosion to be removed by the hard mask silicon nitride layer in Low-Voltage Logic Devices region, expose sacrificial oxide layer;
Low voltage CMOS trap injects and cut-in voltage of being correlated with regulates injection;
Utilize the method for wet etching to be removed by the sacrificial oxide layer in Low-Voltage Logic Devices region, expose silicon substrate;
Utilize the method for wet etching to be removed by the hard mask silicon nitride layer in high tension apparatus region, expose the grid oxic horizon of high tension apparatus;
Utilize the method growth low pressure grid oxic horizon of thermooxidizing.
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| CN112103347A (en) * | 2020-11-17 | 2020-12-18 | 晶芯成(北京)科技有限公司 | Method for manufacturing semiconductor structure |
| CN112635316B (en) * | 2020-12-14 | 2022-06-07 | 华虹半导体(无锡)有限公司 | Method for manufacturing high-voltage thick gate oxide |
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| CN1750254A (en) * | 2004-09-16 | 2006-03-22 | 中芯国际集成电路制造(上海)有限公司 | Method for producing embedded flash memory |
| CN102243995A (en) * | 2011-06-23 | 2011-11-16 | 上海集成电路研发中心有限公司 | Integration method of gate oxide with different thicknesses in high-voltage process |
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| CN1750254A (en) * | 2004-09-16 | 2006-03-22 | 中芯国际集成电路制造(上海)有限公司 | Method for producing embedded flash memory |
| CN102243995A (en) * | 2011-06-23 | 2011-11-16 | 上海集成电路研发中心有限公司 | Integration method of gate oxide with different thicknesses in high-voltage process |
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