CN104967437A - Si-based low leakage current cantilever beam gate CMOS (complementary metal oxide semiconductor) transmission gate and preparation method thereof - Google Patents
Si-based low leakage current cantilever beam gate CMOS (complementary metal oxide semiconductor) transmission gate and preparation method thereof Download PDFInfo
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Abstract
The invention relates to a Si-based low leakage current cantilever beam gate CMOS (complementary metal oxide semiconductor) transmission gate and a preparation method thereof. The transmission gate is composed of a cantilever beam gate NMOS (N-channel metal oxide semiconductor) transistor and a cantilever beam gate PMOS (P-channel metal oxide semiconductor) transistor. The MOS transistor of the transmission gate is prepared on a silicon substrate, and a grid electrode of the MOS transistor is suspended above a gate oxidation layer so as to form a cantilever beam structure. Electrode plates are designed below each cantilever beam gate. Pull-down voltage of the cantilever beam gate is designed to be equal to an absolute value of threshold voltage of the MOS transistor. When voltage between the cantilever beam gate and the electrode plates is less than the absolute value of the threshold voltage, the cantilever beam gate is suspended above the gate oxidation layer, and only when the voltage between the cantilever beam gate and the electrode plates reaches or is greater than the absolute value of the threshold voltage, the cantilever beam gate is pulled down to and attached to the gate oxidation layer. If the input end and the output end are different in level value at the time, the MOS transistor is conducted. The field intensity in the gate oxidation layer is low when the Si-based low leakage current cantilever beam gate CMOS transmission gate is in operation, so that the gate leakage current is reduced, and the power consumption is reduced effectively.
Description
Technical field
The present invention proposes silica-based low-leakage current cantilever beam grid cmos transmission gate, belong to the technical field of microelectromechanical systems.
Background technology
Along with the appearance of modern times various mobile portable equipment, the heat dispersion of electronic equipment and flying power face huge challenge.Meanwhile, along with the development of integrated circuit, the integrated level of chip is more and more higher, and the characteristic size of device constantly reduces, and the number of the metal-oxide-semiconductor that chip internal is integrated sharply increases, and clock frequency is also more and more higher.A large amount of metal-oxide-semiconductors, at very high operation at frequencies, causes the power consumption of chip constantly to increase.This and the requirement of modern electronic equipment to low-power consumption are contrary.Moreover, too high power consumption can make chip overheating, not only can reduce chip performance and also can shorten its useful life.For chip designer, the speed of chip and the area of silicon chip used are no longer only paid close attention in the design of chip.The power consumption of chip also becomes the major issue that chip designer must be concerned about.Low power dissipation design is more and more important in VLSI (very large scale integrated circuit) designs process.
The power consumption of common MOS transistor device mainly comprises two aspects, the dynamic power consumption that when referring to that metal-oxide-semiconductor works on the one hand, AC signal produces; And be the loss that leakage current causes on the other hand.And two kinds are mainly contained for leakage current, a kind of grid leakage current being grid voltage and bringing, leakage current time another kind of during cut-off between source and drain.And at present the research of MOS transistor device is focused mostly in the reduction to metal-oxide-semiconductor dynamic power consumption.Little to the research of the reduction of leakage current.Namely the present invention is a kind of silica-based low-leakage current cantilever beam grid cmos transmission gate with extremely low grid leakage current based on Si technological design.
Summary of the invention
Technical problem: the object of this invention is to provide a kind of silica-based low-leakage current cantilever beam grid cmos transmission gate and preparation method, when COMS transmission gate works, wishes that it is be 0 at the direct current of grid usually.And in fact, because the gate oxide of conventional MOS pipe is very thin, so the field intensity in gate oxide is very large, usually certain DC leakage current can be caused.Particularly in same cmos transmission gate, the voltage added by the grid of NMOS tube and PMOS is contrary, so just define current circuit between two grids.In large scale integrated circuit, the existence of this leakage current can increase the power consumption of transmission gate in work.And this leakage current is effectively reduced in the present invention.
Technical scheme: silica-based low-leakage current cantilever beam grid cmos transmission gate of the present invention is made up of cantilever beam grid NMOS tube and cantilever beam grid PMOS, cantilever beam grid NMOS tube and cantilever beam grid PMOS are connected in parallel, metal-oxide-semiconductor in this transmission gate is produced on P type Si substrate, its lead-in wire is all utilize Al to make, for the metal-oxide-semiconductor in transmission gate, its grid is suspended in above gate oxide, form cantilever beam grid structure, this cantilever beam Shan Mao district is produced on gate oxide, cantilever beam grid envisaged underneath has battery lead plate, the upper surface of battery lead plate is provided with the covering of gate oxide, the battery lead plate ground connection of cantilever beam grid NMOS tube, and the battery lead plate of cantilever beam grid PMOS connects power supply.
The threshold voltage designs of cantilever beam grid NMOS tube is just, the threshold voltage designs of cantilever beam grid PMOS is negative, the absolute value of the threshold voltage of two metal-oxide-semiconductors is designed to equal, the actuation voltage of cantilever beam grid is designed to the absolute value of the threshold voltage equaling metal-oxide-semiconductor, at work, the cantilever beam grid of cantilever beam grid NMOS tube are contrary with the signal that the cantilever beam grid of cantilever beam grid PMOS load, when transmission gate is opened, the cantilever beam grid of cantilever beam grid NMOS tube connect high level, the voltage of its cantilever beam grid and its lower electrode plate is greater than the absolute value of threshold voltage, so cantilever beam grid pull down on gate oxide, and the cantilever beam grid of cantilever beam grid PMOS connect low level, the voltage of its cantilever beam grid and its lower electrode plate is also greater than the absolute value of threshold voltage, so its cantilever beam grid also pull down on gate oxide, now transmission gate of the present invention and traditional cmos transmission gate similar, as long as export different with incoming level, two metal-oxide-semiconductors just can conducting, realize the transmission of level, and when transmission gate closes, situation is just the opposite, the cantilever beam grid of cantilever beam grid NMOS tube connect low level, the cantilever beam grid of cantilever beam grid PMOS connect high level, the cantilever beam grid of two metal-oxide-semiconductors float, now no matter input and output are in high level or low level, two metal-oxide-semiconductors are all cut-offs, so can not transmission level value, thus achieve the function of transmission gate.
When the voltage between cantilever beam grid and battery lead plate is less than the absolute value of threshold voltage, cantilever beam grid are the tops being suspended in gate oxide, and the voltage only between cantilever beam grid and battery lead plate is when reaching or surpassing the absolute value of threshold voltage, cantilever beam grid just can pull down to and be attached on gate oxide, if now input is different from the level value of output, then metal-oxide-semiconductor conducting, compared to traditional metal-oxide-semiconductor, the present invention is due to the design of cantilever beam grid, field intensity in gate oxide is less, therefore DC leakage current reduces greatly, thus effectively reduces power consumption.
The preparation method of silica-based low-leakage current cantilever beam grid cmos transmission gate of the present invention is as follows:
1) P type Si substrate is prepared;
2) initial oxidation, growth SiO
2layer, as the screen of doping;
3) photoetching SiO
2layer, carves N trap hand-hole;
4) N trap injects, and anneals in a nitrogen environment; After having annealed, at high temperature carry out dopant redistribution, form N trap;
5) whole oxide layers of silicon face are removed;
6) end oxide growth.The uniform oxide layer of one deck is grown, as resilient coating at smooth silicon face by thermal oxidation.
7) deposited silicon nitride, then photoetching and etch nitride silicon layer, remain with the silicon nitride in source region, and the silicon nitride of place is removed;
8) field oxidation.High-temperature thermal oxidation is carried out to silicon chip, grown required thick oxide layer in place;
9) remove silicon nitride and basal oxygen sheet, adopt dry etching technology by silicon chip surface silicon nitride and end oxygen all remove.
10) on silicon chip, apply one deck photoresist, photoetching and etching photoresist, remove the photoresist needing to make cantilever beam battery lead plate position.Then deposit one deck Al, removes the Al on photoresist and photoresist, forms battery lead plate;
11) gate oxidation is carried out.Carry out gate oxidation, form the high-quality oxide layer of one deck;
12) utilize CVD technology deposit spathic silicon, photoetching gate figure and polysilicon lead-in wire figure, by dry etching technology etch polysilicon, retain the polysilicon of the anchor zone position of cantilever beam.
13) form PMGI sacrifice layer by spin coating mode, then photoetching sacrifice layer, only retain the sacrifice layer below cantilever beam grid;
14) evaporation growth Al;
15) apply photoresist, retain the photoresist above cantilever beam grid;
16) anti-carve Al, form cantilever beam grid;
17) apply photoresist, photoetching also etches the hand-hole of boron, injects boron, forms the active area of cantilever beam grid PMOS;
18) apply photoresist, photoetching also etches the hand-hole of phosphorus, injects phosphorus, forms the active area of cantilever beam grid NMOS tube;
19) through hole and lead-in wire is made;
20) discharge polyimide sacrificial layer: developer solution soaks, remove the polyimide sacrificial layer under cantilever beam grid, deionized water soaks slightly, and absolute ethyl alcohol dewaters, and volatilizees, dry under normal temperature, forms the cantilever beam grid suspended.
In the present invention, the grid of metal-oxide-semiconductor is not directly be attached on gate oxide, but is suspended in the top of gate oxide, forms a cantilever beam structure.In the present invention, the threshold voltage designs of cantilever beam grid NMOS tube is just, the threshold voltage designs of cantilever beam grid PMOS is negative, and the absolute value of the threshold voltage of two metal-oxide-semiconductors is designed to identical.The actuation voltage of the cantilever beam grid of metal-oxide-semiconductor is designed to equal with the absolute value of the threshold voltage of metal-oxide-semiconductor.At work, the cantilever beam grid of cantilever beam grid NMOS tube are contrary with the signal that the cantilever beam grid of cantilever beam grid PMOS load.When transmission gate is opened, the cantilever beam grid of cantilever beam grid NMOS tube connect high level, the voltage of its cantilever beam grid and its lower electrode plate is greater than the absolute value of threshold voltage, so cantilever beam grid pull down on gate oxide, and the cantilever beam grid of cantilever beam grid PMOS connect low level, the voltage of its cantilever beam grid and its lower electrode plate is also greater than the absolute value of threshold voltage, so its cantilever beam grid also pull down on gate oxide, now transmission gate of the present invention and traditional cmos transmission gate similar, as long as export different with incoming level, two metal-oxide-semiconductors just can conducting, realize the transmission of level.And when transmission gate closes, situation is just the opposite, the cantilever beam grid of cantilever beam grid NMOS tube connect low level, the cantilever beam grid of cantilever beam grid PMOS connect high level, the cantilever beam grid of two metal-oxide-semiconductors suspend, now no matter input and output are in high level or low level, two metal-oxide-semiconductors are all cut-offs, so in metal-oxide-semiconductor work in the present invention, when voltage between cantilever beam grid and battery lead plate is less than the absolute value of threshold voltage, cantilever beam grid are the tops being suspended in gate oxide, and the voltage only between cantilever beam grid and battery lead plate is when reaching or surpassing the absolute value of threshold voltage, cantilever beam grid just can pull down to and be attached on gate oxide, if now input is different from the level value of output, then metal-oxide-semiconductor conducting.Compared to traditional metal-oxide-semiconductor, when the voltage of cantilever beam grid only between grid and battery lead plate of the metal-oxide-semiconductor in the present invention is more than or equal to the absolute value of threshold voltage, just can be attached on gate oxide, and be all suspend in other situations, so the field intensity in gate oxide is less, therefore DC leakage current also reduces greatly.
Beneficial effect: the field intensity of cantilever beam grid transmission gate of the present invention at work in gate oxide is less, effectively reduces grid leakage current.Thus the power consumption of the cantilever beam grid transmission gate in the present invention is effectively reduced.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the present invention's silica-based low-leakage current cantilever beam grid cmos transmission gate,
Fig. 2 is the vertical view of the present invention's silica-based low-leakage current cantilever beam grid cmos transmission gate,
Fig. 3 be Fig. 2 silica-based low-leakage current cantilever beam grid cmos transmission gate P-P ' to profile,
Fig. 4 be Fig. 2 silica-based low-leakage current cantilever beam grid cmos transmission gate A-A ' to profile,
Fig. 5 be Fig. 2 silica-based low-leakage current cantilever beam grid cmos transmission gate B-B ' to profile,
Figure comprises: cantilever beam grid NMOS tube 1, cantilever beam grid PMOS 2, P type Si substrate 3, lead-in wire 4, gate oxide 5, cantilever beam grid 6, anchor district 7, battery lead plate 8, N trap 9, cantilever beam grid PMOS active area 10, cantilever beam grid NMOS tube active area 11, through hole 12.
Embodiment
The present invention is made up of cantilever beam grid NMOS tube 1 and cantilever beam grid PMOS 2, and cantilever beam grid NMOS tube 1 and cantilever beam grid PMOS 2 are connected in parallel.The MOS of this transmission gate makes based on P type Si substrate 3, and its lead-in wire 4 utilizes Al to make.The grid of NMOS and PMOS in the present invention is the top being suspended in gate oxide 5, forms cantilever beam grid 6.The anchor district 7 of cantilever beam grid 6 utilizes polysilicon to be produced on gate oxide.In the below of each cantilever beam grid 6, devise two battery lead plates 8.There is the covering of gate oxide 5 top of battery lead plate 8.The battery lead plate 8 of cantilever beam grid NMOS tube 1 is ground connection, and the battery lead plate 8 of cantilever beam grid PMOS 2 connects power supply.
In the present invention, the grid of metal-oxide-semiconductor is not directly be attached on gate oxide 5, but is suspended in the top of gate oxide 5, forms cantilever beam grid 6.The threshold voltage designs of cantilever beam grid NMOS tube 1 is just, the threshold voltage designs of cantilever beam grid PMOS 2 is negative, and the absolute value of the threshold voltage of two metal-oxide-semiconductors is designed to equal.The actuation voltage of these cantilever beam grid 6 is designed to equal with the absolute value of the threshold voltage of metal-oxide-semiconductor.At work, the cantilever beam grid 6 of cantilever beam grid NMOS tube 1 are contrary with the signal that the cantilever beam grid 6 of cantilever beam grid PMOS 2 load.When transmission gate is opened, the cantilever beam grid 6 of cantilever beam grid NMOS tube 1 connect high level, its cantilever beam grid 6 and the voltage of its lower electrode plate 8 are greater than the absolute value of threshold voltage, so cantilever beam grid 6 pull down on gate oxide 5, and the cantilever beam grid 6 of cantilever beam grid PMOS 2 connect low level, its cantilever beam grid 6 and the voltage of its lower electrode plate 8 are also greater than the absolute value of threshold voltage, so its cantilever beam grid 6 also pull down on gate oxide 5, now transmission gate of the present invention and traditional cmos transmission gate similar, as long as export different with incoming level, two metal-oxide-semiconductors just can conducting, realize the transmission of level.And when transmission gate closes, situation is just the opposite, the cantilever beam grid 6 of cantilever beam grid NMOS tube 1 connect low level, the cantilever beam grid 6 of cantilever beam grid PMOS 2 connect high level, the cantilever beam grid 6 of two metal-oxide-semiconductors suspend, now no matter input and output are in high level or low level, and two metal-oxide-semiconductors are all cut-offs, so can not transmission level value.In metal-oxide-semiconductor work in the present invention, when voltage when between cantilever beam grid 6 and battery lead plate 8 is less than the absolute value of threshold voltage, cantilever beam grid 6 are the tops being suspended in gate oxide 5, and the voltage only between cantilever beam grid 6 and battery lead plate 8 is when reaching or surpassing the absolute value of threshold voltage, cantilever beam grid 6 just can pull down to and be attached on gate oxide, if now input is different from the level value of output, then metal-oxide-semiconductor conducting.Compared to traditional metal-oxide-semiconductor, the voltage of cantilever beam grid 6 only between cantilever beam grid and battery lead plate of the metal-oxide-semiconductor in the present invention is just attached on gate oxide 5 when being more than or equal to the absolute value of threshold voltage, and be all suspend in other situations, so the field intensity in gate oxide 5 is less, therefore DC leakage current also reduces greatly.
The preparation method of silica-based low-leakage current cantilever beam grid cmos transmission gate comprises following step:
1) P type Si substrate 3 is prepared;
2) initial oxidation, growth SiO
2layer, as the screen of doping;
3) photoetching SiO
2layer, carves N trap 9 hand-hole;
4) N trap 9 injects, and anneals in a nitrogen environment; After having annealed, at high temperature carry out dopant redistribution, form N trap 9;
5) whole oxide layers of silicon face are removed;
6) end oxide growth.The uniform oxide layer of one deck is grown, as resilient coating at smooth silicon face by thermal oxidation.
7) deposited silicon nitride, then photoetching and etch nitride silicon layer, remain with the silicon nitride in source region, and the silicon nitride of place is removed;
8) field oxidation.High-temperature thermal oxidation is carried out to silicon chip, grown required thick oxide layer in place;
9) remove silicon nitride and basal oxygen sheet, adopt dry etching technology by silicon chip surface silicon nitride and end oxygen all remove.
10) on silicon chip, apply one deck photoresist, photoetching and etching photoresist, remove the photoresist needing to make battery lead plate 8 position.Then deposit one deck Al, removes the Al on photoresist and photoresist, forms battery lead plate;
11) gate oxidation is carried out.Form the high-quality oxide layer of one deck;
12) utilize CVD technology deposit spathic silicon, photoetching gate figure and polysilicon lead-in wire figure, by dry etching technology etch polysilicon, retain the polysilicon of the position, anchor district 7 of cantilever beam grid 6.
13) form PMGI sacrifice layer by spin coating mode, then photoetching sacrifice layer, only retain the sacrifice layer below cantilever beam grid 6;
14) evaporation growth Al;
15) apply photoresist, retain the photoresist above cantilever beam grid 6;
16) anti-carve Al, form cantilever beam grid 6;
17) apply photoresist, photoetching also etches the hand-hole of boron, injects boron, forms the active area 10 of cantilever beam grid PMOS 2;
18) apply photoresist, photoetching also etches the hand-hole of phosphorus, injects phosphorus, forms the active area 11 of cantilever beam grid NMOS tube 1;
19) through hole 12 and lead-in wire 4 is made;
20) discharge polyimide sacrificial layer: developer solution soaks, remove the polyimide sacrificial layer under cantilever beam grid 6, deionized water soaks slightly, and absolute ethyl alcohol dewaters, and volatilizees, dry under normal temperature, forms the cantilever beam grid 6 suspended.
Difference with the prior art of the present invention is:
The present invention effectively can reduce metal-oxide-semiconductor grid leakage current operationally, reduces power consumption.Transmission gate in the present invention is made up of cantilever beam grid NMOS tube and cantilever beam grid PMOS.Cantilever beam grid metal-oxide-semiconductor and the maximum difference of traditional metal-oxide-semiconductor are, the grid of cantilever beam grid metal-oxide-semiconductor is the top being suspended in oxide layer, form cantilever beam structure.The battery lead plate of cantilever beam grid NMOS tube is ground connection, and the battery lead plate of cantilever beam grid PMOS connects power supply.The actuation voltage of cantilever beam grid is designed to the absolute value of the threshold voltage equaling metal-oxide-semiconductor.When voltage when between cantilever beam grid and battery lead plate is less than the absolute value of the threshold voltage of metal-oxide-semiconductor, cantilever beam grid and the oxide layer below it have certain gap.And when only having the voltage when between cantilever beam grid and battery lead plate to be equal to or greater than the absolute value of the threshold voltage of metal-oxide-semiconductor, cantilever beam grid just can pulled down in attached oxide layer thereunder.So, when transmission gate in the present invention works, when the voltage of cantilever beam grid only between itself and battery lead plate is more than or equal to the absolute value of threshold voltage, just be attached on gate oxide, and be all suspend in other situations, field intensity in gate oxide is less, so the AC and DC leakage current of grid will reduce greatly, thus power consumption is effectively lowered.
Namely the structure meeting above condition is considered as silica-based low-leakage current cantilever beam grid cmos transmission gate of the present invention.
Claims (2)
1. a silica-based low-leakage current cantilever beam grid cmos transmission gate, it is characterized in that this transmission gate is made up of cantilever beam grid NMOS tube (1) and cantilever beam grid PMOS (2), cantilever beam grid NMOS tube (1) and cantilever beam grid PMOS (2) are connected in parallel, metal-oxide-semiconductor in this transmission gate is produced on P type Si substrate (3), its lead-in wire (4) is all utilize Al to make, for the metal-oxide-semiconductor in transmission gate, its grid is suspended in gate oxide (5) top, form cantilever beam grid structure, the anchor district (7) of this cantilever beam grid (6) is produced on gate oxide (5), cantilever beam grid (6) envisaged underneath has battery lead plate (8), the upper surface of battery lead plate (8) is provided with the covering of gate oxide (5), battery lead plate (8) ground connection of cantilever beam grid NMOS tube (1), and the battery lead plate (8) of cantilever beam grid PMOS (2) connects power supply.
2. a preparation method for silica-based low-leakage current cantilever beam grid cmos transmission gate as claimed in claim 1, is characterized in that the preparation method of this transmission gate is as follows:
1. prepare P type Si substrate;
2. initial oxidation, growth SiO
2layer, as the screen of doping;
3. photoetching SiO
2layer, carves N trap hand-hole;
4.N trap injects, and anneals in a nitrogen environment; After having annealed, at high temperature carry out dopant redistribution, form N trap;
5. remove whole oxide layers of silicon face;
6. end oxide growth.The uniform oxide layer of one deck is grown, as resilient coating at smooth silicon face by thermal oxidation;
7. deposited silicon nitride, then photoetching and etch nitride silicon layer, remain with the silicon nitride in source region, and the silicon nitride of place is removed;
8. an oxidation.High-temperature thermal oxidation is carried out to silicon chip, grown required thick oxide layer in place;
9. remove silicon nitride and basal oxygen sheet, adopt dry etching technology by silicon chip surface silicon nitride and end oxygen all remove;
10. on silicon chip, apply one deck photoresist, photoetching and etching photoresist, remove the photoresist needing to make cantilever beam battery lead plate position.Then deposit one deck Al, removes the Al on photoresist and photoresist, forms battery lead plate;
11. carry out gate oxidation.Carry out gate oxidation, form the high-quality oxide layer of one deck;
12. utilize CVD technology deposit spathic silicon, and photoetching gate figure and polysilicon lead-in wire figure, by dry etching technology etch polysilicon, retain the polysilicon of the anchor zone position of cantilever beam;
13. form PMGI sacrifice layer by spin coating mode, then photoetching sacrifice layer, only retain the sacrifice layer below cantilever beam grid;
14. evaporation growth Al;
15. coating photoresists, retain the photoresist above cantilever beam grid;
16. anti-carve Al, form cantilever beam grid;
17. coating photoresists, photoetching also etches the hand-hole of boron, injects boron, forms the active area of cantilever beam grid PMOS;
18. coating photoresists, photoetching also etches the hand-hole of phosphorus, injects phosphorus, forms the active area of cantilever beam grid NMOS tube;
19. make through hole and lead-in wire;
20. release polyimide sacrificial layer: developer solution soaks, and remove the polyimide sacrificial layer under cantilever beam grid, deionized water soaks slightly, and absolute ethyl alcohol dewaters, and volatilizees, dry under normal temperature, forms the cantilever beam grid suspended.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107181483A (en) * | 2017-06-05 | 2017-09-19 | 北京锐达芯集成电路设计有限责任公司 | Radioresistance cmos transmission gate and the cmos circuit comprising it |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2192106A (en) * | 1986-05-21 | 1987-12-31 | Clarion Co Ltd | TTL to CMOS interface using clocked latch |
| EP0339737A1 (en) * | 1988-04-29 | 1989-11-02 | Koninklijke Philips Electronics N.V. | Integrated circuit having combinatorial logic functionality and provided with transmission gates having a low threshold voltage |
| CN101431330A (en) * | 2008-11-25 | 2009-05-13 | 中国科学院微电子研究所 | NOR gate logic circuit and its forming method |
| CN102385001A (en) * | 2011-08-11 | 2012-03-21 | 东南大学 | Three-channel micro-mechanical cantilever beam indirect-type microwave power sensor and preparation method |
| CN102735934A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical gallium arsenide-based cantilever beam and detection method |
| CN102735935A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical silicon-based cantilever beam and detection method |
-
2015
- 2015-07-01 CN CN201510378250.3A patent/CN104967437B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2192106A (en) * | 1986-05-21 | 1987-12-31 | Clarion Co Ltd | TTL to CMOS interface using clocked latch |
| EP0339737A1 (en) * | 1988-04-29 | 1989-11-02 | Koninklijke Philips Electronics N.V. | Integrated circuit having combinatorial logic functionality and provided with transmission gates having a low threshold voltage |
| CN101431330A (en) * | 2008-11-25 | 2009-05-13 | 中国科学院微电子研究所 | NOR gate logic circuit and its forming method |
| CN102385001A (en) * | 2011-08-11 | 2012-03-21 | 东南大学 | Three-channel micro-mechanical cantilever beam indirect-type microwave power sensor and preparation method |
| CN102735934A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical gallium arsenide-based cantilever beam and detection method |
| CN102735935A (en) * | 2012-06-20 | 2012-10-17 | 东南大学 | Phase detector based on micro-mechanical silicon-based cantilever beam and detection method |
Non-Patent Citations (1)
| Title |
|---|
| 王克义: "《数字电子技术基础》", 27 February 2013, 清华大学出版社 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107181483A (en) * | 2017-06-05 | 2017-09-19 | 北京锐达芯集成电路设计有限责任公司 | Radioresistance cmos transmission gate and the cmos circuit comprising it |
| CN107181483B (en) * | 2017-06-05 | 2023-10-31 | 北京锐达芯集成电路设计有限责任公司 | Radiation-resistant CMOS transmission gate and CMOS circuit comprising same |
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| CN104967437B (en) | 2018-02-06 |
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