GB2192106A

GB2192106A - TTL to CMOS interface using clocked latch

Info

Publication number: GB2192106A
Application number: GB08711208A
Authority: GB
Inventors: Masaaki Harada
Original assignee: Clarion Co Ltd
Current assignee: Faurecia Clarion Electronics Co Ltd
Priority date: 1986-05-21
Filing date: 1987-05-12
Publication date: 1987-12-31
Also published as: FR2599199A1; JPS62272722A; DE3715655A1; GB8711208D0

Description

1 GB 2 192 106 A 1

SPECIFICATION MOS ICs, whose feature is that the electric power TTL logic level CIVIOS input buffer circuit consumption is low and in particular it is zero, when arrangement the input level is fixed.

According to this invention there is provided a This invention relates to a TTL logic level CMOS 70 TTL logic level CMOS input buffer circuit input buffer circuit arrangement. arrangement comprising a first transmission gate In a prior art CMOS inverter as shown in Figure 5 controlled by gate signals having mutually different of the drawings consisting of a p conductivity type poiarities; a first inverter conneetd to the output of MOS transistor and an n conductivity type MOS the first transmission gate, the output of the first transistor (herein-below abbreviated to pMOS AND 75 inverter providing an output of the arrangement, nMOS, respectively), the logic threshold level is and a feedback path between the output and the adjusted to the TTL level (1AV) and a TTL input of the first inverter, the feedback path compatible input buffer was formed. In order to comprising a second inverter and a second lower the logic threshold level from the CMOS level transmission gate controlled by said gate signals, (2.5V) to the TTL level, it is necessary to increase the 80 the first transmission gate being open when the ratio of the channel width wn of the nMOS to the second transmission gate is closed and vice versa.

channel width wp of the pMOS (wn/wp) and to This invention provides a TTL logic level CMOS reduce the on-resistance of the nMOS. Atthis time a input buffer circuit arrangment, for which it is difference is produced between lp and In, which are possible to specify an input timing for which no the currents flowing through the pMOS and the 85 static electric current consumption is produced.

nMOS, respectively, at their on-state (1p<in), which In the TTL logic level CMOS input buffer circuit gives the disadvantage that the symmetry OftPLH arrangement of this invention the input is and tPHL is lost (tPLH<-tPHL). transformed from the TTL level to the CMOS level Usually this difference between tPLH and tPHL is by adding a second inverter for feedback of a first compensated by connecting another similar inverter 90 inverter responding to the TTL input through a first thereafter. transmission gate, and thus static electric current A disadvantage of such an arrangement is that consumption is eliminated. A second transmission there is a static electric current consumption for a gate is inserted so that the TTL input is not wire TTL "H" input. The static electric current connected to the second inverter.

consumption varies, depending on the size of the 95 This invention will now be described by way of input buffer and the voltage of TTL "H", and when example with reference to the drawings, in which:

the voltage of TTL "H" is low (e.g. 2AV), it is about 1 Figure 1 is a circuit diagram of a TTL logic level to 2 mA. As indicated in Figures 6A to 6D of the CMOS input buffer circuit arrangement according to drawings, when the input is at the CMOS level, for a this invention; "H" input (---U' input) the gate voltage of the nMOS 100 Figure 2 shows waveforms of signals used for (pMOS) is higherthan the threshold voltage and controlling the circuit arrangement of Figure 1; thus the nMOS (pMOS) is in the on-state. On the Figure 3 shows an application of the circuit contrary, the gate voltage of the pMOS (nMOS) is arrangement of this invention to a data input of a lower than the threshold voltage and thus the pMOS counter; (nMOS) is in the off-state. In this way either one of 105 Figure 4 shows an application of the circuit of this the transistors is in the off-state. Figure 6A indicates invention to a data latch; the response of the CMOS input buffer when the Figure 5 is a circuit diagram of a prior art CMOS input is at CMOS "L"; Figure 613 the same when the input buffer; and input is at CMOS "H"; Figure 6C the same when the Figures 6Ato 6D show responses of the CMOS input is at TTL "L"; and Figure 6C the same when 110 input buffer shown in Figure 5.

the input is at TTL "H", in which V8 indicates the Figure 1 is a circuit diagram of a TTL logic level gate voltage; Vthp the threshold voltage of the pMOS CMOS input buffer circuit arrangement according to (which is about -0.7 to -1.OV); and Vthn the this invention. In this arrangement, pMOS 1 and threshold voltage of the nMOS (which is about 0.7 to nMOS 1 are a p conductivity type MOS transistor 1.OV). For this reason, for a CMOS level input no 115 and an n conductivity type MOS transistor, current path connecting the power supply and the respectively, and together constitute a first inverter ground is formed, and therefore no static current INV1, whose threshold level is adjusted to the TTL consumption is produced. However, in the case level by regulating their channel width so that the where the input is at the TTL level, when the input is on-resistance of nMOS 1 is small. pMOS 4 and "H", since the voltage of TTL---Wis lower than the 120 nMOS 4 area p conductivity type MOS transistor voltage of the power supply by several volts (when and an n conductivity type MOS transistor, the voltage of the power supply is 5V, TTL respectively, and together constitute a second "H"=2.4-3.4V), the gate voltage of the pMOS, inverter INV.2. pMOS 2, pMOS 3 and nMOS 2,nMOS which is in the off-state forthe CMOS level, is also 3 are p conductivity type MOS transistors and n higher than the threshold value and thus it is in the 125 conductivity type MOS transistors, respectively.

on-state. At this time, since both the pMOS and the pMOS 2, nMOS 2, and pMOS 3, nMOS 3 constitute nMOS are in the on-state, a current path connecting first and second transmission gates TG1 and TG2, the power supply and ground is formed, and respectively.

therefore a static current consumption is produced. Figure 2 shows waveforms of control signals (p This is one of the most serious disadvantages for 130 and";for controlling the circuit arrangement of 2 GB 2 192 106 A 2 Figure 1. In the drawing t5 represents the least.set up gate (TG,) in Figure 1; TG2-1, TG2-2, TG2-3, are time; th the least hold time; and t the data read-in transmission gates similar to the second time. 65 transmission gate (TG2); INV1-1, INV1-2, INV1-3, are When the control signal 1) is "H- (; is 'V'), the inverters similar to the first inverter (INV1); and first transmission gate TG1 is in the on-state and the INVA, INV2-2, INV2- 3, are inverters similar to the second transmission gate TG2 1S in the off-state. second inverter (INV2).

Therefore the path between the output NODE 1 of If such a data latch was constructed according to the transmission gate TG1 and the inputterminal is 70 prior art techniques, the propagation speed of the conductive. The inverter INV, reads-in the TTL logic data would be small, because the circuit would have level applied to the input terminal and outputs the CMOS level connected through an input buffer inverted signal at its output NODE 2 with the CMOS having TTL level. Further, since the input buffer logic level. At this time the inverter INV, has a static would have multiple fan-outs, a relatively large size electric current consumption forthe TTL logic level 75 would result, requiring a relatively large chip size "H". The inverter INV2 outputs the inverted signal resulting in high static electric current consumption.

with respect to that at NODE 2, i.e. the same logic With the arrangement of Figure 4, it is possible to state as that at NODE 1, the CMOS logic level, at its reduce the area of the chip, to shorten the delay time output NODE 3. of the propagation and to decrease static electric When the control signal 4) is "L" ( is "H"), the 80 current consumption.

first transmission gate TG1 is in the off-state and the As described above, with arrangements according second transmission gate TB2 is in the on-state. to this invention, static electric current consumption Therefore NODE 1 is electrically separated from the in a TTL logic level CMOS input buffer circuit input terminal and the path between the output arrangement can be eliminated.

NODE 3 of the transmission gate TG2 and the input 85 The pMOS threshold value can be made higher terminal becomes conductive. As a result, the than that of other pMOS in order to decrease static output signal at NODE 1 is transformed from the TTL electric current consumption. However, with level to the CMOS level by the inverter I NV2, the arrangements according to this invention it is not logic state remaining as it is. Atthis time, since necessary to complicate the wafer process by either one of pMOS 1 and nMOS 1 is always in the 90 adopting such a measure, and thus it is possible to off-state in the inverter INV1, no current path is expect reduction of the cost and increase of formed and thus there is not static electric current production yield.

consumption.

Claims

In this way it is possible to eliminate the static CLAIMS electric current

consumption in the TTL logic level 95 1. A TTL logic level CMOS input buffer circuit CMOS input buffer circuit arrangement by making 1) arrangement comprising a first transmission gate "H" ((p "L") only during the data read-in time and controlled by gate signals having mutually different otherwise (p "L" ( "H") by means of the signals polarities; a first inverter connected to the output of shown in Figure
2. the first transmission gate, the output of the first Figure 3 shows an application of the circuit 100 inverter providing an output of the arrangement; arrangement shown in Figure 1 to a data circuit and a feed back path between the output and the input circuit of a counter. In the drawing, TGAI, input of the first inverter, the feedback path TGB1, TGC1, TG1), are transmission gates similar to comprising a second inverter and a second the first transmission gate (TG1) in Figure 1; TGA2, transmission gate controlled by said gate signals, TGB2, TGC2, TGD2 are transmission gates similar to 105 the first transmission gate being open when the the second transmission gate (TG2); INVA1, INVI31, second transmission gate is closed and vice vera.

INVC1, INVD, are inverters similar to the first 2. A circuit arrangement as claimed in Claim 1, in inverter (INV1); and INVA2, INVB2, INVC2, INVD2 are which said first inverter comprises a p conductivity inverters similar to the second inverter (INV2). For type MOS transistor and an n conductivity type the counter, since the timing of the data input is 110 MOS transistor, whose channel widths are such that specified by a LOAD signal, this can be used as the the on-resistance of said n conductivity type MOS control signal (4),) for the input circuit. transistor is small and whose logic threshold value When LOAD is "H", the circuit arrangement is is at the TTL level, and said second inverter consists electrically isolated from the input terminal, and the of a p conductivity type MOS transistor and an n data is held at the CMOS level. In this way static 115 conductivity type MOS transistor having a logic electric current consumption is avoided. threshold value at the CMOS level.

Although in this example external signals (LOAD)
3. A circuit arrangement as claimed in Claim 1 or are used as control signals, it is also possible to use Claim 2, in which each of said first and second signals generated within the counter such as transmission gates comprises a p conductivity type CARRY, etc. 120 MOS transistor and an n conductivity type MOS Figure 4 shows a data latch circuit comprising transistor.

arrangements as shown in Figure 1 connected in
4. A circuit arrangement substantially as parallel. In the drawing, TG1-1, TG1-2, TG1-3, are hereinbefore described with reference to Figures 1 transmission gates similar to the first transmission and 2, Figure 3 or Figure 4 of the drawings.

Printed for Her Majesty's Stationery Office by Courier Press, Leamington Spa, 12187. Demand No. 8991685. Published by the Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.