CN102403273B - Method for forming thick grid oxide layer in SONOS (silicon, oxide film, nitride film, oxide film and silicon) manufacturing process - Google Patents
Method for forming thick grid oxide layer in SONOS (silicon, oxide film, nitride film, oxide film and silicon) manufacturing process Download PDFInfo
- Publication number
- CN102403273B CN102403273B CN201010279848.4A CN201010279848A CN102403273B CN 102403273 B CN102403273 B CN 102403273B CN 201010279848 A CN201010279848 A CN 201010279848A CN 102403273 B CN102403273 B CN 102403273B
- Authority
- CN
- China
- Prior art keywords
- film
- sonos
- voltage
- oxide
- grid oxic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a method for forming thick grid oxide layer in SONOS (silicon, oxide film, nitride film, oxide film and silicon) manufacturing process, which includes steps of firstly, implanting a high-voltage metal-oxide semiconductor, driving in, annealing and field oxidizing, secondly, implanting a low-voltage CMOS (complementary metal oxide semiconductor) and adjusting the implantation, thirdly, implanting and corroding SONOS nonvolatile storage groove windows, fourthly, forming ON (oxide/nitride) films, fifthly, removing the ON films in a high-voltage device grid area to lead a silicon substrate to be exposed, sixthly, oxidizing the ON films to form ONO (oxide/nitride/oxide) films and forming a high-voltage grid oxide layer, seventhly, removing the ON films in a low-voltage CMOS area to lead the silicon substrate to be exposed and protecting the high-voltage grid oxide layer by photoresist during etching, and eighthly, forming a low-voltage grid oxide layer. Silicon consumption of the low-voltage device and nonvolatile storage device area during oxidizing of the high-voltage grid can be effectively avoided by the method, and thereby changes of electrical characteristics and reliability can be effectively reduced.
Description
Technical field
The present invention relates to a kind of ic manufacturing technology, be specifically related to a kind of SONOS non-volatility memorizer manufacturing technology.
Background technology
Along with the development of integrated circuit, system-on-a-chip is integrated becomes trend.This just needs the intelligent control circuit simultaneously having MCU on one chip, non-volatile memory circuit and simulation or high-tension circuit.
At SONOS(silicon/oxide-film/nitride film/oxide-film/silicon) in non-volatility memorizer manufacturing process, by adding high-voltage metal oxide semiconductor device and analogue device can provide in same set of technique: logic, non-volatility memorizer, the device such as high pressure and simulation.For system-on-a-chip integrated circuit (IC) design provides necessary condition.
But in the technique of reality, the thick grid oxic horizon of high tension apparatus can introduce extra surface silicon consumption, thus serious low pressure and SONOS non-volatility memorizer electrical characteristics and reliability performance is caused to change.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of method of grow thick grid oxic horizon in SONOS non-volatility memorizer manufacturing process, it can avoid the silicon consumption in high pressure gate oxidation process mesolow device and non-volatile memory device region, thus effectively reduces electrical characteristics and reliability performance change.
In order to solve above technical problem, the invention provides a kind of method of grow thick grid oxic horizon in SONOS non-volatility memorizer manufacturing process; Comprise the following steps:
Step one, injection form high-voltage metal oxide semiconductor device, push away trap and annealing and place and are oxidized;
Step 2, injection form the low voltage CMOS trap and cut-in voltage adjustment injection that are used for logical circuit;
Step 3, injection and corrosion SONOS non-volatility memorizer raceway groove window;
Step 4, growth ON film;
Step 5, the ON film in high-voltage device grate region to be removed, expose silicon substrate;
Step 6, oxidation ON film form ONO film, and grow high pressure grid oxic horizon;
Step 7, the ONO film in low voltage CMOS region to be removed, expose silicon substrate, in etching process, utilize photoresist to protect high pressure grid oxic horizon simultaneously;
Step 8, growth low voltage gate oxide layer.
Beneficial effect of the present invention is: the ONO film (oxide-film/nitride film/oxide-film) making charge storage in non-volatile memory device covers the region beyond high-voltage device grate, effectively can stop the diffusion of oxygen in the thermal oxidation of high pressure grid oxic horizon.Thus effectively avoid the silicon consumption in high pressure gate oxidation process mesolow device and non-volatile memory device region, thus effectively reduce electrical characteristics and reliability performance change
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
Fig. 1 is in method described in the embodiment of the present invention, and high tension apparatus is relevant to be injected, and pushes away the schematic diagram of trap and annealing process and place oxidation step;
Fig. 2 is in method described in the embodiment of the present invention, and the injection of low voltage CMOS trap and cut-in voltage of being correlated with regulate the schematic diagram of implantation step;
Fig. 3 is in method described in the embodiment of the present invention, the schematic diagram of the injection of SONOS non-volatility memorizer raceway groove window and corrosion step;
Fig. 4 is in method described in the embodiment of the present invention, the schematic diagram of ON thin film growth step;
Fig. 5 is in method described in the embodiment of the present invention, utilizes photoetching and dry plasma corrosion to add the schematic diagram that wet corrosion technique removes the ON films Step in high-voltage device grate region;
Fig. 6 is in method described in the embodiment of the present invention, utilizes the method for thermal oxidation to be oxidized ON film and forms ONO film and the schematic diagram growing high pressure grid oxic horizon step;
Fig. 7 is in method described in the embodiment of the present invention, utilizes photoetching and dry plasma corrosion to add the schematic diagram that wet corrosion technique removes the ONO films Step in low voltage CMOS region;
Fig. 8 is in method described in the embodiment of the present invention, utilizes the schematic diagram of the method growth low voltage gate oxide layer step of thermal oxidation;
Fig. 9 is method flow diagram described in the embodiment of the present invention.
Embodiment
The present invention is a kind of method grown in the non-volatility memorizer manufacturing process of SONOS structure (silicon/oxide-film/nitride film/oxide-film/silicon) for the thick grid oxic horizon of high-voltage metal oxide semiconductor device.The thickness of thick grid oxic horizon of the present invention is that 200 dusts are to 1500 dusts.It utilizes in non-volatile memory device oxide-film/nitride film/oxide-film of making charge storage as the thick grid oxic horizon of high pressure hard mask used.This method can avoid the silicon consumption in high pressure gate oxidation process mesolow device and non-volatile memory device region, thus effectively reduces electrical characteristics and reliability performance change.As shown in Figure 9, idiographic flow is as follows:
(1) as shown in Figure 1, inject and form high-voltage metal oxide semiconductor device, push away trap and annealing and place and be oxidized.
(2) as shown in Figure 2, low voltage CMOS trap injects and cut-in voltage adjustment injection of being correlated with.
(3) as shown in Figure 3, SONOS non-volatility memorizer raceway groove window injects and corrosion.
(4) as shown in Figure 4, oxide-film/nitride film ON film growth: the method that can adopt a secondary growth or repeatedly grow.
(5) as shown in Figure 5, the ON film in high-voltage device grate region is removed by the method utilizing photoetching and dry plasma corrosion to add wet etching, exposes silicon substrate.
(6) as shown in Figure 6, utilize the method for thermal oxidation to be oxidized ON film form ONO film and grow high pressure grid oxic horizon.
(7) as shown in Figure 7, the oxide-film/nitride film in low voltage CMOS region/oxide-film ONO film is removed by the method utilizing photoetching and dry plasma corrosion to add wet etching, exposes silicon substrate.In etching process, utilize photoresist to protect high pressure grid oxic horizon simultaneously.
(8) the method growth low voltage gate oxide layer of thermal oxidation as shown in Figure 8, is utilized.
In the present invention, because the ONO film (oxide-film/nitride film/oxide-film) making charge storage in non-volatile memory device covers the region beyond high-voltage device grate, in the thermal oxidation of high pressure grid oxic horizon, the diffusion of oxygen can effectively be stoped.Thus effectively avoid the silicon consumption in high pressure gate oxidation process mesolow device and non-volatile memory device region, thus effectively reduce electrical characteristics and reliability performance change.Described high pressure is that operating voltage is greater than 8 volts, and described low pressure is that operating voltage is lower than 8 volts.
The present invention is not limited to execution mode discussed above.Above the description of embodiment is intended to describe and the technical scheme that the present invention relates to being described.Based on the present invention enlightenment apparent conversion or substitute also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, can apply numerous embodiments of the present invention and multiple alternative to reach object of the present invention to make those of ordinary skill in the art.
Claims (6)
1. the method for grow thick grid oxic horizon in SONOS manufacturing process, is characterized in that, comprise the following steps:
Step one, injection form high-voltage metal oxide semiconductor device, push away trap and annealing and place and are oxidized;
Step 2, injection form the low voltage CMOS trap and cut-in voltage adjustment injection that are used for logical circuit;
Step 3, injection and corrosion SONOS non-volatility memorizer raceway groove window;
Step 4, growth ON film;
Step 5, the ON film in high-voltage device grate region to be removed, expose silicon substrate;
Step 6, oxidation ON film form ONO film, and synchronous growth goes out high pressure grid oxic horizon;
Step 7, the ONO film in low voltage CMOS region to be removed, expose silicon substrate, in etching process, utilize photoresist to protect high pressure grid oxic horizon simultaneously;
Step 8, growth low voltage gate oxide layer.
2. the method for grow thick grid oxic horizon in SONOS manufacturing process as claimed in claim 1, is characterized in that, the method growth ON film that can adopt a secondary growth in described step 4 or repeatedly grow.
3. the method for grow thick grid oxic horizon in SONOS manufacturing process as claimed in claim 1, it is characterized in that, in described step 5, the ON film in high-voltage device grate region is removed by the method utilizing photoetching and dry plasma corrosion to add wet etching, exposes silicon substrate.
4. the method for grow thick grid oxic horizon in SONOS manufacturing process as claimed in claim 1, is characterized in that, in described step 6, utilizes the method oxidation ON film of thermal oxidation to form ONO film, and utilizes this technique synchronously to form high pressure grid oxic horizon.
5. the method for grow thick grid oxic horizon in SONOS manufacturing process as claimed in claim 1, it is characterized in that, in described step 7, the ONO film in low voltage CMOS region is removed by the method utilizing photoetching and dry plasma corrosion to add wet etching, exposes silicon substrate.
6. the method for grow thick grid oxic horizon in SONOS manufacturing process as claimed in claim 1, is characterized in that, in described step 8, utilizes the method growth low voltage gate oxide layer of thermal oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010279848.4A CN102403273B (en) | 2010-09-14 | 2010-09-14 | Method for forming thick grid oxide layer in SONOS (silicon, oxide film, nitride film, oxide film and silicon) manufacturing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010279848.4A CN102403273B (en) | 2010-09-14 | 2010-09-14 | Method for forming thick grid oxide layer in SONOS (silicon, oxide film, nitride film, oxide film and silicon) manufacturing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102403273A CN102403273A (en) | 2012-04-04 |
| CN102403273B true CN102403273B (en) | 2015-02-04 |
Family
ID=45885343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010279848.4A Active CN102403273B (en) | 2010-09-14 | 2010-09-14 | Method for forming thick grid oxide layer in SONOS (silicon, oxide film, nitride film, oxide film and silicon) manufacturing process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102403273B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106129011A (en) * | 2016-09-27 | 2016-11-16 | 上海华力微电子有限公司 | A kind of method improving SONOS structure embedded flash memory performance |
| CN106298680A (en) * | 2016-10-24 | 2017-01-04 | 上海华力微电子有限公司 | The manufacture method of SONOS structure embedded flash memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6689653B1 (en) * | 2003-06-18 | 2004-02-10 | Chartered Semiconductor Manufacturing Ltd. | Method of preserving the top oxide of an ONO dielectric layer via use of a capping material |
| CN101770989A (en) * | 2008-12-30 | 2010-07-07 | 华邦电子股份有限公司 | Forming method of semiconductor structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100437451B1 (en) * | 2002-05-07 | 2004-06-23 | 삼성전자주식회사 | Method Of Fabricating Trap-type Nonvolatile Memory Device |
-
2010
- 2010-09-14 CN CN201010279848.4A patent/CN102403273B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6689653B1 (en) * | 2003-06-18 | 2004-02-10 | Chartered Semiconductor Manufacturing Ltd. | Method of preserving the top oxide of an ONO dielectric layer via use of a capping material |
| CN101770989A (en) * | 2008-12-30 | 2010-07-07 | 华邦电子股份有限公司 | Forming method of semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102403273A (en) | 2012-04-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104137239B (en) | The manufacture method of nonvolatile semiconductor memory and nonvolatile semiconductor memory | |
| CN104716098A (en) | Method for manufacturing flash memory | |
| CN102386140B (en) | Method for developing thick gate oxide integrity layer in manufacturing process of silicon oxide nitride oxide semiconductor (SONOS) nonvolatile memory | |
| CN102403273B (en) | Method for forming thick grid oxide layer in SONOS (silicon, oxide film, nitride film, oxide film and silicon) manufacturing process | |
| CN102104025B (en) | Method for manufacturing gate oxide layer of EEPROM and gate oxide layer manufactured thereby | |
| CN101533776A (en) | Method for fabricating semiconductor memory device | |
| US9312378B2 (en) | Transistor device | |
| US10177040B2 (en) | Manufacturing of FET devices having lightly doped drain and source regions | |
| CN103367255A (en) | Manufacture method of multiple-time programmable silicon-oxide-nitride-oxide-silicon | |
| KR100673205B1 (en) | Method of manufacturing in flash memory device | |
| CN115881524A (en) | Embedded flash memory, embedded flash memory grid and preparation method | |
| CN103137453B (en) | Growth is used for the method for the thick grid oxic horizon of high-voltage metal oxide semiconductor device | |
| CN102593055B (en) | Manufacturing method of high-voltage device integrated circuit | |
| CN100550305C (en) | Flash memory device | |
| CN102446851B (en) | Method for embedding high-voltage device in silicon oxide-nitride-oxide semiconductor (SONOS) nonvolatile memory process | |
| CN104952804B (en) | A method of making embedded flash memory | |
| CN102446850B (en) | Method for embedding high-voltage apparatus in SONOS (silicon oxide nitride oxide semiconductor) nonvolatile memory technology | |
| US20120261740A1 (en) | Flash memory and method for fabricating the same | |
| CN103258797B (en) | The manufacture method of separate gate flash memory unit | |
| CN101447423A (en) | Manufacturing method for semiconductor device | |
| CN108511450A (en) | The forming method and peripheral circuit structure of the threshold adjustment layer of memory peripheral circuit | |
| CN101770944B (en) | Manufacture method of semiconductor device grid electrode | |
| CN109166804A (en) | The preparation method of zero threshold voltage NMOS | |
| JPS5982770A (en) | Semiconductor memory | |
| TW454343B (en) | Process for making high density mask ROM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |