CN103632949B - The forming method of the hot oxygen medium layer of the inter polysilicon of groove type double-layer grid MOS - Google Patents
The forming method of the hot oxygen medium layer of the inter polysilicon of groove type double-layer grid MOS Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 92
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 92
- 238000000034 method Methods 0.000 title claims abstract description 47
- 229910052760 oxygen Inorganic materials 0.000 title claims abstract description 37
- 239000001301 oxygen Substances 0.000 title claims abstract description 37
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title claims abstract description 36
- 150000004767 nitrides Chemical class 0.000 claims abstract description 49
- 238000005530 etching Methods 0.000 claims abstract description 40
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000000206 photolithography Methods 0.000 claims abstract description 9
- 230000008021 deposition Effects 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 claims abstract description 6
- 238000006263 metalation reaction Methods 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 18
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 140
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000011241 protective layer Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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Abstract
本发明公开了一种沟槽型双层栅MOS的多晶硅间的热氧介质层的形成方法,包括步骤:1)生长第一氮化膜;2)沟槽刻蚀;3)生长介质层;4)生长第一层多晶硅;5)第一层多晶硅第一步反刻蚀;6)第一层多晶硅光刻及第二步反刻蚀,并去除第一层多晶硅上方的沟槽侧壁介质层;7)淀积第二氮化膜后,刻蚀,露出第一层多晶硅;8)生长热氧介质层;9)去除氮化膜;10)栅极氧化层生长;11)第二层多晶硅淀积与反刻蚀;12)形成基极和源极;13)形成接触孔、金属和钝化层。本发明可解决了两层多晶硅之间介质层厚度难以控制的问题,提高MOS器件性能的稳定性;同时,能避免因为多晶硅尖的两头产生的强电场削弱栅源击穿电压。
The invention discloses a method for forming a thermal oxygen dielectric layer between polysilicon of trench-type double-layer gate MOS, comprising the steps of: 1) growing a first nitride film; 2) trench etching; 3) growing a dielectric layer; 4) Growth of the first layer of polysilicon; 5) The first step of reverse etching of the first layer of polysilicon; 6) Photolithography of the first layer of polysilicon and second step of reverse etching, and removal of the trench sidewall dielectric above the first layer of polysilicon 7) After depositing the second nitride film, etch to expose the first layer of polysilicon; 8) Growing the thermal oxygen dielectric layer; 9) Removing the nitride film; 10) Growth of the gate oxide layer; 11) The second layer Polysilicon deposition and reverse etching; 12) Formation of base and source; 13) Formation of contact holes, metal and passivation layers. The invention can solve the problem that the thickness of the dielectric layer between the two layers of polysilicon is difficult to control, and improve the performance stability of the MOS device; at the same time, it can prevent the gate-source breakdown voltage from being weakened by the strong electric field generated at the two ends of the polysilicon tip.
Description
技术领域 technical field
本发明涉及一种半导体领域中的热氧介质层的形成方法,特别是涉及一种沟槽型双层栅MOS中的多晶硅之间的热氧介质层的形成方法。The invention relates to a method for forming a thermal oxygen dielectric layer in the field of semiconductors, in particular to a method for forming a thermal oxygen dielectric layer between polysilicon in a trench-type double-layer gate MOS.
背景技术 Background technique
在功率器件中,沟槽型双层栅功率MOS器件具有击穿电压高、导通电阻低、转换效率高、开关速度快的特性。通常,第一层多晶硅电极作为屏蔽电极与源极短接或者通单独引出,第二层多晶硅电极作为栅极。两层多晶硅电极之间的氧化层厚度需要严格控制,否则会形成漏电或较低的击穿电压。Among power devices, trench double-layer gate power MOS devices have the characteristics of high breakdown voltage, low on-resistance, high conversion efficiency and fast switching speed. Usually, the polysilicon electrode of the first layer is used as a shielding electrode and is short-circuited with the source or drawn out separately, and the polysilicon electrode of the second layer is used as a gate. The thickness of the oxide layer between the two polysilicon electrodes needs to be strictly controlled, otherwise leakage or lower breakdown voltage will occur.
目前,现有工艺中的两层多晶硅电极之间的氧化层的制备方法,是在第一层多晶硅反刻之后,生长高密度等离子体(HDP)氧化膜,生长的HDP氧化膜要足够厚可以将沟槽(Trench)填满,再进行CMP(化学机械研磨)、光刻、HDP氧化膜反刻,最终在第一层多晶硅上面留下2500埃的HDP作为两层多晶硅之间的介质层。其中,具体的工艺流程如下:At present, the preparation method of the oxide layer between two layers of polysilicon electrodes in the existing process is to grow a high-density plasma (HDP) oxide film after the first layer of polysilicon is etched back, and the grown HDP oxide film must be thick enough to Fill the trench (Trench), and then perform CMP (Chemical Mechanical Polishing), photolithography, HDP oxide film reverse etching, and finally leave 2500 Angstroms of HDP on the first layer of polysilicon as the dielectric layer between the two layers of polysilicon. Among them, the specific process is as follows:
1)在沟槽刻蚀前长一层氧化层作为阻挡层,然后进行沟槽刻蚀;1) Before trench etching, grow an oxide layer as a barrier layer, and then perform trench etching;
2)沟槽内介质层生长;2) Dielectric layer growth in the trench;
3)第一层多晶硅生长;3) The first layer of polysilicon growth;
4)第一层多晶硅第一步反刻蚀;4) The first step of reverse etching of the first layer of polysilicon;
5)第一层多晶硅光刻及第二步反刻蚀;5) The first layer of polysilicon photolithography and the second step of reverse etching;
6)高密度等离子体(HDP)氧化膜淀积;6) High-density plasma (HDP) oxide film deposition;
7)HDP氧化膜CMP(化学机械研磨)至剩余3000埃;7) HDP oxide film CMP (chemical mechanical polishing) to the remaining 3000 Angstroms;
8)湿法腐蚀,使沟槽内的第一层多晶硅上剩余2500埃HDP氧化膜;8) Wet etching, so that 2500 Angstrom HDP oxide film remains on the first layer of polysilicon in the trench;
9)栅极氧化层生长;9) Growth of gate oxide layer;
10)第二层多晶硅淀积与反刻蚀;10) The second layer of polysilicon deposition and reverse etching;
11)形成基极(BODY)和源极(Source);11) Form the base (BODY) and source (Source);
12)形成接触孔、金属和钝化层。12) Form contact holes, metal and passivation layers.
其中,现有工艺中的沟槽刻蚀前生长一层氧化层作为阻挡层的cell(MOSFET的原胞)区断面图,如图1所示;现有工艺中的第一层多晶硅两次刻蚀及去除侧壁氧化层后的cell区断面图,如图2所示;现有工艺中的HDP氧化膜生长后的cell区断面图,如图3所示;现有工艺中的HDP氧化膜湿法刻蚀后的cell区断面图,如图4所示。Among them, the cross-sectional view of the cell (the original cell of MOSFET) in which an oxide layer is grown as a barrier layer before trench etching in the existing process is shown in Figure 1; the first layer of polysilicon in the existing process is etched twice The cross-sectional view of the cell area after etching and removing the sidewall oxide layer is shown in Figure 2; the cross-sectional view of the cell area after the growth of the HDP oxide film in the existing process is shown in Figure 3; the HDP oxide film in the existing process The cross-sectional view of the cell area after wet etching is shown in FIG. 4 .
对于现有工艺,第一层多晶硅第二次刻蚀深度为硅表面以下1.15μm时,HDP氧化硅淀积厚度约1.5μm,HDP氧化硅CMP研磨量约1.2μm,由于HDP氧化膜生长厚度和CMP研磨厚度都很大,所以CMP之后的残余膜厚波动很大。另外,CMP研磨速率在硅片面内不同位置和硅片间存在差异,这也导致了CMP之后的残余膜厚的均一性很差。以上两点导致两层多晶该之间的介质膜厚度的均一性和稳定性都很差。For the existing process, when the second etching depth of the first layer of polysilicon is 1.15 μm below the silicon surface, the HDP silicon oxide deposition thickness is about 1.5 μm, and the HDP silicon oxide CMP grinding amount is about 1.2 μm. Due to the HDP oxide film growth thickness and The thickness of the CMP grinding is very large, so the residual film thickness after CMP fluctuates greatly. In addition, there are differences in the CMP polishing rate between different positions in the silicon wafer and among silicon wafers, which also leads to poor uniformity of the residual film thickness after CMP. The above two points lead to poor uniformity and stability of the thickness of the dielectric film between the two polycrystalline layers.
由于HDP氧化膜在CMP之后残留厚度存在起伏和波动,所以HDP氧化膜反刻之后的残留厚度很难控制,这样会使器件的性能很不稳定。因此,需解决两层多晶硅之间介质层厚度难以控制的问题,以提高沟槽型双层栅功率MOS器件性能的稳定性。Since the residual thickness of the HDP oxide film after CMP fluctuates and fluctuates, it is difficult to control the residual thickness of the HDP oxide film after etching back, which will make the performance of the device very unstable. Therefore, it is necessary to solve the problem that the thickness of the dielectric layer between the two layers of polysilicon is difficult to control, so as to improve the performance stability of the trench type double-layer gate power MOS device.
发明内容 Contents of the invention
本发明要解决的技术问题是提供一种沟槽型双层栅MOS中的多晶硅之间的热氧介质层的形成方法。通过该方法,可解决了两层多晶硅之间介质层厚度难以控制的问题,提高MOS器件性能的稳定性;同时,能避免因为多晶硅尖的两头产生的强电场削弱栅源击穿电压。The technical problem to be solved by the present invention is to provide a method for forming a thermal oxygen dielectric layer between polysilicon in a trench-type double-layer gate MOS. Through this method, the problem of difficulty in controlling the thickness of the dielectric layer between the two layers of polysilicon can be solved, and the stability of the performance of the MOS device can be improved; at the same time, the strong electric field generated at the two ends of the polysilicon tip can prevent the gate-source breakdown voltage from being weakened.
为解决上述技术问题,本发明的沟槽型双层栅MOS中的多晶硅之间的热氧介质层的形成方法,包括步骤:In order to solve the above-mentioned technical problems, the method for forming the thermal oxygen dielectric layer between the polysilicon in the trench type double-layer gate MOS of the present invention comprises steps:
1)在硅基板上,生长第一氮化膜;1) On the silicon substrate, grow the first nitride film;
2)在硅基板上,进行沟槽刻蚀;2) On the silicon substrate, trench etching is performed;
3)在沟槽内,生长介质层;3) In the trench, grow a dielectric layer;
4)在介质层上,生长第一层多晶硅;4) On the dielectric layer, grow the first layer of polysilicon;
5)对第一层多晶硅进行第一步反刻蚀;5) Perform the first step of reverse etching on the first layer of polysilicon;
6)对第一层多晶硅进行光刻及第二步反刻蚀,并去除第一层多晶硅上方的沟槽侧壁介质层;6) Perform photolithography and the second step of reverse etching on the first layer of polysilicon, and remove the trench sidewall dielectric layer above the first layer of polysilicon;
7)在沟槽的底部和侧壁以及硅基板表面淀积第二氮化膜后,刻蚀去除沟槽底部的第二氮化膜,露出第一层多晶硅;7) After depositing the second nitride film on the bottom and side walls of the trench and the surface of the silicon substrate, etch and remove the second nitride film at the bottom of the trench to expose the first layer of polysilicon;
8)在第一层多晶硅上,生长热氧介质层;8) On the first layer of polysilicon, grow a thermal oxygen dielectric layer;
9)去除沟槽侧壁的第二氮化膜和硅基板表面的第一、二氮化膜;9) removing the second nitride film on the side wall of the trench and the first and second nitride films on the surface of the silicon substrate;
10)栅极氧化层生长;10) Growth of gate oxide layer;
11)第二层多晶硅淀积与反刻蚀;11) The second layer of polysilicon deposition and reverse etching;
12)形成基极(BODY)和源极(Source);12) Form the base (BODY) and source (Source);
13)形成接触孔、金属和钝化层。13) Form contact holes, metal and passivation layers.
所述步骤1)中,生长第一氮化膜的方法包括:低压化学气相沉积或等离子体增强式化学气相沉积;第一氮化膜的材质包括:氮化硅;第一氮化膜的厚度为500~3000埃。In the step 1), the method for growing the first nitride film includes: low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition; the material of the first nitride film includes: silicon nitride; the thickness of the first nitride film It is 500-3000 Angstroms.
所述步骤3)中,介质层为氧化膜,厚度为500~3000埃;介质层的生长方式包括:热氧或低压化学气相沉积方式。In the step 3), the dielectric layer is an oxide film with a thickness of 500-3000 angstroms; the growth method of the dielectric layer includes: thermal oxygen or low pressure chemical vapor deposition.
所述步骤4)中,生长第一层多晶硅的方法包括:低压化学气相沉积;第一层多晶硅的厚度为足以填满沟槽内部。In the step 4), the method for growing the first layer of polysilicon includes: low pressure chemical vapor deposition; the thickness of the first layer of polysilicon is sufficient to fill the inside of the trench.
所述步骤5)中,第一步反刻蚀时,直至刻蚀至硅表面。In the step 5), in the first step of reverse etching, until the silicon surface is etched.
所述步骤6)的对第一层多晶硅进行光刻及第二步反刻蚀中,对第一层多晶硅进行光刻,保护住需要接出源极多晶硅的位置,剩余的第一层多晶硅位置进行第二步多晶硅反刻蚀,直至刻蚀至硅表面以下所需深度。In the step 6) of performing photolithography on the first layer of polysilicon and the second step of reverse etching, photoetching is performed on the first layer of polysilicon to protect the position where the source polysilicon needs to be connected, and the remaining position of the first layer of polysilicon The second step of polysilicon back etching is carried out until the desired depth below the silicon surface is etched.
所述步骤7)中,第二氮化膜淀积的方法包括:低压化学气相沉积或等离子体增强式化学气相沉积;第二氮化膜的材质包括:氮化硅;第二氮化膜的厚度为500~3000埃;刻蚀的方法为干法刻蚀。In the step 7), the second nitride film deposition method includes: low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; the material of the second nitride film includes: silicon nitride; the second nitride film The thickness is 500-3000 Angstroms; the etching method is dry etching.
所述步骤8)中,生长热氧介质层的的方法为通过热氧方式生长热氧介质层;其中,热氧方式中的工艺温度为高于950℃;热氧介质层的厚度为500~3000埃。In the step 8), the method of growing the thermal oxygen medium layer is to grow the thermal oxygen medium layer by means of thermal oxygen; wherein, the process temperature in the thermal oxygen mode is higher than 950°C; the thickness of the thermal oxygen medium layer is 500- 3000 Angstroms.
所述步骤9)中,去除的方式包括:湿法刻蚀。In the step 9), the removal method includes: wet etching.
本发明通过在沟槽刻蚀前,生长一层氮化层,并保留到第一层多晶硅电极刻蚀至硅表面以下之后,在沟槽表面生长一层氮化膜,然后利用干法刻蚀各向异性原理,形成氮化硅侧壁,并与之前保留在硅基板表面的氮化硅层连在一起,形成侧壁及顶部的保护层。利用热氧化在多晶硅沟槽底部的多晶硅表面生成热氧化层,再去除侧壁及顶部氮化硅,形成沟槽型双层栅MOS结构两层多晶硅之间热氧介质层。由于本发明利用氮化膜作为长两层多晶硅间热氧隔离介质层的保护层,使得在同样隔离性能的情况下,较现有的形成氧化硅介质层工艺大大简化,省略多次HDP以及CMP等高成本工艺流程,且不存在HDP氧化膜难以控制的风险,大大简化工艺控制难度,即本发明解决了两层多晶硅之间介质层厚度难以控制的问题,提高器件性能的稳定性。更为重要的是,该方法因为使用热氧化工艺作为介质层,使得下方的源极多晶硅(第一层多晶硅)的形貌从两端尖的凹形变为了两端圆的凸形,从而避免因为多晶硅尖的两头产生的强电场削弱栅源击穿电压。The present invention grows a layer of nitride layer before etching the trench, and retains it until the first layer of polysilicon electrode is etched below the silicon surface, grows a layer of nitride film on the surface of the groove, and then uses dry etching The principle of anisotropy forms the sidewall of silicon nitride and connects it with the silicon nitride layer previously retained on the surface of the silicon substrate to form a protective layer on the sidewall and top. Thermal oxidation is used to generate a thermal oxide layer on the polysilicon surface at the bottom of the polysilicon trench, and then the sidewall and top silicon nitride are removed to form a thermal oxygen dielectric layer between two layers of polysilicon in a trench-type double-layer gate MOS structure. Since the present invention utilizes the nitride film as the protective layer of the long two-layer inter-polysilicon heat-oxygen isolation dielectric layer, the process of forming the silicon oxide dielectric layer is greatly simplified compared with the existing process of forming the silicon oxide dielectric layer under the same isolation performance, and multiple HDP and CMP are omitted. High-cost process flow, and there is no risk of difficult control of HDP oxide film, which greatly simplifies the difficulty of process control, that is, the present invention solves the problem of difficult control of the thickness of the dielectric layer between two layers of polysilicon, and improves the stability of device performance. More importantly, because this method uses a thermal oxidation process as the dielectric layer, the shape of the underlying source polysilicon (the first layer of polysilicon) changes from a concave shape with sharp ends to a convex shape with round ends, thereby avoiding the The strong electric field generated at both ends of the polysilicon tip weakens the gate-source breakdown voltage.
附图说明 Description of drawings
下面结合附图与具体实施方式对本发明作进一步详细的说明:Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:
图1是现有工艺中的沟槽刻蚀前生长一层氧化层作为阻挡层的cell区断面图;FIG. 1 is a cross-sectional view of a cell region in which an oxide layer is grown as a barrier layer before trench etching in the prior art;
图2是现有工艺中的第一层多晶硅两步反刻蚀及去除侧壁氧化层后的cell区断面图;Figure 2 is a cross-sectional view of the cell area after two-step reverse etching of the first layer of polysilicon and removal of the sidewall oxide layer in the prior art;
图3是现有工艺中的HDP氧化膜生长后的cell区断面图;Fig. 3 is a cross-sectional view of the cell area after the growth of the HDP oxide film in the prior art;
图4是现有工艺中的HDP氧化膜湿法刻蚀后的cell区断面图;Fig. 4 is a cross-sectional view of the cell area after wet etching of the HDP oxide film in the prior art;
图5是本发明的沟槽刻蚀前生长一层氮化层作为阻挡层的cell区断面图;Fig. 5 is a cross-sectional view of a cell region in which a layer of nitride layer is grown as a barrier layer before trench etching of the present invention;
图6是本发明的第一层多晶硅两步反刻蚀及去除侧壁氧化层后的cell区断面图;Fig. 6 is a cross-sectional view of the cell area after two-step reverse etching of the first layer of polysilicon and removal of the sidewall oxide layer of the present invention;
图7是本发明的生长一层氮化膜后的cell区断面图;Fig. 7 is a sectional view of the cell area after growing a nitride film of the present invention;
图8是本发明的刻蚀形成侧壁氮化膜保护层的cell区断面图;Fig. 8 is a cross-sectional view of the cell area where the sidewall nitride film protection layer is formed by etching in the present invention;
图9是本发明的在第一层多晶硅上生长热氧介质层后的cell区断面图;Fig. 9 is a cross-sectional view of the cell region after growing a thermal oxygen dielectric layer on the first layer of polysilicon in the present invention;
图10是本发明的去除沟槽侧壁及硅基板表面的氮化膜后的cell区断面图。10 is a cross-sectional view of the cell region after removing the trench sidewall and the nitride film on the surface of the silicon substrate according to the present invention.
图中附图标记说明如下:The reference signs in the figure are explained as follows:
1为硅基板,2为氧化层,3为第一氮化膜,4为介质层,5为第一层多晶硅,6为第二氮化膜,7为热氧介质层。1 is the silicon substrate, 2 is the oxide layer, 3 is the first nitride film, 4 is the dielectric layer, 5 is the first polysilicon layer, 6 is the second nitride film, and 7 is the thermal oxygen dielectric layer.
具体实施方式 detailed description
本发明的沟槽型双层栅MOS中的多晶硅之间的热氧介质层的形成方法,其步骤如下:The method for forming the thermal oxygen dielectric layer between the polysilicon in the trench type double-layer gate MOS of the present invention, its steps are as follows:
1)在硅基板1上,通过低压化学气相沉积或等离子体增强式化学气相沉积方法,生长第一氮化膜3,即氮化硅层,第一氮化膜3的厚度为500~3000埃(如图5所示);1) On the silicon substrate 1, grow the first nitride film 3, that is, the silicon nitride layer, by low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, and the thickness of the first nitride film 3 is 500-3000 angstroms (as shown in Figure 5);
本步骤中的第一氮化膜3可作为后续工艺中沟槽顶部的保护层;The first nitride film 3 in this step can be used as a protective layer on the top of the trench in subsequent processes;
2)在硅基板1上,进行沟槽刻蚀;2) performing trench etching on the silicon substrate 1;
3)在沟槽的侧壁和底部,通过热氧或低压化学气相沉积方式,生长介质层4(即氧化硅),厚度为500~3000埃;3) On the sidewall and bottom of the trench, grow a dielectric layer 4 (i.e., silicon oxide) with a thickness of 500-3000 angstroms by means of thermal oxygen or low-pressure chemical vapor deposition;
4)在介质层4上,通过低压化学气相沉积,生长第一层多晶硅5,第一层多晶硅5的厚度为足以填满沟槽内部;4) On the dielectric layer 4, a first layer of polysilicon 5 is grown by low-pressure chemical vapor deposition, and the thickness of the first layer of polysilicon 5 is sufficient to fill the inside of the trench;
5)对第一层多晶硅5进行第一步反刻蚀,直至刻蚀至硅表面;5) Perform the first step of reverse etching on the first layer of polysilicon 5 until it is etched to the silicon surface;
6)对第一层多晶硅5进行光刻及第二步反刻蚀,并通过湿法刻蚀,去除第一层多晶硅5上方的沟槽侧壁介质层4(如图6所示);6) Perform photolithography and second step reverse etching on the first layer of polysilicon 5, and remove the trench sidewall dielectric layer 4 above the first layer of polysilicon 5 by wet etching (as shown in Figure 6);
其中,对第一层多晶硅5进行光刻,保护住需要接出源极多晶硅的位置,剩余的第一层多晶硅位置进行第二步多晶硅反刻蚀,直至刻蚀至硅表面以下所需深度(特定深度);Wherein, the first layer of polysilicon 5 is photolithographically protected to protect the position where the source polysilicon needs to be connected, and the remaining first layer of polysilicon is subjected to the second step of polysilicon reverse etching until it is etched to the desired depth below the silicon surface ( specific depth);
图6中的第一氮化膜3作为后续热氧介质层7的表面保护层;The first nitride film 3 in FIG. 6 serves as a surface protection layer for the subsequent thermal oxygen dielectric layer 7;
7)通过低压化学气相沉积或等离子体增强式化学气相沉积,在沟槽的底部和侧壁以及硅基板1表面(第一氮化膜3表面)淀积第二氮化膜(即氮化硅)6后(如图7所示),干法刻蚀去除沟槽底部的第二氮化膜6,露出第一层多晶硅5(如图8所示);其中,第二氮化膜6的厚度为500~3000埃;7) By low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition, deposit a second nitride film (that is, silicon nitride film) on the bottom and side walls of the trench and the surface of the silicon substrate 1 (the surface of the first nitride film 3 ). ) 6 (as shown in FIG. 7 ), dry etching removes the second nitride film 6 at the bottom of the trench, exposing the first layer of polysilicon 5 (as shown in FIG. 8 ); wherein, the second nitride film 6 The thickness is 500-3000 Angstroms;
8)在第一层多晶硅5上,通过热氧方式(温度高于950℃),生长热氧介质层7(如图9所示),即氧化硅层,其厚度为500~3000埃;8) On the first layer of polysilicon 5, grow a thermal oxygen dielectric layer 7 (as shown in FIG. 9 ), that is, a silicon oxide layer, with a thickness of 500-3000 angstroms by means of thermal oxygen (temperature higher than 950°C);
9)湿法刻蚀,去除沟槽侧壁的第二氮化膜6,以及硅基板1表面的第一氮化膜3、和第二氮化膜6(如图10所示),留下沟槽底部的第一层多晶硅5上存在的热氧介质层7,从而形成沟槽型双层栅MOS结构中的两层多晶硅之间的热氧介质层;9) Wet etching, removing the second nitride film 6 on the side wall of the trench, and the first nitride film 3 and the second nitride film 6 on the surface of the silicon substrate 1 (as shown in FIG. 10 ), leaving A thermal oxygen dielectric layer 7 exists on the first layer of polysilicon 5 at the bottom of the trench, thereby forming a thermal oxygen dielectric layer between two layers of polysilicon in the trench type double-layer gate MOS structure;
10)按照现有工艺,利用热氧化,生长栅极氧化层;10) According to the existing process, use thermal oxidation to grow the gate oxide layer;
11)按照现有工艺,进行第二层多晶硅淀积与反刻蚀,即利用低压化学气相沉积生长第二层多晶硅,刻蚀至硅表面;11) According to the existing process, the second layer of polysilicon deposition and reverse etching is carried out, that is, the second layer of polysilicon is grown by low-pressure chemical vapor deposition, and etched to the silicon surface;
12)按照现有工艺,通过离子注入,形成基极(BODY)和源极(Source);12) According to the existing process, form the base (BODY) and source (Source) by ion implantation;
13)按照现有工艺,形成接触孔、金属和钝化层,即利用掩膜板刻蚀形成接触孔,淀积金属层并刻蚀形成接触电极,淀积并刻蚀形成钝化层。13) According to the existing process, form the contact hole, metal and passivation layer, that is, use the mask plate to etch to form the contact hole, deposit the metal layer and etch to form the contact electrode, deposit and etch to form the passivation layer.
按照上述步骤,通过在第一层多晶硅5光刻及第二步反刻蚀后,需要再生长一层第二氮化膜6并利用干法刻蚀各向异性特征,使得沟槽底部氮化硅刻蚀干净,露出下面的第一层多晶硅5的同时,侧壁氮化硅保护层保留下来(即第二氮化膜6侧壁保护层),并与硅基板1表面的氮化硅一起形成保护层,即沟槽侧壁与之前生长在硅基板1表面的第一氮化膜3连在一起形成保护层,使得后续的热氧介质层7仅在第一层多晶硅5上生长;然后,通过去除沟槽侧壁及硅基板1表面的氮化膜,热氧隔离层(即热氧介质层)就此形成,即通过氮化硅作为屏蔽层来形成沟槽型双层栅MOS结构中的两层多晶硅之间热氧介质层。因此,本发明能解决了两层多晶硅之间介质层厚度难以控制的问题,而且最终制备得到的沟槽型双层栅MOS具有较高的性能稳定性;同时,本发明也能避免因为多晶硅尖的两头产生的强电场削弱栅源击穿电压。According to the above steps, after the photolithography of the first layer of polysilicon 5 and the second step of reverse etching, it is necessary to grow a second layer of nitride film 6 and use dry etching to anisotropic features, so that the bottom of the trench is nitrided. The silicon is etched clean to expose the underlying first layer of polysilicon 5, while the sidewall silicon nitride protection layer remains (that is, the sidewall protection layer of the second nitride film 6) and is formed together with the silicon nitride on the surface of the silicon substrate 1. Forming a protective layer, that is, the sidewall of the trench is connected with the first nitride film 3 previously grown on the surface of the silicon substrate 1 to form a protective layer, so that the subsequent thermal oxygen dielectric layer 7 is only grown on the first layer of polysilicon 5; then , by removing the trench sidewalls and the nitride film on the surface of the silicon substrate 1, the thermal oxygen isolation layer (that is, the thermal oxygen dielectric layer) is formed, that is, the trench type double-layer gate MOS structure is formed by using silicon nitride as a shielding layer The thermal oxygen dielectric layer between the two layers of polysilicon. Therefore, the present invention can solve the problem that the thickness of the dielectric layer between two layers of polysilicon is difficult to control, and the trench type double-layer gate MOS that is finally prepared has high performance stability; at the same time, the present invention can also avoid The strong electric field generated at both ends weakens the gate-source breakdown voltage.
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