CN103632949A - Thermal oxidation dielectric layer forming method in groove type double-layer grid MOS polysilicon - Google Patents
Thermal oxidation dielectric layer forming method in groove type double-layer grid MOS polysilicon Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 95
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 91
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000003647 oxidation Effects 0.000 title claims abstract description 10
- 238000007254 oxidation reaction Methods 0.000 title claims abstract description 10
- 150000004767 nitrides Chemical class 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 35
- 239000001301 oxygen Substances 0.000 claims description 35
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 29
- 229910052710 silicon Inorganic materials 0.000 claims description 29
- 239000010703 silicon Substances 0.000 claims description 29
- 230000003628 erosive effect Effects 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 18
- 230000012010 growth Effects 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- 230000026267 regulation of growth Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000006263 metalation reaction Methods 0.000 claims description 4
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims description 3
- 102000013275 Somatomedins Human genes 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 230000007773 growth pattern Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000005684 electric field Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 88
- 239000011241 protective layer Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000006396 nitration reaction Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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Abstract
The invention discloses a thermal oxidation dielectric layer forming method in groove type double-layer grid MOS polysilicon; the method comprises the steps of: 1, growing a first nitride film; 2, etching a groove; 3, growing a dielectric layer; 4, growing a first polysilicon layer; 5, first step inverse etching the first polysilicon layer; 6, photoetching and second step inverse etching the first polysilicon layer, and removing a groove side wall dielectric layer above the first polysilicon layer; 7, depositing a second nitride film, etching the second nitride film to expose the first polysilicon layer; 8, growing a thermal oxidation dielectric layer; 9, removing the nitride film; 10, growing a gird oxide layer; 11, depositing and inverse etching a second polysilicon layer; 12, forming a base electrode and a source electrode; 13, forming a contact hole, metal and a passivation layer. The method can solve the problem that the dielectric layer thickness between two polysilicon layers is different to control, thereby improving the stability of MOS device performance; simultaneously, the condition in which the strong electric field generated on two sides of the polysilicon tips can weaken the grid source and breakdown the voltage is prevented.
Description
Technical field
The present invention relates to the formation method of the hot oxygen medium layer in a kind of semiconductor applications, particularly relate to the formation method of the hot oxygen medium layer between the polysilicon in a kind of groove type double-layer grid MOS.
Background technology
In power device, groove type double-layer grid power MOS device has the characteristic that puncture voltage is high, conducting resistance is low, conversion efficiency is high, switching speed is fast.Conventionally, ground floor polysilicon electrode is as bucking electrode and source shorted or logically draw separately, and second layer polysilicon electrode is as grid.Oxidated layer thickness between two-layer polysilicon electrode needs strict control, otherwise can form electric leakage or lower puncture voltage.
At present, the preparation method of the oxide layer between the two-layer polysilicon electrode in existing technique, after ground floor polysilicon anti-carves, growing high density plasma (HDP) oxide-film, the HDP oxide-film of growth is wanted enough thick groove (Trench) can being filled up, carry out again CMP(cmp), photoetching, HDP oxide-film anti-carve, the HDP that finally leaves 2500 dusts on ground floor polysilicon is as the dielectric layer between two-layer polysilicon.Wherein, concrete technological process is as follows:
1) before etching groove, long layer of oxide layer, as barrier layer, is then carried out etching groove;
2) groove inner medium layer growth;
3) ground floor polycrystalline silicon growth;
4) the ground floor polysilicon first step anti-carves erosion;
5) photoetching of ground floor polysilicon and second step anti-carve erosion;
6) high-density plasma (HDP) oxide-film deposit;
7) HDP oxidation film CMP (cmp) is to remaining 3000 dusts;
8) wet etching, makes to remain on the ground floor polysilicon in groove 2500 dust HDP oxide-films;
9) gate oxidation layer growth;
10) deposit of second layer polysilicon with anti-carve erosion;
11) form base stage (BODY) and source electrode (Source);
12) form contact hole, metal and passivation layer.
Wherein, before the etching groove in existing technique, growth layer of oxide layer is as the primitive unit cell of the cell(MOSFET on barrier layer) district's sectional drawing, as shown in Figure 1; Cell district sectional drawing after ground floor polysilicon twice etching in existing technique and removal sidewall oxide, as shown in Figure 2; Cell district sectional drawing after HDP oxide growth in existing technique, as shown in Figure 3; Cell district sectional drawing after HDP oxide film wet etching in existing technique, as shown in Figure 4.
For existing technique, ground floor polysilicon is when etching depth is the following 1.15 μ m of silicon face for the second time, HDP silicon oxide deposition thickness approximately 1.5 μ m, HDP silica CMP amount of grinding approximately 1.2 μ m, due to HDP oxide growth thickness and CMP grinding thickness all very large, so the remaining thickness fluctuation after CMP is very large.In addition, CMP grinding rate there are differences between diverse location and silicon chip in silicon chip face, and this has also caused the homogeneity of the remaining thickness after CMP very poor.Above 2 cause two-layer polycrystalline should between homogeneity and the stability of deielectric-coating thickness all very poor.
Because HDP oxide-film residual thickness after CMP exists, rise and fall and fluctuation, so HDP oxide-film anti-carves residual thickness afterwards, be difficult to control, can make like this performance of device very unstable.Therefore, need to solve the unmanageable problem of thickness of dielectric layers between two-layer polysilicon, to improve the stability of groove type double-layer grid power MOS device performance.
Summary of the invention
The technical problem to be solved in the present invention is to provide the formation method of the hot oxygen medium layer between the polysilicon in a kind of groove type double-layer grid MOS.By the method, can solve the unmanageable problem of thickness of dielectric layers between two-layer polysilicon, improve the stability of MOS device performance; Meanwhile, can avoid because the highfield that two of polycrystalline silicon tip produces weakens grid source puncture voltage.
For solving the problems of the technologies described above, the formation method of the hot oxygen medium layer between the polysilicon in groove type double-layer grid MOS of the present invention, comprises step:
1) on silicon substrate, first nitride film of growing;
2), on silicon substrate, carry out etching groove;
3) in groove, somatomedin layer;
4) on dielectric layer, growth regulation one deck polysilicon;
5) ground floor polysilicon is carried out to the first step and anti-carve erosion;
6) ground floor polysilicon is carried out to photoetching and second step anti-carves erosion, and remove the trenched side-wall dielectric layer of ground floor polysilicon top;
7), behind the bottom and sidewall and silicon substrate surface deposition the second nitride film of groove, the second nitride film that etching is removed channel bottom, exposes ground floor polysilicon;
8) on ground floor polysilicon, the hot oxygen medium layer of growing;
9) remove the second nitride film of trenched side-wall and first and second nitride film on silicon substrate surface;
10) gate oxidation layer growth;
11) deposit of second layer polysilicon with anti-carve erosion;
12) form base stage (BODY) and source electrode (Source);
13) form contact hole, metal and passivation layer.
In described step 1), the method for first nitride film of growing comprises: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; The material of the first nitride film comprises: silicon nitride; The thickness of the first nitride film is 500～3000 dusts.
In described step 3), dielectric layer is oxide-film, and thickness is 500～3000 dusts; The growth pattern of dielectric layer comprises: hot oxygen or low-pressure chemical vapor deposition mode.
In described step 4), the method for growth regulation one deck polysilicon comprises: low-pressure chemical vapor deposition; The thickness of ground floor polysilicon is for being enough to fill up groove inside.
In described step 5), when the first step anti-carves erosion, until be etched to silicon face.
Described step 6) ground floor polysilicon is carried out to photoetching and second step anti-carves in erosion; ground floor polysilicon is carried out to photoetching; protect the position that need to pick out source electrode polysilicon; remaining ground floor polysilicon position is carried out second step polysilicon and is anti-carved erosion, until be etched to the following desired depth of silicon face.
In described step 7), the method for the second nitride film deposit comprises: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; The material of the second nitride film comprises: silicon nitride; The thickness of the second nitride film is 500～3000 dusts; The method of etching is dry etching.
In described step 8), the hot oxygen medium layer of growing method for by the hot oxygen mode hot oxygen medium layer of growing; Wherein, the technological temperature in hot oxygen mode is higher than 950 ℃; The thickness of hot oxygen medium layer is 500～3000 dusts.
In described step 9), the mode of removal comprises: wet etching.
The present invention is by before etching groove; growth one deck nitration case; and remain into ground floor polysilicon electrode be etched to silicon face following after; at flute surfaces growth one deck nitride film; then utilize dry etching anisotropy principle; form silicon nitride sidewall, and connect together with the silicon nitride layer that is retained in before silicon substrate surface, form the protective layer at sidewall and top.Utilize thermal oxidation in the polysilicon surface Heat of Formation oxide layer of polysilicon trench bottom, then remove sidewall and top silicon nitride, form hot oxygen medium layer between groove type double-layer grid MOS structure two-layer polysilicon.Because the present invention utilizes nitride film as the protective layer of hot oxygen spacer medium layer between long two-layer polysilicon; make the in the situation that of same isolation performance; more existing formation silica medium layer process is simplified greatly; omit repeatedly the expensive technological process such as HDP and CMP; and there is not the unmanageable risk of HDP oxide-film; greatly simplify technique controlling difficulty, the invention solves the unmanageable problem of thickness of dielectric layers between two-layer polysilicon, improve the stability of device performance.What is more important, the method is because used thermal oxidation technology as dielectric layer, make the pattern of the source electrode polysilicon (ground floor polysilicon) of below from fusiform spill, become the convex of two terminal circle, thereby avoid because the highfield that two of polycrystalline silicon tip produces weakens grid source puncture voltage.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is the cell district sectional drawing of layer of oxide layer as barrier layer of growing before the etching groove in existing technique;
Fig. 2 is that ground floor polysilicon two steps in existing technique anti-carve erosion and remove the cell district sectional drawing after sidewall oxide;
Fig. 3 is the cell district sectional drawing after the HDP oxide growth in existing technique;
Fig. 4 is the cell district sectional drawing after the HDP oxide film wet etching in existing technique;
Fig. 5 is the cell district sectional drawing of one deck nitration case as barrier layer of growing before etching groove of the present invention;
Fig. 6 is that ground floor polysilicon two steps of the present invention anti-carve erosion and remove the cell district sectional drawing after sidewall oxide;
Fig. 7 is the cell district sectional drawing after growth one deck nitride film of the present invention;
Fig. 8 is the cell district sectional drawing that etching of the present invention forms sidewall nitride film protective layer;
Fig. 9 is cell district sectional drawing of growing on ground floor polysilicon after hot oxygen medium floor of the present invention;
Figure 10 is the cell district sectional drawing after the nitride film on removal trenched side-wall of the present invention and silicon substrate surface.
In figure, description of reference numerals is as follows:
1 is silicon substrate, and 2 is oxide layer, and 3 is the first nitride film, and 4 is dielectric layer, and 5 is ground floor polysilicon, and 6 is the second nitride film, and 7 is hot oxygen medium layer.
Embodiment
The formation method of the hot oxygen medium layer between the polysilicon in groove type double-layer grid MOS of the present invention, its step is as follows:
1) on silicon substrate 1, by low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition method, first nitride film 3 of growing, i.e. silicon nitride layer, the thickness of the first nitride film 3 is 500～3000 dusts (as shown in Figure 5);
The first nitride film 3 in this step can be used as the protective layer at groove top in subsequent technique;
2), on silicon substrate 1, carry out etching groove;
3), in sidewall and the bottom of groove, by hot oxygen or low-pressure chemical vapor deposition mode, somatomedin layer 4(is silica), thickness is 500～3000 dusts;
4) on dielectric layer 4, by low-pressure chemical vapor deposition, growth regulation one deck polysilicon 5, the thickness of ground floor polysilicon 5 is for being enough to fill up groove inside;
5) ground floor polysilicon 5 is carried out to the first step and anti-carve erosion, until be etched to silicon face;
6) ground floor polysilicon 5 is carried out to photoetching and second step anti-carves erosion, and by wet etching, remove the trenched side-wall dielectric layer 4(of ground floor polysilicon 5 tops as shown in Figure 6);
Wherein, ground floor polysilicon 5 is carried out to photoetching, protect the position that need to pick out source electrode polysilicon, remaining ground floor polysilicon position is carried out second step polysilicon and is anti-carved erosion, until be etched to the following desired depth of silicon face (certain depth);
The first nitride film 3 in Fig. 6 is as the sealer of subsequent thermal oxygen medium layer 7;
7) by low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, bottom and sidewall and silicon substrate 1 surface (the first nitride film 3 surfaces) deposit the second nitride film (being silicon nitride) 6 rear (as shown in Figure 7) at groove, dry etching is removed the second nitride film 6 of channel bottom, exposes ground floor polysilicon 5(as shown in Figure 8); Wherein, the thickness of the second nitride film 6 is 500～3000 dusts;
8), on ground floor polysilicon 5, by hot oxygen mode (temperature is higher than 950 ℃), grow hot oxygen medium layer 7(as shown in Figure 9), i.e. silicon oxide layer, its thickness is 500～3000 dusts;
9) wet etching, remove the second nitride film 6 of trenched side-wall, and first nitride film 3 on silicon substrate 1 surface and the second nitride film 6(are as shown in figure 10), leave the hot oxygen medium layer 7 existing on the ground floor polysilicon 5 of channel bottom, thereby form the hot oxygen medium layer between the two-layer polysilicon in groove type double-layer grid MOS structure;
10) according to existing technique, utilize thermal oxidation, growth grid oxic horizon;
11) according to existing technique, carry out the deposit of second layer polysilicon and anti-carve erosion, utilize low-pressure chemical vapor deposition growth second layer polysilicon, be etched to silicon face;
12), according to existing technique, by Implantation, form base stage (BODY) and source electrode (Source);
13) according to existing technique, form contact hole, metal and passivation layer, utilize mask plate etching to form contact hole, deposited metal etching form contact electrode, and deposit etching form passivation layer.
According to above-mentioned steps, by anti-carving after erosion in 5 photoetching of ground floor polysilicon and second step, need regrowth one deck the second nitride film 6 and utilize dry etching anisotropic character, make channel bottom silicon nitride etch clean, when exposing ground floor polysilicon below 5, sidewall silicon nitride protective layer remains (i.e. the second nitride film 6 side wall protective layers), and form protective layer with together with the silicon nitride on silicon substrate 1 surface, it is trenched side-wall and the first nitride film 3 that is grown in the before silicon substrate 1 surface formation protective layer that connects together, make the only growth on ground floor polysilicon 5 of follow-up hot oxygen medium layer 7, then, by removing the nitride film on trenched side-wall and silicon substrate 1 surface, hot oxygen separator (instant heating oxygen medium layer) forms at this point, by silicon nitride, as screen, forms hot oxygen medium layer between the two-layer polysilicon in groove type double-layer grid MOS structure.Therefore, the present invention can solve the unmanageable problem of thickness of dielectric layers between two-layer polysilicon, and the groove type double-layer grid MOS finally preparing has higher stability; Meanwhile, the present invention also can avoid because the highfield that two of polycrystalline silicon tip produces weakens grid source puncture voltage.
Claims (9)
1. a formation method for the hot oxygen medium layer between the polysilicon in groove type double-layer grid MOS, is characterized in that, comprises step:
1) on silicon substrate, first nitride film of growing;
2), on silicon substrate, carry out etching groove;
3) in groove, somatomedin layer;
4) on dielectric layer, growth regulation one deck polysilicon;
5) ground floor polysilicon is carried out to the first step and anti-carve erosion;
6) ground floor polysilicon is carried out to photoetching and second step anti-carves erosion, and remove the trenched side-wall dielectric layer of ground floor polysilicon top;
7), behind the bottom and sidewall and silicon substrate surface deposition the second nitride film of groove, the second nitride film that etching is removed channel bottom, exposes ground floor polysilicon;
8) on ground floor polysilicon, the hot oxygen medium layer of growing;
9) remove the second nitride film of trenched side-wall and first and second nitride film on silicon substrate surface;
10) gate oxidation layer growth;
11) deposit of second layer polysilicon with anti-carve erosion;
12) form base stage and source electrode;
13) form contact hole, metal and passivation layer.
2. the method for claim 1, is characterized in that: in described step 1), the method for first nitride film of growing comprises: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition; The material of the first nitride film comprises: silicon nitride; The thickness of the first nitride film is 500～3000 dusts.
3. the method for claim 1, is characterized in that: in described step 3), dielectric layer is oxide-film, and thickness is 500～3000 dusts; The growth pattern of dielectric layer comprises: hot oxygen or low-pressure chemical vapor deposition mode.
4. the method for claim 1, is characterized in that: in described step 4), the method for growth regulation one deck polysilicon comprises: low-pressure chemical vapor deposition; The thickness of ground floor polysilicon is for being enough to fill up groove inside.
5. the method for claim 1, is characterized in that: in described step 5), when the first step anti-carves erosion, until be etched to silicon face.
6. the method for claim 1; it is characterized in that: described step 6) ground floor polysilicon is carried out to photoetching and second step anti-carves in erosion; ground floor polysilicon is carried out to photoetching; protect the position that need to pick out source electrode polysilicon; remaining ground floor polysilicon position is carried out second step polysilicon and is anti-carved erosion, until be etched to the following desired depth of silicon face.
7. the method for claim 1, is characterized in that: in described step 7), the method for the second nitride film deposit comprises: low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition;
The material of the second nitride film comprises: silicon nitride; The thickness of the second nitride film is 500～3000 dusts;
The method of etching is dry etching.
8. the method for claim 1, is characterized in that: in described step 8), the hot oxygen medium layer of growing method be the hot oxygen medium layer of growing by hot oxygen mode; Wherein, the technological temperature in hot oxygen mode is higher than 950 ℃;
The thickness of hot oxygen medium layer is 500～3000 dusts.
9. the method for claim 1, is characterized in that: in described step 9), the mode of removal comprises: wet etching.
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| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
| CN106024607A (en) * | 2016-05-18 | 2016-10-12 | 上海华虹宏力半导体制造有限公司 | Shielding gate power MOSFET manufacturing method |
| CN106920752A (en) * | 2017-03-15 | 2017-07-04 | 西安龙腾新能源科技发展有限公司 | Low pressure super node MOSFET grid source aoxidizes Rotating fields and manufacture method |
| CN107482003A (en) * | 2016-06-08 | 2017-12-15 | 中芯国际集成电路制造(上海)有限公司 | Domain structure, transistor and its manufacture method of transistor |
| CN112838009A (en) * | 2021-01-11 | 2021-05-25 | 广州粤芯半导体技术有限公司 | Manufacturing method of shielded gate trench power device |
| CN113193046A (en) * | 2021-03-24 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
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| CN105448741A (en) * | 2015-12-31 | 2016-03-30 | 上海华虹宏力半导体制造有限公司 | Shield grid groove type MOSFET process method |
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| CN113972269A (en) * | 2020-07-24 | 2022-01-25 | 和舰芯片制造(苏州)股份有限公司 | Preparation method of SGT power MOSFET |
| CN112838009A (en) * | 2021-01-11 | 2021-05-25 | 广州粤芯半导体技术有限公司 | Manufacturing method of shielded gate trench power device |
| CN113193046A (en) * | 2021-03-24 | 2021-07-30 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113193046B (en) * | 2021-03-24 | 2024-04-26 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN113707550A (en) * | 2021-09-01 | 2021-11-26 | 浙江同芯祺科技有限公司 | IGBT trench gate oxide film forming process |
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