CN102593038A - Shallow trench isolation manufacturing method - Google Patents
Shallow trench isolation manufacturing method Download PDFInfo
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- CN102593038A CN102593038A CN2011100094823A CN201110009482A CN102593038A CN 102593038 A CN102593038 A CN 102593038A CN 2011100094823 A CN2011100094823 A CN 2011100094823A CN 201110009482 A CN201110009482 A CN 201110009482A CN 102593038 A CN102593038 A CN 102593038A
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Abstract
The invention discloses a shallow trench isolation manufacturing method. The technical procedures for forming the shallow trench isolation and an active region on a silicon substrate comprise that non-crystallizing ions are injected in the position at the edge of the active region so as to allow the crystalline silicon on the surface of the active region at the injection position to be subjected to non-crystallizing processing. According to the method provided by the invention, during the following growth process of a gate oxide layer, the growth speed at the border edge is faster than that in the active region, the thinning effect of the edge thickness of the gate oxide layer is reduced, gate breakdown voltage and gate breakdown service life of a device is improved, and accordingly, the reliability of the device is improved.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to the manufacturing approach that a kind of shallow trench isolation leaves.
Background technology
Existing shallow trench isolation is included in the etching technics that forms shallow trench on the silicon substrate, inserts the technology of said shallow trench and adopt cmp that the outside unnecessary said shallow trench isolating oxide layer of said shallow trench is polished the technology of removal with the shallow trench isolating oxide layer from (STI) process, polishes the electric isolation of the said shallow trench isolating oxide layer of back in being formed at said shallow trench as active area.
In existing shallow ditch groove separation process; Like 0.18 μ m and following technology node; In the time of the growth grid oxic horizon; The thickness of said grid oxic horizon is often thin than active area inside at the edge, boundary that active area and said shallow trench isolation leave, so-called oxide layer edge thickness attenuation (Thinning) effect that Here it is.This effect not only can cause so-called at I
DsAnd V
GsCurve forms dual waves (Double hump); Reduce the cut-in voltage of device; Increase electric leakage; What is more important maybe be owing to edge's grid oxic horizon attenuation, and the maximum voltage that makes grid oxic horizon to bear descends, and causes the gate breakdown voltage (GOI) and the reliability failures in gate breakdown life-span (TDDB) of grid oxic horizon.
Summary of the invention
Technical problem to be solved by this invention provides the manufacturing approach that a kind of shallow trench isolation leaves, and can eliminate follow-up grid oxic horizon edge thickness attenuation effect, improves device grids puncture voltage and gate breakdown life-span.
For solving the problems of the technologies described above; The manufacturing approach that shallow trench isolation provided by the invention leaves on silicon substrate, form shallow trench isolation from the processing step of active area in be included in said active area the marginal position place carry out the step that decrystallized ion injects; The marginal position place of said active area is that said active area and said shallow trench isolation leave the marginal position place that has a common boundary, and the monocrystalline silicon that said decrystallized ion injects the said surfaces of active regions that makes injection place is decrystallized.
Further improve is that said decrystallized ion is injected to the silicon ion injection or argon ion injects.
Further improve is on said silicon substrate, to form said shallow trench isolation and comprise from the processing step with said active area:
Step 1, on said silicon substrate, form hard mask layer, said hard mask layer is carried out photoetching and etching, define said shallow plough groove isolation area; Said hard mask layer comprises sacrificial oxide layer and the silicon nitride layer that is formed at said surface of silicon successively.
Step 2, be that mask carries out etching to said silicon substrate, form shallow trench with said hard mask layer.
Step 3, carry out thermal oxidation technology, form first cushion oxide layer on the surface of said shallow trench.
Step 4, carry out chemical vapor deposition method, on said silicon substrate, form the shallow trench isolating oxide layer, the said said shallow trench of shallow trench isolating oxide layer complete filling also covers said silicon nitride layer surface.
Step 5, carry out chemical mechanical milling tech, the shallow trench isolating oxide layer on the said silicon nitride layer has been ground.
Step 6, employing wet-etching technology carry out etching to said shallow trench isolating oxide layer, make said shallow trench isolating oxide layer etch into the position that is higher than said surfaces of active regions certain distance.
Step 7, said silicon nitride layer is carried out wet method return quarter, said active area and said shallow trench isolation are exposed from the said sacrificial oxide layer at the marginal position place that has a common boundary.The thickness that said silicon nitride layer returns quarter is 200 dusts～600 dusts.
Step 8, carrying out decrystallized ion, to inject the monocrystalline silicon at the marginal position place that makes said active area decrystallized.
Step 9, employing wet-etching technology are removed said silicon nitride layer and said sacrificial oxide layer.
Step 10, employing thermal oxidation technology form grid oxic horizon on the surface of said active area; In thermal oxidation process, the oxidation rate of the amorphous silicon at the marginal position place of said active area is accelerated, and the edge thickness of said grid oxic horizon is increased.
The present invention is utilized in the forming process of shallow ditch groove separation process; Silicon is introduced at edge, boundary through at active area and shallow channel isolation area, argon plasma injects; Make that the silicon face at this edge is decrystallized; Thereby make that in ensuing grid oxic horizon growth course the grid oxic horizon growth rate that is positioned at this boundary edge is inner faster than active area, thereby can reduce so-called grid oxic horizon edge thickness attenuation effect; Thereby can improve device grids puncture voltage and gate breakdown life-span, improve the reliability of device.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the flow chart of the embodiment of the invention;
Fig. 2-Figure 10 is the product structure sketch map in the embodiment of the invention growth course.
Embodiment
As shown in Figure 1 is the flow chart of the embodiment of the invention, as Fig. 2 to shown in Figure 10 be product structure sketch map in the embodiment of the invention growth course.The manufacturing approach that embodiment of the invention shallow trench isolation leaves forms said shallow trench isolation and comprises from the processing step with said active area on said silicon substrate:
Step 1, as shown in Figure 2 forms hard mask layer on said silicon substrate, said hard mask layer is carried out photoetching and etching, defines said shallow plough groove isolation area; Said hard mask layer comprises sacrificial oxide layer and the silicon nitride layer that is formed at said surface of silicon successively.
Step 2, as shown in Figure 2 is that mask carries out etching to said silicon substrate with said hard mask layer, forms shallow trench.
Step 3, as shown in Figure 3 is carried out thermal oxidation technology, forms first cushion oxide layer on the surface of said shallow trench.
Step 4, as shown in Figure 4 is carried out chemical vapor deposition method, on said silicon substrate, forms the shallow trench isolating oxide layer, and the said said shallow trench of shallow trench isolating oxide layer complete filling also covers said silicon nitride layer surface.
Step 5, as shown in Figure 5 is carried out chemical mechanical milling tech, and the shallow trench isolating oxide layer on the said silicon nitride layer has been ground.
Step 6, as shown in Figure 6; Adopt wet-etching technology that said shallow trench isolating oxide layer is carried out etching; Control the height of said shallow trench isolating oxide layer, make said shallow trench isolating oxide layer etch into the position that is higher than said surfaces of active regions certain distance.
Step 7, as shown in Figure 7 is carried out wet method to said silicon nitride layer and is returned quarter, and said active area and said shallow trench isolation are exposed from the said sacrificial oxide layer at the marginal position place that has a common boundary.The thickness that said silicon nitride layer returns quarter is 200 dusts～600 dusts.
Step 8, as shown in Figure 8, carrying out decrystallized ion, to inject the monocrystalline silicon at the marginal position place that makes said active area decrystallized, promptly is formed with decrystallized ion implanted region.Said decrystallized ion is injected to the silicon ion injection or argon ion injects.
Step 9, as shown in Figure 9 adopts wet-etching technology to remove said silicon nitride layer and said sacrificial oxide layer.
Step 10, shown in figure 10 adopts thermal oxidation technology to form grid oxic horizon on the surface of said active area; In thermal oxidation process, the oxidation rate of the amorphous silicon at the marginal position place of said active area is accelerated, and the edge thickness of said grid oxic horizon is increased.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (4)
1. manufacturing approach that shallow trench isolation leaves; It is characterized in that: on silicon substrate, form shallow trench isolation from the processing step of active area in; The marginal position place that is included in said active area carries out the step that decrystallized ion injects; The marginal position place of said active area is that said active area and said shallow trench isolation leave the marginal position place that has a common boundary, and the monocrystalline silicon that said decrystallized ion injects the said surfaces of active regions that makes injection place is decrystallized.
2. the manufacturing approach that leaves of shallow trench isolation according to claim 1 is characterized in that: said decrystallized ion is injected to that silicon ion injects or argon ion injects.
3. the manufacturing approach that leaves of shallow trench isolation according to claim 1 is characterized in that: on said silicon substrate, form said shallow trench isolation and comprise from the processing step with said active area:
Step 1, on said silicon substrate, form hard mask layer, said hard mask layer is carried out photoetching and etching, define said shallow plough groove isolation area; Said hard mask layer comprises sacrificial oxide layer and the silicon nitride layer that is formed at said surface of silicon successively;
Step 2, be that mask carries out etching to said silicon substrate, form shallow trench with said hard mask layer;
Step 3, carry out thermal oxidation technology, form first cushion oxide layer on the surface of said shallow trench;
Step 4, carry out chemical vapor deposition method, on said silicon substrate, form the shallow trench isolating oxide layer, the said said shallow trench of shallow trench isolating oxide layer complete filling also covers said silicon nitride layer surface;
Step 5, carry out chemical mechanical milling tech, the shallow trench isolating oxide layer on the said silicon nitride layer has been ground;
Step 6, employing wet-etching technology carry out etching to said shallow trench isolating oxide layer, make said shallow trench isolating oxide layer etch into the position that is higher than said surfaces of active regions certain distance;
Step 7, said silicon nitride layer is carried out wet method return quarter, said active area and said shallow trench isolation are exposed from the said sacrificial oxide layer at the marginal position place that has a common boundary;
Step 8, carrying out decrystallized ion, to inject the monocrystalline silicon at the marginal position place that makes said active area decrystallized;
Step 9, employing wet-etching technology are removed said silicon nitride layer and said sacrificial oxide layer;
Step 10, employing thermal oxidation technology form grid oxic horizon on the surface of said active area; In thermal oxidation process, the oxidation rate of the amorphous silicon at the marginal position place of said active area is accelerated, and the edge thickness of said grid oxic horizon is increased.
4. the manufacturing approach that leaves like the said shallow trench isolation of claim 3 is characterized in that: the thickness that silicon nitride layer described in the step 7 returns quarter is 200 dusts～600 dusts.
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| CN2011100094823A CN102593038A (en) | 2011-01-17 | 2011-01-17 | Shallow trench isolation manufacturing method |
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| CN2011100094823A CN102593038A (en) | 2011-01-17 | 2011-01-17 | Shallow trench isolation manufacturing method |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576346A (en) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of trench gate in trench type MOS device |
| CN105097639A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN105655284A (en) * | 2014-11-13 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Formation method of trench isolation structure |
| CN106158613A (en) * | 2015-04-15 | 2016-11-23 | 上海格易电子有限公司 | A kind of method improving floating-gate device electronics retentivity and FGS floating gate structure |
| CN108831919A (en) * | 2018-05-04 | 2018-11-16 | 上海华力集成电路制造有限公司 | Flat-grid MOSFET |
| CN111855636A (en) * | 2019-04-29 | 2020-10-30 | 中国科学院微电子研究所 | SERS substrate |
| CN112038225A (en) * | 2020-08-06 | 2020-12-04 | 上海华力集成电路制造有限公司 | Method for forming gate oxide |
| CN112635313A (en) * | 2020-12-07 | 2021-04-09 | 华虹半导体(无锡)有限公司 | IO device gate oxide manufacturing method, terminal and storage medium |
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| US20050012173A1 (en) * | 2003-07-14 | 2005-01-20 | Yi-Ming Sheu | Narrow width effect improvement with photoresist plug process and STI corner ion implantation |
| CN101159237A (en) * | 2006-10-08 | 2008-04-09 | 上海华虹Nec电子有限公司 | Pre amorphous ion injection process for improving high-pressure gate oxide homogeneity |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576346A (en) * | 2013-10-29 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Preparation method of trench gate in trench type MOS device |
| CN104576346B (en) * | 2013-10-29 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | The preparation method of trench gate in groove type MOS device |
| CN105097639A (en) * | 2014-04-21 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacture method thereof |
| CN105655284A (en) * | 2014-11-13 | 2016-06-08 | 中芯国际集成电路制造(上海)有限公司 | Formation method of trench isolation structure |
| CN105655284B (en) * | 2014-11-13 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of groove isolation construction |
| CN106158613A (en) * | 2015-04-15 | 2016-11-23 | 上海格易电子有限公司 | A kind of method improving floating-gate device electronics retentivity and FGS floating gate structure |
| CN108831919A (en) * | 2018-05-04 | 2018-11-16 | 上海华力集成电路制造有限公司 | Flat-grid MOSFET |
| CN111855636A (en) * | 2019-04-29 | 2020-10-30 | 中国科学院微电子研究所 | SERS substrate |
| CN111855636B (en) * | 2019-04-29 | 2023-10-27 | 中国科学院微电子研究所 | SERS substrate |
| CN112038225A (en) * | 2020-08-06 | 2020-12-04 | 上海华力集成电路制造有限公司 | Method for forming gate oxide |
| CN112635313A (en) * | 2020-12-07 | 2021-04-09 | 华虹半导体(无锡)有限公司 | IO device gate oxide manufacturing method, terminal and storage medium |
| CN112635313B (en) * | 2020-12-07 | 2023-03-24 | 华虹半导体(无锡)有限公司 | IO device gate oxide manufacturing method, terminal and storage medium |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140103 |
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Application publication date: 20120718 |