CN112864236B - Preparation method of medium-high voltage shielded gate field effect transistor - Google Patents
Preparation method of medium-high voltage shielded gate field effect transistor Download PDFInfo
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- CN112864236B CN112864236B CN202110255880.7A CN202110255880A CN112864236B CN 112864236 B CN112864236 B CN 112864236B CN 202110255880 A CN202110255880 A CN 202110255880A CN 112864236 B CN112864236 B CN 112864236B
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- 230000005669 field effect Effects 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 45
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 38
- 238000005530 etching Methods 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 14
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000011049 filling Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 210000000746 body region Anatomy 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 10
- 238000001259 photo etching Methods 0.000 abstract description 7
- 239000000126 substance Substances 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 229910004298 SiO 2 Inorganic materials 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 238000006263 metalation reaction Methods 0.000 abstract description 2
- 238000002161 passivation Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 230000008901 benefit Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000009028 cell transition Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a preparation method of a medium-high voltage shielding gate field effect transistor, which adopts an advanced polycrystalline Chemical Mechanical Polishing (CMP) process and utilizes CMP to carry out SiO treatment 2 And silicon, stop at SiO 2 And (5) an interface. Compared with the traditional preparation method, the method has fewer photoetching times and achieves the effect required by the same polycrystalline tube product. The whole process flow comprises 6 times of photoetching of Deep tree, gate tree, npuse, cont, metal and Passivation, and compared with the conventional flow, one photoetching layer is reduced, and the process cost is reduced.
Description
Technical Field
The invention relates to the technical field of transistor preparation, in particular to a preparation method of a medium-high voltage shielding gate field effect transistor.
Background
The field oxide thickness in the trench of the medium-high voltage shielded gate field effect transistor (SGT) generally needs to be more than 5000 angstroms (the higher the voltage-withstanding requirement of the device is, the thicker the field oxide is), and a corresponding scheme needs to be selected in the manufacturing process to prevent the problem of control gate polysilicon residue caused by too high step difference between the formed protection ring and the cell transition region. At present, silicon dioxide is mainly adopted as a groove etching barrier layer in a medium-high voltage SGT manufacturing process in the industry, and after the silicon dioxide is removed after groove etching, thick field oxygen mentioned above starts to grow in a thermal oxidation mode, so that silicon dioxide with similar thickness can be generated on the surface of active area (active) silicon except the side wall and the bottom of the groove. After filling polysilicon in the groove, removing the polycrystal outside the groove of the active area cleanly by adopting polycrystalline Chemical Mechanical Polishing (CMP) or etchback, and etching away part of the polycrystal in the trench of the active area by photoetching; grinding the thick field oxide by using a CMP (chemical mechanical polishing) process, eliminating thick oxygen steps of the transition region, defining an active region by photoetching, and etching away a trench side wall thickness oxide layer of the active region by a wet method; this process requires a single photolithography to define the thin gate oxide region after CMP planarization.
Disclosure of Invention
The invention aims to provide a preparation method of a medium-high voltage shielded gate field effect transistor with simple process and reduced process cost.
In order to achieve the above purpose, the present invention provides a method for manufacturing a middle-high voltage shielded gate field effect transistor, comprising the following steps:
step 1: preparing a substrate;
step 2: generating a first silicon dioxide layer in an active area and a terminal area on the surface of the substrate;
step 3: etching a groove between the active region and the terminal region;
step 4: performing thermal oxidation field oxygen growth on the surface of the substrate to form thick field oxygen on the inner wall of the groove and the surface of the substrate;
step 5: filling polysilicon into the groove, and etching the polysilicon after filling so that the surface of the polysilicon is flush with the thick field oxide surface of the substrate;
step 6: the protection ring area of the substrate is glued and protected, the polysilicon of the primitive cell area of the substrate is etched, part of the polysilicon is removed, and the unetched polysilicon forms a shielding gate;
step 7: etching the whole thick field oxide on the surface of the substrate by adopting etching solution, and shielding part of the thick field oxide in the gate area;
step 8: adopting a mechanical polishing process to polish the polysilicon of the protruding part of the terminal area, so that the surface of the polysilicon of the terminal area is flush with the surface of the substrate;
step 9: performing thermal oxidation field oxygen growth on the surface of the substrate;
step 10: depositing a second layer of polysilicon on the thick field oxide surface of the shielding gate region; etching and polishing the polysilicon to form a control gate;
step 11: and performing conventional body region and source region ion implantation, back metal through holes and metal interconnection, back thinning and back metallization on the control gate to complete the manufacture of the whole medium-high voltage SGT transistor.
Further, in step 2, the thickness of the silicon dioxide layer is 4000 to 5000 angstroms.
Further, in step 3, the width of the trench is: 1 um-2 um, depth is: 5um to 7um, the spacing between adjacent grooves is as follows: 0.5um to 1um.
Further, in step 4, the thickness of the thick field oxide is 5000 to 7000 angstroms.
Further, in step 5, the polysilicon is etched using dry etching or mechanical polishing.
Further, in step 6, the polysilicon in the trench of the primitive cell region is etched by 1.2um to 1.7um.
Further, in step 7, the etching amount of the partial thick field oxide of the shielding gate region is 10-30% of the original thick field oxide of the shielding gate region.
Further, in step 9, the thickness of the regenerated thick field oxide is 500 to 1000 angstroms.
Further, the polysilicon of the control gate region is etched to be flush with the surface of the substrate.
Compared with the prior art, the invention has the advantages that: the invention adopts advanced polycrystalline Chemical Mechanical Polishing (CMP) process, utilizes CMP to carry out SiO treatment 2 And silicon, stop at SiO 2 And (5) an interface. Compared with the traditional preparation method, the method has fewer photoetching times and achieves the effect required by the same polycrystalline tube product. The whole process flow comprises Deep tree, gate tree, npuse, cont, metal and Passivation for 6 times, and compared with the conventional flow, the method has the advantage that one photoetching layer is reduced.
Drawings
FIG. 1 is a schematic view of a substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure of a silicon dioxide layer formed on a surface of a substrate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure of a substrate after trench etching in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a structure for generating a thick field culture on a surface of a substrate according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a structure of a trench filled with polysilicon according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure of a polysilicon etched in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure of the embodiment of the invention after etching thick field oxide;
FIG. 8 is a schematic diagram of the structure of the mechanically polished guard ring region polysilicon according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a structure of a polysilicon layer after a second deposition in accordance with an embodiment of the present invention;
fig. 10 is a schematic diagram of a transistor according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be further described below.
The invention provides a preparation method of a medium-high voltage shielding gate field effect transistor, which comprises the following steps:
step 1: preparing a substrate 1; as shown in fig. 1, the N-type arsenic/phosphorus doped substrate 1, resistivity range:
1-3 mohm.Cm; and (3) growing an N-type phosphorus epitaxial layer, wherein the resistivity is as follows: 250mohm.cm to 450mohm.cm, thickness: 5um to 10um.
Step 2: generating a first silicon dioxide layer 4 in an active region a and a terminal region b on the surface of the substrate 1; the thickness of the silicon dioxide layer 4 is 4000 to 5000 angstroms as shown in fig. 2.
Step 3: etching a groove between the active region a and the terminal region b; as shown in fig. 3, the width of the trench is: 1 um-2 um, depth is: 5um to 7um, the spacing between adjacent grooves is as follows: 0.5um to 1um.
Step 4: performing thermal oxidation field oxygen growth on the surface of the substrate 1 to form thick field oxygen 2 on the inner wall of the groove and the surface of the substrate 1; as shown in fig. 4, the thickness of the thick field oxide 2 is 5000-7000 angstroms, and the field oxide thickness affects the device breakdown voltage.
Step 5: and filling the polysilicon 3 into the groove, and etching the polysilicon 3 by dry etching or mechanical grinding after filling, wherein the surface ReCess of the polysilicon 3 is smaller than 1000A, so that the surface of the polysilicon 3 is flush with the surface of the thick field oxide 2 on the surface of the substrate 1, as shown in figure 5.
Step 6: and (3) gluing and protecting the protection ring area c of the substrate 1, etching the polycrystalline silicon 3 of the primitive cell area d of the substrate 1 to remove part of the polycrystalline silicon 3, forming a shielding gate by the unetched polycrystalline silicon 3, and etching the polycrystalline silicon 3 in the groove of the primitive cell area d by 1.2um to 1.7um, as shown in figure 6.
Step 7: etching the whole thick field oxide 2 on the surface of the substrate 1 by adopting etching solution, and shielding part of the thick field oxide 2 in the gate area; the etching amount of the partial thick field oxide 2 of the shielding gate region is 10-30% of the original thick field oxide 2 of the shielding gate region, as shown in fig. 7.
Step 8: polishing the polysilicon 3 of the protruding part of the terminal area b by adopting a mechanical polishing process, so that the surface of the polysilicon 3 of the terminal area b is flush with the surface of the substrate 1; as shown in fig. 8.
Step 9: performing thermal oxidation field oxygen growth on the surface of the substrate 1; the thickness of the regenerated thick field oxide 2 is 500-1000 angstroms; as shown in fig. 9.
Step 10: depositing a second layer of polysilicon 3 on the surface of the thick field oxide 2 of the shielding gate region; and the polysilicon 3 is etched and polished, and the polysilicon 3 of the control gate region is etched to be flush with the surface of the substrate 1, so as to form a control gate, as shown in fig. 9.
Step 11: conventional body region and source region ion implantation, back metal through hole and metal interconnection, back thinning and back metallization process are carried out on the control gate, and the whole middle-high voltage SGT transistor manufacture is completed, as shown in fig. 10.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (9)
1. The preparation method of the medium-high voltage shielded gate field effect transistor is characterized by comprising the following steps of:
step 1: preparing a substrate;
step 2: generating a first silicon dioxide layer in a cell region and a protection ring region on the surface of the substrate;
step 3: etching grooves in the primordial cell area and the protection ring area;
step 4: performing thermal oxidation field oxygen growth on the surface of the substrate to form thick field oxygen on the inner wall of the groove and the surface of the substrate;
step 5: filling polysilicon into the groove, and etching the polysilicon after filling so that the surface of the polysilicon is flush with the thick field oxide surface of the substrate;
step 6: the protection ring area of the substrate is glued and protected, the polysilicon of the primitive cell area of the substrate is etched, part of the polysilicon is removed, and the unetched polysilicon forms a shielding gate;
step 7: etching the whole thick field oxide on the surface of the substrate by adopting etching solution, and shielding part of the thick field oxide in the gate area;
step 8: adopting a mechanical polishing process to polish the polysilicon of the protruding part of the terminal area, so that the surface of the polysilicon of the terminal area is flush with the surface of the substrate;
step 9: performing thermal oxidation field oxygen growth on the surface of the substrate;
step 10: depositing a second layer of polysilicon on the thermal oxidation field oxygen of the shielding gate region; etching and polishing the polysilicon to form a control gate;
step 11: and performing conventional body region and source region ion implantation, back metal through holes and metal interconnection, back thinning and back metallization on the control gate to complete the manufacture of the whole medium-high voltage SGT transistor.
2. The method of manufacturing a medium-high voltage shielded gate field effect transistor according to claim 1, wherein in step 2, the thickness of the silicon dioxide layer is 4000 angstroms to 5000 angstroms.
3. The method of manufacturing a medium-high voltage shielded gate field effect transistor according to claim 1, wherein in step 3, the width of the trench is: 1um to 2um, the depth is: 5um to 7um, the spacing between adjacent grooves is as follows: 0.5um to 1um.
4. The method for manufacturing a medium-high voltage shielded gate field effect transistor according to claim 1, wherein in the step 4, the thickness of the thick field oxide is 5000-7000 angstroms.
5. The method of manufacturing a medium-high voltage shielded gate field effect transistor according to claim 1, wherein in step 5, the polysilicon is etched using dry etching or mechanical grinding.
6. The method for manufacturing a medium-high voltage shielded gate field effect transistor according to claim 1, wherein in step 6, polysilicon in the cell region trench is etched by 1.2um to 1.7um.
7. The method for manufacturing a medium-high voltage shielded gate field effect transistor according to claim 1, wherein in step 7, the etching amount of the partial thick field oxide of the shielded gate region is 10-30% of the original thick field oxide of the shielded gate region.
8. The method of manufacturing a medium-high voltage shielded gate field effect transistor according to claim 1, wherein in step 9, the thickness of the regenerated thick field oxide is 500-1000 angstroms.
9. The method of manufacturing a medium and high voltage shielded gate field effect transistor according to claim 1, wherein in step 10, the polysilicon of the control gate region is etched to be flush with the surface of the substrate.
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| CN112864236B true CN112864236B (en) | 2023-08-11 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298945A (en) * | 2016-09-30 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Shield grid trench MOSFET process |
| CN108039369A (en) * | 2017-11-30 | 2018-05-15 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8772865B2 (en) * | 2012-09-26 | 2014-07-08 | Semiconductor Components Industries, Llc | MOS transistor structure |
| US9553184B2 (en) * | 2014-08-29 | 2017-01-24 | Nxp Usa, Inc. | Edge termination for trench gate FET |
| TWI696288B (en) * | 2019-07-16 | 2020-06-11 | 力晶積成電子製造股份有限公司 | Shield gate mosfet and method for fabricating the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106298945A (en) * | 2016-09-30 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Shield grid trench MOSFET process |
| CN108039369A (en) * | 2017-11-30 | 2018-05-15 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
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