CN108039369A - Shield grid groove MOSFET and its manufacture method - Google Patents

Shield grid groove MOSFET and its manufacture method Download PDF

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Publication number
CN108039369A
CN108039369A CN201711234703.0A CN201711234703A CN108039369A CN 108039369 A CN108039369 A CN 108039369A CN 201711234703 A CN201711234703 A CN 201711234703A CN 108039369 A CN108039369 A CN 108039369A
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groove
polysilicon
layer
shielding
grid
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范让萱
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
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    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

The invention discloses a kind of shield grid groove MOSFET, is filled up completely groove formed with bottom oxidization layer, shielding polysilicon in the side of the groove of gate structure and lower surface；Define lower shielding polysilicon in bottom oxidization layer autoregistration and be self-aligned back and be carved into the bottom of groove；The shielding polysilicon surface that autoregistration is returned after carving is oxidized to form inter polysilicon isolation oxide layer；Bottom oxidization layer is gone back to the bottom of ditch groove after inter polysilicon isolation oxide layer is formed, and bottom oxidization layer and inter polysilicon the isolation oxide layer of Hui Kehou will shield polysilicon and surround and form top channel at the top of groove；There is gate oxide in the side of top channel and be filled with polysilicon gate.The invention also discloses a kind of manufacture method of shield grid groove MOSFET.The present invention can reduce the grid source and drain electricity of device while the threshold voltage of device is reduced, and can improve the consistency of thickness of inter polysilicon isolation oxide layer, make the corresponding capacitance of inter polysilicon isolation oxide layer stable and controllable.

Description

Shield grid groove MOSFET and its manufacture method
Technical field
The present invention relates to semiconductor integrated circuit manufacturing field, more particularly to a kind of shield grid (Shield Gate Trench, SGT) groove MOSFET；The invention further relates to a kind of manufacture method of shield grid groove MOSFET.
Background technology
As shown in Figure 1A to Fig. 1 P, be existing shield grid groove MOSFET each step of manufacture method in device architecture show It is intended to；This method forms the shield grid trench gate structure with up-down structure, in general, the conducting of shield grid groove MOSFET Area is made of multiple primitive unit cell periodic arrangements, and each primitive unit cell in the conducting area all includes a gate structure, has up-down structure Shield grid trench gate structure in, it is also necessary to a grid draw-out area is set, including the forming step of grid draw-out area is as follows：
Step 1: as shown in Figure 1A, there is provided semi-conductive substrate such as silicon substrate 101；In the surface shape of Semiconductor substrate 101 Into hard mask layers 201, hard mask layers 201 can use oxide layer, or add nitration case using oxide layer.
As shown in Figure 1B, hard mask layers 201 are performed etching using photoetching process afterwards and define grid forming region, Again Semiconductor substrate 101 is performed etching to form groove 202 for mask with hard mask layers 201 afterwards.It only show in Figure 1B The grid forming region of one primitive unit cell and the forming region of grid draw-out area, the groove of grid lead-out area is individually with mark 202a is marked, but groove 202 and 202a are actually to be formed at the same time using identical technique.
Step 2: as shown in Figure 1 C, remove hard mask layers 201.
As shown in figure iD, bottom oxidization layer 102 is formed in the side of groove 202 and lower surface.In groove 202a at the same time The bottom oxidization layer of formation is individually marked with mark 102a.
Step 3: as referring to figure 1E, source polysilicon 103 is filled in the groove 202, which is to shield Polysilicon is covered, source polysilicon 103 is generally connected with source electrode, for forming shield grid.The source polycrystalline formed at the same time in groove 202a Silicon is individually marked with mark 103a.
Step 4: as shown in fig. 1F, source polysilicon 103 carve, this time is carved the source outside groove 202 and 202a is more Crystal silicon 103 all removes, and groove 202 and the top of source polysilicon 103 in 202a are equal with Semiconductor substrate 101 respectively.
Step 5: as shown in Figure 1 G, forming photoresist layer 203, grid draw-out area is covered, will turned on by photoresist layer 203 Area opens, and carries out polysilicon afterwards and returns quarter, the source polysilicon 103 in groove 202 is returned to the bottom for being carved into groove.As shown in Fig. 1 G Understand, the top of the source polysilicon 103 of Hui Kehou has wedge angle, and wedge angle refer to shown in dotted line circle 204.
As shown in fig. 1H, carry out returning for bottom oxidization layer 103 afterwards to carve, bottom oxidization layer 103, which is returned, is carved into groove 202 Bottom.In practical application, the height that bottom oxidization layer 103 retains is by subsequently needing channel length to be formed to determine.By Fig. 1 H As can be seen that since groove 202 itself has incline structure so that the side of source polysilicon 103 is incline structure, is so being marked Corner shown in note 205, the angle between the side of source polysilicon 103 and the surface of bottom oxidization layer 103 can be less than 90 Degree.
Step 6: as shown in Figure 1 I, remove photoresist layer 203；Thermal oxidation technology is carried out afterwards forms gate oxide at the same time 104 and inter polysilicon isolation oxide layer 104a.The shortcomings that inter polysilicon isolation oxide layer 104a that this method is formed is polycrystalline The thickness of isolating oxide layer 104a is limited be subject to the thickness of gate oxide 104 between silicon, and the thickness of same gate oxide 104 also can Limited be subject to the thickness of inter polysilicon isolation oxide layer 104a so that gate oxide 104 can not continue to be thinned, because being thinned Inter polysilicon isolation oxide layer 104a also can be thinning afterwards, so as to influence between source polysilicon 103 and follow-up polysilicon gate 105 Isolation, easily produce the electric leakage in grid sources.
In addition, the other regions of thickness ratio of the inter polysilicon isolation oxide layer 104a in the corner shown in dotted line circle 205 It is thin, this easily to produce the electric leakage between grid source at dotted line circle 205.
In addition, the wedge angle defect in region shown in dotted line circle 204 finally also easily produces the electric leakage between grid source.
Step 7: as shown in figure iJ, form polysilicon gate 105.
Afterwards the step of, includes：As shown in figure iK, well region 106, source region 107 are formed.
As can be seen in 1L, interlayer film 108 is formed.As depicted in figure iM, the opening 109a of contact hole 109 is formed；Preferably, open After mouth 109a is formed, it is also necessary to form well region contact zone in the bottom of the contact hole 111a corresponding to the top of source region 107.Such as figure Shown in 1N, metal is filled in opening 109a afterwards and forms contact hole 109.
As shown in Fig. 1 O, front metal layer 110 is formed.
As shown in Fig. 1 O, front metal layer 110 is patterned using lithographic etch process and forms source electrode and grid respectively Pole, wherein source electrode are contacted by the source region 107 of contact hole 109 and bottom, well region contact zone and source polysilicon 103a, grid Contacted by contact hole 109 and polysilicon gate 105.Wherein source polysilicon 103 with source polysilicon 103a by being connected and passing through source Contact hole 109 at the top of polysilicon 103a is connected to source electrode, realizes the connection by source polysilicon 103 and source electrode.
As shown in Fig. 1 P, the back side for being formed in Semiconductor substrate 101 afterwards forms drain region and metal layer on back 111, by carrying on the back The composition drain electrode of face metal layer 111.
Above-mentioned trench gate mosfet device of the present invention is the shield grid groove MOSFET with up-down structure, by scheming Understand that spacer medium layer, that is, inter polysilicon isolation oxide layer 104a of gate oxide 104 and shield grid is formed at the same time shown in 1I, So gate oxide 104 just determines the isolation water between trench gate i.e. polysilicon gate 105 and shield grid i.e. source polysilicon 103 Flat, when 104 thinner thickness of gate oxide, the electric leakage that be easy to cause between grid source has thus fettered the structure in Low threshold Application in voltage devices.It follows that low threshold voltage device in order to obtain, it is necessary to relatively thin gate oxide 104 is used, And between relatively thin gate oxide 104 can be such that the thickness of inter polysilicon isolation oxide layer 104a reduces so as to increase grid source at the same time Electric leakage, can not solve in a conventional method reduce threshold voltage and reduce grid source and drain electricity between contradiction.
In addition, the device that existing method is formed also has the polycrystalline of the foregoing corner shown in dotted line circle 205 The other regions of the thickness ratio of isolating oxide layer 104a is thin between silicon, this easily to produce at dotted line circle 205 between grid source Electric leakage.And the wedge angle defect in region shown in dotted line circle 204 finally also easily produces the electric leakage between grid source.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of shield grid groove MOSFET, can reduce the threshold value of device The grid source and drain electricity of device is reduced while voltage.For this reason, the present invention also provides a kind of manufacture method of shield grid groove MOSFET.
In order to solve the above technical problems, the conducting area of shield grid groove MOSFET provided by the invention is by multiple primitive unit cell cycles Property rearrange, it is described conducting area each primitive unit cell all include a gate structure, the gate structure includes：
The groove being formed in Semiconductor substrate, in the side of the groove and lower surface formed with bottom oxidization layer, The groove formed with the bottom oxidization layer is filled up completely by shielding polysilicon.
The lower shielding polysilicon is defined in the autoregistration of the bottom oxidization layer to be self-aligned back and be carved into the groove Bottom and autoregistration return the shielding polysilicon surface after carving formed with wedge angle defect.
The shielding polysilicon surface that autoregistration is returned after carving is oxidized to form inter polysilicon isolation oxide layer, the polycrystalline Between silicon isolating oxide layer by it is described shielding polysilicon surface wedge angle defect expressivity.
The bottom oxidization layer is gone back to the bottom for carving the groove after the inter polysilicon isolation oxide layer is formed, and is returned and is carved The bottom oxidization layer and inter polysilicon isolation oxide layer afterwards surrounds the shielding polysilicon and in the groove Top channel is formed on top.
There is gate oxide in the Semiconductor substrate side of the top channel, in the institute formed with the gate oxide State and polysilicon gate is filled with top channel.
A further improvement is that each primitive unit cell in the conducting area further includes：
The well region of the second conduction type of the semiconductor substrate surface is formed at, the Semiconductor substrate has first to lead Electric type doping；The junction depth of the well region is less than the depth of the top channel, and the polysilicon gate covers the trap from side Area and by the polysilicon gate side covering the well region surface be used for form raceway groove.
It is formed at the source region of the first conduction type heavy doping on the well region surface.
Interlayer film is covered in the semiconductor substrate surface outside the region surface and the groove of the groove.
The contact hole of corresponding interlayer film is formed through at the top of the source region and is all connected to by front metal layer group Into source electrode.
The contact hole of corresponding interlayer film is formed through at the top of the polysilicon gate and is connected to by front metal The grid of layer composition.
A further improvement is that shield grid groove MOSFET further includes：
The drain region of first conduction type heavy doping, the back side for the Semiconductor substrate being formed at after being thinned, in the leakage The back side in area is formed with metal layer on back as drain electrode.
A further improvement is that shield grid groove MOSFET further includes：Grid draw-out area outside the conducting area, institute State the deriving structure formed with the shielding polysilicon in grid draw-out area, the groove of the deriving structure and the gate structure Groove communicate, be also formed with bottom oxidization layer in the side of the groove of the deriving structure and lower surface, it is described to draw knot Also it is filled up completely in the groove of structure by shielding polysilicon, the bottom oxidization layer of the deriving structure and the top of shielding polysilicon are all It is equal with the top surface of corresponding groove, the shielding polysilicon of the gate structure and the shielding polysilicon of the deriving structure The contact hole formed at the top of the shielding polysilicon for being connected and passing through the deriving structure is connected to the source electrode.
A further improvement is that the Semiconductor substrate is silicon substrate, in the surface of silicon formed with silicon epitaxy layer, The groove is located in the silicon epitaxy layer.
A further improvement is that it is heavily doped to further include the second conduction type in the bottom for the contact hole being in contact with the source region Miscellaneous well region contact zone.
A further improvement is that shield grid groove MOSFET is N-type device, the first conduction type is N-type, the second conductive-type Type is p-type；Alternatively, shield grid groove MOSFET is P-type device, the first conduction type is p-type, and the second conduction type is N-type.
In order to solve the above technical problems, in the manufacture method of shield grid groove MOSFET provided by the invention, shield grid ditch The conducting area of groove MOSFET is made of multiple primitive unit cell periodic arrangements, and each primitive unit cell in the conducting area all includes a grid knot Structure, gate structure are formed using following steps：
Step 1: providing semi-conductive substrate, the semiconductor substrate surface forms hard mask layers, using photoetching process Grid forming region is defined, is removed the hard mask layers of the grid forming region using etching technics.
Step 2: anisotropic etching is carried out to the Semiconductor substrate using the hard mask layers after etching as mask Form groove；The hard mask layers are removed afterwards.
Step 3: forming bottom oxidization layer in the side of the groove and lower surface, the bottom oxidization layer also extends Onto the surface outside the groove.
Step 4: carrying out first time polysilicon deposition forms shielding polysilicon by formed with described in the bottom oxidization layer Groove is filled up completely；The shielding polysilicon is also extended on the surface outside the groove.
The shielding polysilicon outside the groove is removed and by the trench area Step 5: carrying out polysilicon and returning to carve The surface of the shielding polysilicon in domain time is carved into equal with the top surface of the groove.
Step 6: using the bottom oxidization layer as autoregistration define condition to it is described conducting area the shielding polysilicon into The bottom carved and make the shielding polysilicon be etched into the groove is gone back in row autoregistration, and the shielding polycrystalline after carving is returned in autoregistration Silicon face is formed with wedge angle defect.
Step 7: carrying out oxidation to the shielding polysilicon surface forms inter polysilicon isolation oxide layer, the polysilicon Between isolating oxide layer by it is described shielding polysilicon surface wedge angle defect expressivity.
Step 8: it is complete by the groove gap at the top of inter polysilicon isolation oxide layer to form the first photoresist layer Filling.
Be carved into the bottom of the groove Step 9: the bottom oxidization layer is returned, the bottom oxidization layer of Hui Kehou and The shielding polysilicon is surrounded and forms top channel at the top of the groove by the inter polysilicon isolation oxide layer.
Step 10: removing first photoresist layer, gate oxide is formed in the side of the top channel.
Step 11: carry out second of polysilicon deposition forms polysilicon gate in the top channel.
A further improvement is that step is further included after step 11：
Carry out the second conductive type ion and be infused in the Semiconductor substrate to form well region, the Semiconductor substrate has First conduction type adulterates.
The source for carrying out the first conduction type heavy doping is infused in the well region surface formation source region.
Thermal annealing is carried out to the well region and the source region and promotes technique.
Form interlayer film, what the interlayer film was covered in outside the region surface and the groove of the groove described partly leads Body substrate surface.
The contact hole and front metal layer through the interlayer film are formed, chemical wet etching shape is carried out to the front metal layer Into source electrode and grid, the source electrode passes through contact hole and the polysilicon by contact hole and the source contact, the grid Grid contact.
The Semiconductor substrate back side is carried out to be thinned and formed the drain region of heavy doping, the back of the body is formed at the back side in the drain region Face metal layer is as drain electrode.
A further improvement is that shield grid groove MOSFET further includes the grid draw-out area outside the conducting area, institute State the deriving structure formed with the shielding polysilicon in grid draw-out area, the groove of the deriving structure and the gate structure Groove communicate and formed at the same time；Bottom oxide is also formed simultaneously with the side of the groove of the deriving structure and lower surface Layer, also it is filled up completely in the groove of the deriving structure by shielding polysilicon.
The polysilicon of step 5 is returned after the completion of quarter formed with the second photoresist layer for covering the grid draw-out area, described Second photoresist layer removes after the autoregistration of the shielding polysilicon of step 6 is returned and carved, the shielding polycrystalline of the deriving structure The top of silicon is equal with the top surface of corresponding groove.
First photoresist layer described in step 8 at the same time covers the grid draw-out area, makes the bottom oxygen of step 9 The top for changing the bottom oxidization layer of the deriving structure after the completion of layer time is carved is equal with the top surface of corresponding groove.
The shielding polysilicon of the gate structure is connected with the shielding polysilicon of the deriving structure and is drawn by described Go out the contact hole formed at the top of the shielding polysilicon of structure and be connected to the source electrode.
A further improvement is that the Semiconductor substrate is silicon substrate, in the surface of silicon formed with silicon epitaxy layer, The groove is located in the silicon epitaxy layer.
A further improvement is that hard mask layers are made of oxide layer described in step 1.
A further improvement is that the inter polysilicon isolation oxide layer is formed using thermal oxidation technology；The gate oxide Formed using thermal oxidation technology.
A further improvement is that the contact hole opening formed after, it is metal filled before, be additionally included in and the source region The bottom for the contact hole being in contact carries out the step of the first conduction type heavily-doped implant forms well region contact zone.
A further improvement is that shield grid groove MOSFET is N-type device, the first conduction type is N-type, the second conductive-type Type is p-type；Alternatively, shield grid groove MOSFET is P-type device, the first conduction type is p-type, and the second conduction type is N-type.
Shielding polysilicon in the present invention is defined before bottom oxidization layer is returned and carved using the autoregistration of bottom oxidization layer to carry out Return to carve and formed, can so be aoxidized to form polysilicon spacer at the top of shielding polysilicon using the definition of bottom oxidization layer at the same time From oxide layer, inter polysilicon isolation oxide layer can will shield the wedge angle defect expressivity of polysilicon surface, more so as to eliminate shielding Electric leakage caused by wedge angle defect at the top of crystal silicon is the electric leakage between grid source.
In addition, the inter polysilicon isolation oxide layer of the present invention is formed before gate oxide, so the polycrystalline of the present invention The formation process of isolating oxide layer and gate oxide is independent mutually between silicon, both bad limitations mutually of thickness so that the present invention Relatively thin gate oxide and thicker inter polysilicon isolation oxide layer can be formed at the same time, wherein relatively thin gate oxide is convenient The adjusting of the threshold voltage of device is so as to reducing the threshold voltage of device；And thicker inter polysilicon isolation oxide layer then can Realize the electric leakage between the grid source for reducing device.
In addition, the present invention bottom oxidization layer and inter polysilicon isolation oxide layer after bottom oxidization layer is returned and carved are formed together The structure of shielding polysilicon is surrounded, the surface that bottom oxidization layer after carving is returned this avoid bottom oxidization layer in the prior art can be low It is less than the structure of 90 bottom corner in an angle so as to shape in the surface of shielding polysilicon, so as to be avoided that this angle is small The thickness of inter polysilicon isolation oxide layer caused by bottom corner in 90 is less, so as to further reduce the grid source of device Between electric leakage.
In addition, independently forming the structure of inter polysilicon isolation oxide layer in the present invention, inter polysilicon can be made to isolate oxide layer With preferable consistency of thickness so that the capacitance produced by inter polysilicon isolation oxide layer is stable and controllable.
Brief description of the drawings
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments：
Figure 1A-Fig. 1 P are the device architecture schematic diagrames in each step of manufacture method of existing shield grid groove MOSFET；
Fig. 2 is the structure diagram of shield grid groove MOSFET of the embodiment of the present invention；
Fig. 3 A- Fig. 3 S are the device architecture schematic diagrames in each step of present invention method.
Embodiment
As shown in Fig. 2, it is the structure diagram of shield grid groove MOSFET of the embodiment of the present invention；The embodiment of the present invention shields The conducting area of gate groove MOSFET is made of multiple primitive unit cell periodic arrangements, and each primitive unit cell in the conducting area all includes a grid Structure, the gate structure of shield grid groove MOSFET of the embodiment of the present invention is up-down structure, and grid are additionally provided with outside area turning on Pole draw-out area, also shows grid draw-out area in Fig. 2 at the same time.The gate structure includes：
The groove being formed in Semiconductor substrate 1, in the side of the groove and lower surface formed with bottom oxidization layer 2, the groove formed with the bottom oxidization layer 2 is filled up completely by shielding polysilicon 3.
Preferably, the Semiconductor substrate 1 is silicon substrate, in the surface of silicon formed with silicon epitaxy layer, the ditch Groove is located in the silicon epitaxy layer.
The shielding polysilicon 3, which is self-aligned back, under the autoregistration definition of the bottom oxidization layer 2 is carved into the groove Bottom and autoregistration return carve after 3 surface of shielding polysilicon formed with wedge angle defect.
3 surface of shielding polysilicon that autoregistration is returned after carving is oxidized to form inter polysilicon isolation oxide layer 4, described more Isolating oxide layer 4 is by the wedge angle defect expressivity on shielding polysilicon 3 surface between crystal silicon.
The bottom oxidization layer 2 is gone back to the bottom for carving the groove after the inter polysilicon isolation oxide layer 4 is formed, and is returned The bottom oxidization layer 2 and inter polysilicon isolation oxide layer 4 after quarter surround the shielding polysilicon 3 and in the ditch Top channel is formed on the top of groove.
There is gate oxide 5 in 1 side of the Semiconductor substrate of the top channel, formed with the gate oxide 5 The top channel in be filled with polysilicon gate 6.
Each primitive unit cell in the conducting area further includes：
It is formed at the well region 7 of second conduction type on 1 surface of Semiconductor substrate, the Semiconductor substrate 1 has the One conduction type adulterates；The junction depth of the well region 7 is less than the depth of the top channel, and the polysilicon gate 6 is covered from side The well region 7 and by 6 side of polysilicon gate covering 7 surface of the well region be used for form raceway groove.
It is formed at the source region 8 of the first conduction type heavy doping on 7 surface of well region.
Interlayer film 9 is covered in 1 surface of the Semiconductor substrate outside the region surface and the groove of the groove.
The contact hole 10 of corresponding interlayer film 9 is formed through at the top of source region 8 and is all connected to by front metal The source electrode of the composition of layer 11.Preferably, the second conduction type weight is further included in the bottom for the contact hole 10 being in contact with the source region 8 The well region contact zone of doping.
The contact hole 10 of corresponding interlayer film 9 is formed through at the top of the polysilicon gate 6 and is connected to by front The grid that metal layer 11 forms.
Shield grid groove MOSFET further includes：
The drain region of first conduction type heavy doping, the back side for the Semiconductor substrate 1 being formed at after being thinned, in the leakage The back side in area is formed with metal layer on back 12 as drain electrode.
Grid outside the conducting area draws plot structure and is：Formed with the shielding polycrystalline in the grid draw-out area The groove of the deriving structure of silicon 3, the groove of the deriving structure and the gate structure communicates, in the groove of the deriving structure Side and lower surface be also formed with bottom oxidization layer 2a, it is also complete by shielding polysilicon 3a in the groove of the deriving structure Top surface phase of the top of filling, the bottom oxidization layer 2a of the deriving structure and shielding polysilicon 3a all with corresponding groove Flat, the shielding polysilicon 3 of the gate structure is connected and by the extraction with the shielding polysilicon 3a of the deriving structure The contact hole 10 formed at the top of the shielding polysilicon 3a of structure is connected to the source electrode.
In the embodiment of the present invention, shield grid groove MOSFET is N-type device, and the first conduction type is N-type, the second conductive-type Type is p-type.Also can be in other embodiments：Shield grid groove MOSFET is P-type device, and the first conduction type is p-type, second Conduction type is N-type.
It is the device architecture schematic diagram in each step of present invention method as shown in Fig. 3 A to Fig. 3 S.It is of the invention real Apply in a manufacture method for shield grid groove MOSFET, the conducting area of shield grid groove MOSFET is by multiple primitive unit cell periodic arrangements Composition, each primitive unit cell in the conducting area all include a gate structure, the grid of shield grid groove MOSFET of the embodiment of the present invention Structure is up-down structure, is additionally provided with grid draw-out area outside area turning on, comes one below in conjunction with the structure of grid draw-out area Rise and illustrate, the gate structure in the embodiment of the present invention is formed using following steps：
Step 1: as shown in Figure 3A, there is provided semi-conductive substrate 1,1 surface of Semiconductor substrate form hard mask layers 301, grid forming region is defined using photoetching process, is covered the hard of the grid forming region using etching technics Mold layer 301 removes.Hard mask layers 301 can use oxide layer, or add nitration case using oxide layer.
In present invention method, the Semiconductor substrate 1 is silicon substrate, outside the surface of silicon is formed with silicon Prolong layer, the groove 302 is located in the silicon epitaxy layer.
It is mask to the Semiconductor substrate 1 with the hard mask layers 301 after etching Step 2: as shown in Figure 3B Carry out anisotropic etching and form groove 302.It only show a gate structure in Fig. 3 B, also show positioned at conducting area The groove 302a of grid draw-out area.
As shown in Figure 3 C, the hard mask layers 301 are removed afterwards.
Step 3: as shown in Figure 3D, bottom oxidization layer 2, the bottom are formed in the side of the groove 302 and lower surface Portion's oxide layer 2 is also extended on the surface outside the groove 302.The bottom oxidization layer of grid draw-out area is individually with mark 2a tables Show.
Step 4: as shown in FIGURE 3 E, carrying out first time polysilicon deposition formation shielding polysilicon 3 will be formed with the bottom The groove 302 of oxide layer 2 is filled up completely；The shielding polysilicon 3 is also extended on the surface outside the groove 302.Grid The shielding polysilicon of pole draw-out area is represented with mark 3a.
Step 5: as illustrated in Figure 3 F, polysilicon time quarter remove the shielding polysilicon 3 outside the groove 302 And the surface of the shielding polysilicon 3 in 302 region of groove is returned to the top surface phase being carved into the groove 302 It is flat.The shielding polysilicon 3a of grid draw-out area also at the same time by return be carved into it is equal with the top surface of the groove 302.
Step 6: as shown in Figure 3 G, form the second photoresist layer 303 and simultaneously carry out photoetching process, the exposure by photoetching and The grid draw-out area is covered and opens conducting area by the second photoresist layer 303 after development.
In area is turned on, with the bottom oxidization layer 2 for autoregistration define condition to it is described conducting area the shielding it is more Crystal silicon 3 carries out autoregistration and goes back to the bottom carved and make the shielding polysilicon 3 be etched into the groove 302, after autoregistration time is carved 3 surface of the shielding polysilicon is formed with wedge angle defect.
Second photoresist layer 303 is removed afterwards, is removed after quarter is returned in the autoregistration of the shielding polysilicon 3, it is described The shielding polysilicon 3a of deriving structure is not etched so that the top of the shielding polysilicon 3a of the deriving structure and corresponding ditch The top surface of groove 302a also keeps equal.
Step 7: as shown in figure 3h, oxidation is carried out to 3 surface of the shielding polysilicon and forms inter polysilicon isolation oxide layer 4, the inter polysilicon isolates oxide layer 4 by the wedge angle defect expressivity on 3 surface of the shielding polysilicon, the elimination energy of wedge angle defect Reduce the grid source and drain electricity of device.
In step 7, the thickness of the inter polysilicon isolation oxide layer 4 can be adjusted, by increasing the polysilicon spacer The grid source and drain of device electricity is reduced from the thickness of oxide layer 4.
Meanwhile the structure for independently forming the inter polysilicon isolation oxide layer 4 can cause the inter polysilicon isolation oxidation The thickness of layer 4 is uniformly adjustable so that the consistency of thickness of the inter polysilicon isolation oxide layer 4 is preferable, can be so that the polycrystalline The capacitance structure that isolating oxide layer 4 forms between silicon is stable and controllable.
Preferably, the inter polysilicon isolation oxide layer 4 is formed using thermal oxidation technology.The inter polysilicon isolation oxidation Layer 4 can also use the overlaying structure of thermal oxide layer and the oxide layer of depositing operation formation, that is, use thermal oxide by wedge angle defect The oxide layer that one layer of depositing operation of superposition is formed in the case of elimination.
Step 8: as shown in fig. 31, the first photoresist layer 304 is formed by 4 top of inter polysilicon isolation oxide layer 302 gap of groove is filled up completely.
The first photoresist layer 304 is exposed and developed, it is necessary to carry out photoetching process as shown in figure 3j, after development 302 gap of the groove at 4 top of inter polysilicon isolation oxide layer is filled up completely and draws grid by one photoresist 304 Go out area's covering.
Step 9: as shown in Fig. 3 K, carry out time quarter returning the bottom oxidization layer 2 for oxide layer and be carved into the groove 302 Bottom, the bottom oxidization layer 2 of Hui Kehou and the inter polysilicon isolation oxide layer 4 by it is described shielding polysilicon 3 surround And form top channel 305 at the top of the groove 302.
In practical situation, to the bottom oxidization layer 2 return quarter amount need according to the follow-up required length of raceway groove into Row determines.
The bottom oxidization layer 2 return carve after the completion of the deriving structure bottom oxidization layer 2a top and corresponding groove 302 top surface is equal.
Step 10: as shown in figure 3l, remove first photoresist layer 304.
As shown in fig.3m, gate oxide 5 is formed in the side of the top channel 305.
Preferably, the gate oxide 5 is formed using thermal oxidation technology.
Step 11: as shown in Fig. 3 N, carry out second of polysilicon deposition and form polysilicon in the top channel 305 Grid 6.
Gate structure further includes step after being formed：
As shown in Fig. 3 O, carry out the second conductive type ion and be infused in formation well region 7 in the Semiconductor substrate 1, it is described Semiconductor substrate 1 is adulterated with the first conduction type.
As shown in Fig. 3 P, the source for carrying out the first conduction type heavy doping is infused in 7 surface of the well region formation source region 8.
As shown in Fig. 3 P, thermal annealing is carried out to the well region 7 and the source region 8 and promotes technique.
As shown in Fig. 3 P, interlayer film 9 is formed, the interlayer film 9 is covered in the region surface of the groove 302 and described 1 surface of the Semiconductor substrate outside groove 302.Interlayer film 9 is also covered in grid draw-out area.
As shown in Fig. 3 Q, the opening 10a of the contact hole 10 through the interlayer film 9 is formed；Preferably, in the contact hole 10 opening 10a formed after, it is metal filled before, the bottom for being additionally included in the contact hole 10 being in contact with the source region 8 carries out the One conduction type heavily-doped implant forms the step of well region contact zone.
As shown in Fig. 3 R, filling metal forms the contact hole 10 in opening 10a.
As shown in Fig. 3 S, formed front metal layer 11, to the front metal layer 11 carry out chemical wet etching formed source electrode and Grid, the source electrode are contacted by contact hole 10 and the source region 8, and the grid passes through contact hole 10 and the polysilicon gate 6 Contact.In the embodiment of the present invention, the groove 302a of the deriving structure formed in the grid draw-out area and the grid knot The groove 302 of structure communicates, and the shielding polysilicon 3 of the gate structure is connected simultaneously with the shielding polysilicon 3a of the deriving structure The source electrode is connected to by the contact hole 10 formed at the top of the shielding polysilicon 3a of the deriving structure.
As shown in Fig. 2, 1 back side of Semiconductor substrate be thinned and forms the drain region of heavy doping, in the drain region The back side formed metal layer on back 12 as drain electrode.
In present invention method, shield grid groove MOSFET is N-type device, and the first conduction type is N-type, and second leads Electric type is p-type.Also can be in other embodiments method：Shield grid groove MOSFET is P-type device, and the first conduction type is P-type, the second conduction type are N-type.
Shielding polysilicon 3 in the embodiment of the present invention utilizes the autoregistration of bottom oxidization layer 2 before bottom oxidization layer 2 is returned and carved Definition carve and formed, and so can aoxidize to be formed at the top of shielding polysilicon 3 using the definition of bottom oxidization layer 2 at the same time Inter polysilicon isolates oxide layer 4, and inter polysilicon isolation oxide layer 4 can will shield the wedge angle defect expressivity on 3 surface of polysilicon, so that Electric leakage caused by the wedge angle defect at 3 top of shielding polysilicon can be eliminated is the electric leakage between grid source.
In addition, the inter polysilicon isolation oxide layer 4 of the embodiment of the present invention is formed before gate oxide 5, so this hair The inter polysilicon isolation oxide layer 4 of bright embodiment and the formation process of gate oxide 5 are independent mutually, both thickness is bad mutually Limitation so that the embodiment of the present invention can form relatively thin gate oxide 5 and thicker inter polysilicon isolation oxide layer at the same time 4, wherein the adjusting of the threshold voltage of relatively thin 5 convenient device of gate oxide is so as to reducing the threshold voltage of device；It is and thicker Inter polysilicon isolation oxide layer 4 can then realize reduce device grid source between electric leakage.
In addition, bottom oxidization layer 2 and inter polysilicon isolation oxide layer after bottom oxidization layer 2 returns quarter of the embodiment of the present invention 4 form the structure for surrounding shielding polysilicon 3 together, and bottom oxide after carving is returned this avoid bottom oxidization layer 2 in the prior art The surface of layer 2 can be less than the surface of shielding polysilicon 3 so as to which shape is less than the structure of 90 bottom corner in an angle, so as to Avoid the thickness of the inter polysilicon isolation oxide layer 4 caused by bottom corner of this angle less than 90 less, so as into one Step reduces the electric leakage between the grid source of device.
In addition, independently forming the structure of inter polysilicon isolation oxide layer 4 in the embodiment of the present invention, inter polysilicon can be isolated Oxide layer 4 has preferable consistency of thickness so that the capacitance produced by inter polysilicon isolation oxide layer 4 is stable and controllable.
The present invention is described in detail above by specific embodiment, but these not form the limit to the present invention System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these also should It is considered as protection scope of the present invention.

Claims (15)

1. shield grid groove MOSFET, it is characterised in that periodically arranged by multiple primitive unit cells in the conducting area of shield grid groove MOSFET Row composition, each primitive unit cell in the conducting area all include a gate structure, and the gate structure includes：
The groove being formed in Semiconductor substrate, in the side of the groove and lower surface formed with bottom oxidization layer, shielding The groove formed with the bottom oxidization layer is filled up completely by polysilicon；
Define the lower shielding polysilicon in the autoregistration of the bottom oxidization layer and be self-aligned back and be carved into the bottom of the groove And autoregistration returns the shielding polysilicon surface after carving formed with wedge angle defect；
The shielding polysilicon surface that autoregistration is returned after carving is oxidized to form inter polysilicon isolation oxide layer, the inter polysilicon Isolating oxide layer by it is described shielding polysilicon surface wedge angle defect expressivity；
The bottom oxidization layer is gone back to the bottom for carving the groove after the inter polysilicon isolation oxide layer is formed, Hui Kehou's The bottom oxidization layer and inter polysilicon isolation oxide layer surround the shielding polysilicon and at the top of the groove Form top channel；
There is gate oxide in the Semiconductor substrate side of the top channel, on the top formed with the gate oxide Polysilicon gate is filled with portion's groove.
2. shield grid groove MOSFET as claimed in claim 1, it is characterised in that each primitive unit cell in the conducting area further includes：
The well region of the second conduction type of the semiconductor substrate surface is formed at, the Semiconductor substrate has the first conductive-type Type adulterates；The junction depth of the well region is less than the depth of the top channel, the polysilicon gate from side cover the well region and It is used to form raceway groove by the well region surface of polysilicon gate side covering；
It is formed at the source region of the first conduction type heavy doping on the well region surface；
Interlayer film is covered in the semiconductor substrate surface outside the region surface and the groove of the groove；
The contact hole of corresponding interlayer film is formed through at the top of the source region and is all connected to what is be made of front metal layer Source electrode；
The contact hole of corresponding interlayer film is formed through at the top of the polysilicon gate and is connected to by front metal layer group Into grid.
3. shield grid groove MOSFET as claimed in claim 2, it is characterised in that shield grid groove MOSFET further includes：
The drain region of first conduction type heavy doping, the back side for the Semiconductor substrate being formed at after being thinned, in the drain region The back side is formed with metal layer on back as drain electrode.
4. shield grid groove MOSFET as claimed in claim 2, it is characterised in that shield grid groove MOSFET further includes：Position In the grid draw-out area turned on outside area, the deriving structure formed with the shielding polysilicon in the grid draw-out area, institute The groove of the groove and the gate structure of stating deriving structure communicates, in the side of the groove of the deriving structure and lower surface Bottom oxidization layer is also formed with, is also filled up completely in the groove of the deriving structure by shielding polysilicon, the deriving structure Bottom oxidization layer and the top of shielding polysilicon are all equal with the top surface of corresponding groove, and the shielding of the gate structure is more Formed at the top of the shielding polysilicon that crystal silicon is connected with the shielding polysilicon of the deriving structure and passes through the deriving structure Contact hole is connected to the source electrode.
5. shield grid groove MOSFET as claimed in claim 1, it is characterised in that：The Semiconductor substrate is silicon substrate, The surface of silicon is located in the silicon epitaxy layer formed with silicon epitaxy layer, the groove.
6. shield grid groove MOSFET as claimed in claim 2, it is characterised in that：In the contact hole being in contact with the source region Bottom further include the well region contact zone of the second conduction type heavy doping.
7. the shield grid groove MOSFET as described in Claims 2 or 3 or 6, it is characterised in that：Shield grid groove MOSFET is N Type device, the first conduction type are N-type, and the second conduction type is p-type；Alternatively, shield grid groove MOSFET is P-type device, the One conduction type is p-type, and the second conduction type is N-type.
A kind of 8. manufacture method of shield grid groove MOSFET, it is characterised in that the conducting Qu Youduo of shield grid groove MOSFET A primitive unit cell periodic arrangement composition, each primitive unit cell in the conducting area all include a gate structure, and gate structure is using following step It is rapid to be formed：
Step 1: providing semi-conductive substrate, the semiconductor substrate surface forms hard mask layers, is defined using photoetching process Go out grid forming region, removed the hard mask layers of the grid forming region using etching technics；
Formed Step 2: carrying out anisotropic etching to the Semiconductor substrate as mask using the hard mask layers after etching Groove；The hard mask layers are removed afterwards；
Step 3: forming bottom oxidization layer in the side of the groove and lower surface, the bottom oxidization layer also extends into institute State on the surface outside groove；
Step 4: carrying out first time polysilicon deposition forms shielding polysilicon by the groove formed with the bottom oxidization layer It is filled up completely；The shielding polysilicon is also extended on the surface outside the groove；
The shielding polysilicon outside the groove is removed and by the trench region Step 5: carrying out polysilicon and returning to carve The surface time of the shielding polysilicon is carved into equal with the top surface of the groove；
The shielding polysilicon in the conducting area is carried out certainly Step 6: defining condition as autoregistration using the bottom oxidization layer The bottom carved and make the shielding polysilicon be etched into the groove is directed at go back to, the shielding polysilicon table after carving is returned in autoregistration Face is formed with wedge angle defect；
Step 7: carrying out oxidation to the shielding polysilicon surface forms inter polysilicon isolation oxide layer, the polysilicon spacer From oxide layer by it is described shielding polysilicon surface wedge angle defect expressivity；
The groove gap that the inter polysilicon is isolated at the top of oxide layer is filled out completely Step 8: forming the first photoresist layer Fill；
The bottom of the groove is carved into Step 9: the bottom oxidization layer is returned, the bottom oxidization layer of Hui Kehou and described Inter polysilicon isolates oxide layer and surrounds the shielding polysilicon and form top channel at the top of the groove；
Step 10: removing first photoresist layer, gate oxide is formed in the side of the top channel；
Step 11: carry out second of polysilicon deposition forms polysilicon gate in the top channel.
9. the manufacture method of shield grid groove MOSFET as claimed in claim 8, it is characterised in that：After step 11 also Including step：
Carry out the second conductive type ion and be infused in the Semiconductor substrate to form well region, the Semiconductor substrate has first Conduction type adulterates；
The source for carrying out the first conduction type heavy doping is infused in the well region surface formation source region；
Thermal annealing is carried out to the well region and the source region and promotes technique；
Interlayer film is formed, the interlayer film is covered in the semiconductor lining outside the region surface and the groove of the groove Basal surface；
The contact hole and front metal layer through the interlayer film are formed, carrying out chemical wet etching to the front metal layer forms source Pole and grid, the source electrode are connect by contact hole and the source contact, the grid by contact hole and the polysilicon gate Touch；
The Semiconductor substrate back side is carried out to be thinned and formed the drain region of heavy doping, back-side gold is formed at the back side in the drain region Belong to layer as drain electrode.
10. the manufacture method of shield grid groove MOSFET as claimed in claim 9, it is characterised in that：Shield gate groove MOSFET is further included in the grid draw-out area turned on outside area, the grid draw-out area formed with the shielding polysilicon Deriving structure, the groove of the groove of the deriving structure and the gate structure communicates and formed at the same time；Knot is drawn described The side of the groove of structure and lower surface are also formed simultaneously with bottom oxidization layer, are also shielded in the groove of the deriving structure more Crystal silicon is filled up completely；
The polysilicon of step 5 returns carve after the completion of formed with the second photoresist layer for covering the grid draw-out area, described second Photoresist layer removes after the autoregistration of the shielding polysilicon of step 6 is returned and carved, the shielding polysilicon of the deriving structure Top is equal with the top surface of corresponding groove；
First photoresist layer described in step 8 at the same time covers the grid draw-out area, makes the bottom oxidization layer of step 9 The top for returning the bottom oxidization layer of the deriving structure after the completion of carving is equal with the top surface of corresponding groove；
The shielding polysilicon of the gate structure is connected with the shielding polysilicon of the deriving structure and is tied by described draw The contact hole formed at the top of the shielding polysilicon of structure is connected to the source electrode.
11. the manufacture method of shield grid groove MOSFET as claimed in claim 8 or 9, it is characterised in that：The semiconductor lining Bottom is silicon substrate, is located in the surface of silicon formed with silicon epitaxy layer, the groove in the silicon epitaxy layer.
12. the manufacture method of shield grid groove MOSFET as claimed in claim 8, it is characterised in that：It is hard described in step 1 Matter mask layer is made of oxide layer.
13. the manufacture method of shield grid groove MOSFET as claimed in claim 8, it is characterised in that：The polysilicon spacer Formed from oxide layer using thermal oxidation technology；The gate oxide is formed using thermal oxidation technology.
14. the manufacture method of shield grid groove MOSFET as claimed in claim 9, it is characterised in that：In the contact hole Opening formed after, it is metal filled before, be additionally included in the contact hole being in contact with the source region bottom carry out the first conduction type Heavily-doped implant forms the step of well region contact zone.
15. the manufacture method of the shield grid groove MOSFET as described in claim 8 or 14, it is characterised in that：Shield gate groove MOSFET is N-type device, and the first conduction type is N-type, and the second conduction type is p-type；Alternatively, shield grid groove MOSFET is P Type device, the first conduction type are p-type, and the second conduction type is N-type.
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CN111785641B (en) * 2020-08-26 2024-02-02 上海华虹宏力半导体制造有限公司 Method for manufacturing semiconductor device
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CN112864236B (en) * 2021-03-09 2023-08-11 上海恒灼科技有限公司 Preparation method of medium-high voltage shielded gate field effect transistor
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