CN106876279A - Shield grid groove power device and its manufacture method - Google Patents

Shield grid groove power device and its manufacture method Download PDF

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Publication number
CN106876279A
CN106876279A CN201710206001.5A CN201710206001A CN106876279A CN 106876279 A CN106876279 A CN 106876279A CN 201710206001 A CN201710206001 A CN 201710206001A CN 106876279 A CN106876279 A CN 106876279A
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dielectric layer
polysilicon
source
gate
type
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颜树范
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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Abstract

The invention discloses a kind of shield grid groove power device, the polysilicon gate of grid structure is formed at deep trench top-side, second dielectric layer is formed between the polysilicon gate of both sides and the second dielectric layer is deep into the bottom of polysilicon gate, source polysilicon is formed at the bottom of second dielectric layer, and isolation has bottom dielectric layer between the side and lower surface of source polysilicon and deep trench.Second dielectric layer realizes the isolation between source polysilicon and polysilicon gate, can reduce the parasitic capacitance between source polysilicon and polysilicon gate.The invention also discloses a kind of manufacture method of shield grid groove power device.The present invention can reduce the gate-source parasitic capacitance of device, improve the input capacitance of device and improve the performance of device.

Description

Shield grid groove power device and its manufacture method
Technical field
The present invention relates to a kind of semiconductor integrated circuit manufacture method, more particularly to a kind of shield grid (Shield Gate Trench, SGT) groove power device；The invention further relates to a kind of manufacture method of shield grid groove power device.
Background technology
As shown in Figure 1A to Fig. 1 N, be existing shield grid groove power device each step of manufacture method in device architecture Schematic diagram；This method is to form the deep trench with shield grid using bottom-to-top method to separate side grid structure, including such as Lower step：
Step one, as shown in Figure 1A, there is provided semi-conductive substrate such as silicon substrate 101；In the surface shape of Semiconductor substrate 101 Into hard mask layers 102, hard mask layers 102 can use oxide layer, or add nitration case using oxide layer.
As shown in Figure 1B, hard mask layers 102 are performed etching using photoetching process afterwards and define grid forming region, Afterwards again with hard mask layers 102 for mask performs etching to form deep trench 103 to Semiconductor substrate 101.
Step 2, as shown in Figure 1 C, oxide layer 104 is formed in the side of deep trench 103 and lower surface.
Step 3, as shown in figure iD, fills source polysilicon 105, the source polysilicon 105 in the deep trench 103 As source polysilicon, source polysilicon 105 is typically connected with source electrode, for forming shield grid.
Step 4, as referring to figure 1E, is carried out back carving to source polysilicon 105, and this time is carved the source electrode outside deep trench 103 is more Crystal silicon 105 is all removed, and the top of source polysilicon 105 in deep trench 103 is equal with Semiconductor substrate 101.
As shown in fig. 1F, the oxide layer 104 of the top area of deep trench 103 is removed.
Step 5, as shown in Figure 1 G, carries out that thermal oxidation technology forms gate oxide 106a simultaneously and inter polysilicon isolation is situated between Matter layer 106b.
As shown in fig. 1H, polysilicon gate 107 is formed, polysilicon gate 107 is deep trench grid.
As shown in Figure 1 I, polysilicon gate 107 is carried out back carving, the polysilicon gate 107 of Hui Kehou is only located at deep trench 103 and pushes up The both sides of source polysilicon 105 in portion；It follows that the polysilicon gate 107 between the two sides of same deep trench 103 is tied in separation Structure, in order to the deep trench grid constituted with the polysilicon gate being filled up completely with the top of deep trench are distinguished, zanjon is formed at by this The deep trench grid with separate structure of groove sidewall are referred to as deep trench separation side grid.
Step 6, as shown in Figure 1 I, forms well region 108, source region 109.
As shown in figure iJ, interlayer film 110 is formed, contact hole marks the contact hole corresponding to 111a to correspond to and is not filled by gold Structure before category.Preferably, after etching forms contact hole 111a, in addition it is also necessary in the contact corresponding to the top of source region 109 Well region contact zone is formed on the bottom of hole 111a.
As shown in figure iK, metal is filled in contact hole 111a afterwards, the contact hole mark 111 after filling metal is marked Show.
As can be seen in 1L, front metal layer 112 is formed.
As depicted in figure iM, formation source electrode and grid respectively are patterned to front metal layer 112 using lithographic etch process Pole, wherein source electrode pass through contact hole and source region 109, well region contact zone 109 and the source polysilicon 105 of bottom are contacted, grid Contacted by contact hole and polysilicon gate 107.
As shown in Fig. 1 N, the back side that Semiconductor substrate 101 is formed in afterwards forms drain region and metal layer on back 113, by carrying on the back The composition drain electrode of face metal level 113.
In existing method, a side of polysilicon gate 107 is isolated by gate oxide 106a and well region 108, well region 108 By the side of polysilicon gate 107 cover surface be used for form raceway groove.Shown in Fig. 1 N, it is many that above-mentioned existing method is formed Crystal silicon grid 107 are only located at the side wall at the top of deep trench, and this vertical devices with sidewall polycrystalline silicon structure can increase work Electric current；Simultaneously source polysilicon 105 be filled in whole deep trench, source polysilicon 105 can form good shielding, with compared with Small bottom capacitor, so as to reduce the input capacitance of source and drain or grid leak, improves frequency characteristic.
But, the existing device architecture as shown in Fig. 1 N, the device has larger gate-source parasitic capacitance (Cgs), Cgs master To be made up of two parts, i.e. Cgs1 corresponding to dotted line circle 114 and Cgs2, Cgs1 and Cgs2 corresponding to dotted line circle 115 be simultaneously in Fig. 1 N Connection forms Cgs.Wherein, Cgs1 be the polysilicon gate 107 and by the gate oxide 106a and connection source electrode well region 108 The gate-source parasitic capacitance formed with source region 109 is Part I gate-source parasitic capacitance；Cgs2 is the polysilicon gate 107 and passes through The gate-source parasitic capacitance that the source polysilicon 105 of the inter polysilicon isolation dielectric layer 106b and connection source electrode is formed is second Divide gate-source parasitic capacitance；Shown in Fig. 1 N, the inter polysilicon isolation dielectric layer 106b and gate oxide 106a is same When formed, former capital has relatively thin thickness；Meanwhile, the overlapping region of the polysilicon gate 107 and the source polysilicon 105 compared with Greatly, the overlapping region of the overlapping region and the polysilicon gate 107 and well region 108 and source region 109 is suitable, substantially described polycrystalline The first side of Si-gate 107 all with the overlapping of well region 108 and source region 109, the polysilicon gate 107 second side all with it is described Source polysilicon 105 it is overlapping；The relatively thin inter polysilicon isolates the thickness of the dielectric layer 106b and gate oxide 106a And larger overlapping area so that Cgs1 and Cgs2 have larger value, and the value of the Cgs of both parallel connections is Cgs1 and Cgs2 Sum, therefore the value of Cgs is also larger, therefore how to reduce the problem that Cgs is the application concern.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of shield grid groove power device, can reduce the grid source of device Parasitic capacitance, from the input capacitance for improving device and improves the performance of device.Therefore, the present invention also provides a kind of shielding gate groove The manufacture method of power device.
In order to solve the above technical problems, the grid structure of the shield grid groove power device of present invention offer includes：
The deep trench in Semiconductor substrate is formed at, bottom dielectric is formed with the lower surface of the deep trench and side Layer.
The side of the deep trench at the top of the bottom dielectric layer is sequentially formed with gate dielectric layer and polysilicon gate；Institute State bottom dielectric layer not to be filled up completely with the deep trench, make bottom dielectric layer described in the deep trench enclose region for bottom Groove and the polysilicon gate enclose region for top channel.
The width of the superposition width less than the bottom dielectric layer of bottom of the gate dielectric layer and the polysilicon gate, institute State the width of the width more than the undercut of top channel.
Source polysilicon is filled with the undercut, the top surface of the source polysilicon is less than the bottom The top surface of groove；Second dielectric layer is completely filled in the undercut and the top at the top of the source polysilicon In portion's groove, the second dielectric layer realizes the isolation between the source polysilicon and the polysilicon gate.
Parasitic capacitance between the source polysilicon and the polysilicon gate is reduced by the second dielectric layer；It is described Posting between the more deep source polysilicon of the depth that second dielectric layer is deep into the undercut and the polysilicon gate Raw electric capacity is smaller, the parasitic capacitance between the more big source polysilicon of width of the second dielectric layer and the polysilicon gate It is smaller.
Further improvement is that the Semiconductor substrate is adulterated for the first conduction type, in the semiconductor substrate surface The well region of the second conduction type is formed with, the well region surface covered by the polysilicon gate side is used to form raceway groove.
The source region of the first conduction type heavy doping is formed with the well region surface.
Be also formed with interlayer film, contact hole and front metal layer in the front of the Semiconductor substrate, source electrode and grid by Chemical wet etching is carried out to the front metal layer to be formed, the source electrode passes through contact hole and the source region and the source electrode polycrystalline Silicon is contacted, and the grid is contacted by contact hole and the polysilicon gate.
Drain region be formed from it is thinning after the Semiconductor substrate back side the first conduction type heavily doped region composition, in institute The back side for stating drain region forms metal layer on back as drain electrode.
Further improvement is that the bottom dielectric layer is oxide layer, and the second dielectric layer is oxide layer, and the grid are situated between Matter layer is oxide layer.
Further improvement is that the second dielectric layer is made up of the interlayer film.
Further improvement is that it is heavily doped to be formed with the second conduction type in the bottom of the contact hole being in contact with the source region Miscellaneous well region contact zone.
Further improvement is that shield grid groove power device is N-type device, and the first conduction type is N-type, and second is conductive Type is p-type, and the Semiconductor substrate is n-type doping；Or, shield grid groove power device is P-type device, the first conductive-type Type is p-type, and the second conduction type is N-type, and the Semiconductor substrate is adulterated for p-type.
Further improvement is that the Semiconductor substrate is silicon substrate.
In order to solve the above technical problems, the grid structure of the manufacture method of the shield grid groove power device that the present invention is provided Formed using following steps：
Step one, offer semi-conductive substrate, deep trench is formed using lithographic etch process in the Semiconductor substrate.
Step 2, form bottom dielectric layer in the lower surface of the deep trench and side；The bottom dielectric layer will not The deep trench is filled up completely with.
Step 3, carry out polycrystalline silicon deposit and form the first polysilicon layer that the zanjon of the bottom dielectric layer will be formed with Groove is filled up completely with.
Step 4, carry out polysilicon return carve, by return carve after first polysilicon layer constitute source polysilicon；The source Pole polysilicon is located at the bottom of the deep trench and is isolated by the bottom dielectric layer and the zanjon rooved face.
Step 5, first covered using depositing and return to be formed in the deep trench of the carving technology at the top of the source polysilicon Mold layer；Top surface of the top surface of first mask layer less than the deep trench.
Step 6, with first mask layer as mask to the bottom dielectric layer carry out back carve, the bottom of Hui Kehou Portion's dielectric layer be located at the deep trench bottom, and the source polysilicon top surface less than the bottom dielectric layer top Portion surface；Afterwards, first mask layer is removed.
Step 7, the side of the deep trench at the top of the bottom dielectric layer sequentially form gate dielectric layer and polysilicon Grid.
Bottom dielectric layer described in the deep trench is made to enclose region for undercut and the polysilicon gate Suo Wei areas Domain is top channel；The width of the superposition width less than the bottom dielectric layer of bottom of the gate dielectric layer and the polysilicon gate Degree, the width of the width more than the undercut of the top channel.
Step 8, second dielectric layer is formed by the undercut at the top of the source polysilicon and the top ditch Groove is filled up completely with, and the second dielectric layer realizes the isolation between the source polysilicon and the polysilicon gate.
Parasitic capacitance between the source polysilicon and the polysilicon gate is reduced by the second dielectric layer；It is described Posting between the more deep source polysilicon of the depth that second dielectric layer is deep into the undercut and the polysilicon gate Raw electric capacity is smaller, the parasitic capacitance between the more big source polysilicon of width of the second dielectric layer and the polysilicon gate It is smaller.
Further improvement is that polysilicon gate described in step 7 adds crystal silicon and returns carving technology shape using polycrystalline silicon deposit Into.
Further improvement is that the Semiconductor substrate is adulterated for the first conduction type, after grid structure is formed, is also wrapped Include following steps：
Step 9, carry out the well region that ion implanting forms the second conduction type in the Semiconductor substrate；Carry out first The source of conduction type heavy doping is infused in the well region surface and forms source region；Thermal annealing is carried out to the well region and the source region to push away Enter technique；The well region surface covered by the polysilicon gate side is used to form raceway groove.
Step 10, interlayer film, contact hole and front metal layer are formed in the Semiconductor substrate front, to front gold Category layer carries out chemical wet etching and forms source electrode and grid, and the source electrode passes through contact hole and the source region and the source polysilicon Contact, the grid is contacted by contact hole and the polysilicon gate.
Step 11, the Semiconductor substrate back side is carried out it is thinning and formed the first conduction type heavy doping drain region, Metal layer on back is formed as drain electrode at the back side in the drain region.
Further improvement be, after the opening of contact hole described in step 10 is formed, it is metal filled before, be additionally included in and institute State the bottom of the contact hole that source region is in contact carry out the second conduction type heavily-doped implant formed well region contact zone the step of.
Further improvement is that the bottom dielectric layer is oxide layer, and the second dielectric layer is oxide layer；The grid are situated between Matter layer is oxide layer, and the gate dielectric layer is formed using thermal oxidation technology.
Further improvement is that the second dielectric layer is made up of the interlayer film, and now, step 8 is incorporated into step 10 The interlayer film formation process in, step 7 directly carries out step 9 after completing, in the interlayer film of step 10 It is by the interlayer film that the undercut and the top channel at the top of the source polysilicon is complete in formation process Full packing simultaneously constitutes the second dielectric layer.
Further improvement is that shield grid groove power device is N-type device, and the first conduction type is N-type, and second is conductive Type is p-type, and the Semiconductor substrate is n-type doping；Or, shield grid groove power device is P-type device, the first conductive-type Type is p-type, and the second conduction type is N-type, and the Semiconductor substrate is adulterated for p-type.
Further improvement is that the Semiconductor substrate is silicon substrate.
Shield grid groove power device of the present invention is specifically designed to grid structure, and polysilicon gate uses separation side grid knot The deep trench of structure, i.e., one includes two polysilicon gate knots that are side and being mutually isolated out at the top for being formed at deep trench Structure, source polysilicon is then only formed at the bottom of deep trench, and source polysilicon is not filled in many between two sides of deep trench Between crystal silicon grid, but second dielectric layer is filled between the polysilicon gate of the side of deep trench, and second dielectric layer be deep into it is many In the undercut that i.e. present invention is defined in the bottom section of crystal silicon grid, so thicker second dielectric layer can be good at realizing The structure that isolation and second dielectric layer between polysilicon gate and source polysilicon are deep into undercut can also eliminate polycrystalline Side between Si-gate and source polysilicon overlaps, and can so greatly reduce the parasitism between source polysilicon and polysilicon gate Electric capacity, the parasitic capacitance is corresponding with Cgs2 corresponding to the dotted line circle 115 of Fig. 1 N of the prior art, so the present invention can subtract Few Cgs2；And the present invention can be adjusted by adjusting the width of depth and second dielectric layer that second dielectric layer is deep into undercut The size of Cgs2 is saved, second dielectric layer is deep between the more deep source polysilicon of the depth in undercut and polysilicon gate Parasitic capacitance it is smaller, the parasitic capacitance between the more big source polysilicon of width and polysilicon gate of second dielectric layer is more It is small.From the foregoing, it will be observed that the present invention can reduce the gate-source parasitic capacitance of device, from improving the input capacitance of device and improve the property of device Energy.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Figure 1A-Fig. 1 N are the device architecture schematic diagrames in each step of manufacture method of existing shield grid groove power device；
Fig. 2 is embodiment of the present invention shield grid trench power device structure schematic diagram；
Fig. 3 A- Fig. 3 J are the device architecture schematic diagrames in each step of present invention method.
Specific embodiment
As shown in Fig. 2 being embodiment of the present invention shield grid trench power device structure schematic diagram, embodiment of the present invention shielding The grid structure of gate groove power device includes：
The deep trench 301 in Semiconductor substrate such as silicon substrate 1 is formed at, lower surface and side in the deep trench 301 Face is formed with bottom dielectric layer 2.
Gate dielectric layer (unused mark is sequentially formed with the side of the deep trench 301 at the top of the bottom dielectric layer 2 Mark) and polysilicon gate 4；Be not filled up completely with for the deep trench 301 by the bottom dielectric layer 2, makes institute in the deep trench 301 State bottom dielectric layer 2 to enclose region by undercut 302 and the polysilicon gate 4 enclose region is top channel 303.
The width of the superposition width less than the bottom dielectric layer 2 of bottom of the gate dielectric layer and the polysilicon gate 4, Width of the width of the top channel 303 more than the undercut 302.
Source polysilicon 3 is filled with the undercut 302, the top surface of the source polysilicon 3 is less than institute State the top surface of undercut 302；Second dielectric layer 5 is completely filled in the bottom ditch at the top of the source polysilicon 3 In groove 302 and the top channel 303, the second dielectric layer 5 realizes the source polysilicon 3 and the polysilicon gate Isolation between 4.
Parasitic capacitance between the source polysilicon 3 and the polysilicon gate 4 is reduced by the second dielectric layer 5； The second dielectric layer 5 is deep into the more deep source polysilicon 3 of depth and the polysilicon gate in the undercut 302 Parasitic capacitance between 4 is smaller, the more big source polysilicon 3 of width and the polysilicon gate 4 of the second dielectric layer 5 it Between parasitic capacitance it is smaller.Compare Fig. 2 and corresponding Fig. 1 N of prior art to understand, the polysilicon gate 4 of the embodiment of the present invention It is separated between and the source polysilicon 3 between and isolates the thicker second mediums of dielectric layer 106b than the inter polysilicon in Fig. 1 N Layer 5, and is deep into the undercut 302 by by the second dielectric layer 5, so described polysilicon gate 4 and the source Will not directly be overlapped between the side of pole polysilicon 3, so the Cgs2 of the embodiment of the present invention is the source polysilicon 3 and described Parasitic capacitance between polysilicon gate 4 can be smaller.
The Semiconductor substrate 1 is adulterated for the first conduction type, and it is conductive to be formed with second on the surface of the Semiconductor substrate 1 The well region 6 of type, the surface of the well region 6 covered by the side of the polysilicon gate 4 is used to form raceway groove.
The source region 7 of the first conduction type heavy doping is formed with the surface of the well region 6.
Interlayer film 5, contact hole 8 and front metal layer 9, source electrode and grid are also formed with the front of the Semiconductor substrate 1 Pole is formed by carrying out chemical wet etching to the front metal layer 9, and the source electrode is by contact hole 8 and the source region 7 and described Source polysilicon 3 is contacted, and the grid is contacted by contact hole 8 and the polysilicon gate 4.
Drain region be formed from it is thinning after the back side of the Semiconductor substrate 1 the first conduction type heavily doped region composition, The back side in the drain region forms metal layer on back 10 as drain electrode.
The embodiment of the present invention which kind of, the bottom dielectric layer 2 be oxide layer, the second dielectric layer 5 be oxide layer, it is described Gate dielectric layer is oxide layer.And the second dielectric layer 5 is made up of the interlayer film 5, the table of mark 5 is both used in fig. 2 Show.
The well region contact of the second conduction type heavy doping is formed with the bottom of the contact hole 8 being in contact with the source region 7 Area 11.
In the embodiment of the present invention, shield grid groove power device is N-type device, and the first conduction type is N-type, and second is conductive Type is p-type, and the Semiconductor substrate 1 is n-type doping.Also can be in other embodiments：Shield grid groove power device is P Type device, the first conduction type is p-type, and the second conduction type is N-type, and the Semiconductor substrate 1 is adulterated for p-type.
Because the embodiment of the present invention can improve Cgs2, and Cgs1 can keep identical with prior art, this sample hair Bright embodiment device can reduce the total gate-source parasitic capacitance i.e. Cgs formed by Cgs1 and Cgs2 parallel connections.
It is the device architecture schematic diagram in each step of present invention method as shown in Fig. 3 A to Fig. 3 J, the present invention is real A grid structure for the manufacture method of shield grid groove power device is applied to be formed using following steps：
Step one, as shown in Figure 3A, there is provided semi-conductive substrate 1, using lithographic etch process in the Semiconductor substrate 1 Middle formation deep trench 301.
Preferably, the Semiconductor substrate 1 is silicon substrate.Hard mask layers (HM) are used when forming the deep trench 301 401, namely the hard mask layers 401 first were formed on the surface of the Semiconductor substrate 1 before photoetching process, photoetching afterwards The forming region of the deep trench 301 is defined, the hard mask layers is sequentially etched afterwards and the Semiconductor substrate 1 is formed The deep trench 301；The hard mask layers 401 are removed afterwards.
Step 2, as shown in Figure 3 B, bottom dielectric layer 2 is formed in the lower surface of the deep trench 301 and side；It is described Be not filled up completely with for the deep trench 301 by bottom dielectric layer 2.
Preferably, the bottom dielectric layer 2 is oxide layer.
Step 3, as shown in Figure 3 C, carries out polycrystalline silicon deposit and forms the first polysilicon layer 3 that the bottom dielectric will be formed with The deep trench 301 of layer 2 is filled up completely with.
Step 4, as shown in Figure 3 D, carries out polysilicon and returns to carve, and source electrode is constituted by returning first polysilicon layer 3 after carving Polysilicon 3；The source polysilicon 3 is located at the bottom of the deep trench 301 and by the bottom dielectric layer 2 and the zanjon The surface of groove 301 isolates.
Step 5, as shown in FIGURE 3 E, using depositing and return the deep trench of the carving technology at the top of the source polysilicon 3 The first mask layer 402 is formed in 301；Top table of the top surface of first mask layer 402 less than the deep trench 301 Face.Preferably, first mask layer 401 is coated with and complete directly using photoresist such as positive photoresist composition by photoresist The structure of first mask layer 401 can be formed after face exposure plus development.
Step 6, as illustrated in Figure 3 F, is that mask carries out back quarter to the bottom dielectric layer 2 with first mask layer 402, The bottom dielectric layer 2 returned after carving is located at the bottom of the deep trench 301, and the top surface of the source polysilicon 3 is low In the top surface of the bottom dielectric layer 2；Afterwards, first mask layer 402 is removed.
Step 7, sequentially form gate dielectric layer and many in the side of the deep trench 301 at the top of the bottom dielectric layer 2 Crystal silicon grid 4.The polysilicon gate 4 is added crystal silicon time carving technology and is formed using polycrystalline silicon deposit, first, as shown in Figure 3 G, carries out Polycrystalline silicon deposit forms the polysilicon layer 4 of thickness needed for the polysilicon gate 4；Afterwards, as shown in figure 3h, returning for polysilicon is carried out Carve, Hui Keneng is automatically by the polysilicon layer 4 outside the polysilicon layer 4 and the deep trench 301 at the top of the source polysilicon 3 Removal, the polysilicon gate 4 is constituted by remaining in the polysilicon layer 4 of top-side of the deep trench 301.
Preferably, the gate dielectric layer is oxide layer, and the gate dielectric layer is formed using thermal oxidation technology.
Bottom dielectric layer 2 described in the deep trench 301 is made to enclose region for undercut 302 and the polysilicon gate 4 enclose region for top channel 303；The bottom of the superposition width less than bottom of the gate dielectric layer and the polysilicon gate 4 The width of portion's dielectric layer 2, the width of the width more than the undercut 302 of the top channel 303.
Step 8, as shown in figure 3j, forms second dielectric layer 5 by the undercut at the top of the source polysilicon 3 302 and the top channel 303 be filled up completely with, the second dielectric layer 5 realizes the source polysilicon 3 and the polycrystalline Isolation between Si-gate 4；
Parasitic capacitance between the source polysilicon 3 and the polysilicon gate 4 is reduced by the second dielectric layer 5； The second dielectric layer 5 is deep into the more deep source polysilicon 3 of depth and the polysilicon gate in the undercut 302 Parasitic capacitance between 4 is smaller, the more big source polysilicon 3 of width and the polysilicon gate 4 of the second dielectric layer 5 it Between parasitic capacitance it is smaller.
In present invention method, the Semiconductor substrate 1 is adulterated for the first conduction type, and grid structure forms it Afterwards, also comprise the following steps：
Step 9, as shown in fig. 31, carries out the trap that ion implanting forms the second conduction type in the Semiconductor substrate 1 Area 6；The source for carrying out the first conduction type heavy doping is infused in the surface of the well region 6 formation source region 7；To the well region 6 and described Source region 7 carries out thermal annealing propulsion technique；The surface of the well region 6 covered by the side of the polysilicon gate 4 is used to form raceway groove.
Step 10, as shown in figure 3j, interlayer film 5 is formed in the front of the Semiconductor substrate 1.Present invention method In, the second dielectric layer 5 is made up of the interlayer film 5, and now, step 8 is incorporated into the shape of the interlayer film 5 of step 10 Into in technique, step 7 directly carries out step 9 after completing, and institute is passed through in the formation process of the interlayer film 5 of step 10 Interlayer film 5 is stated to be filled up completely with simultaneously the undercut 302 and the top channel 303 at the top of the source polysilicon 3 Constitute the second dielectric layer 5.That is, above-mentioned steps eight are no longer individually carried out, but form same during interlayer film 5 in step 10 When formed.
After the interlayer film 5 is formed, contact hole 8 and front metal layer 9 are formed, light is carried out to the front metal layer 9 Carve etching and form source electrode and grid, the source electrode is contacted by contact hole 8 and the source region 7 and the source polysilicon 3, institute Grid is stated to be contacted by contact hole 8 and the polysilicon gate 4.
The usual interlayer film 5 is oxide layer.
Preferably, after the opening of the contact hole 8 is formed, it is metal filled before, be additionally included in and be in contact with the source region 7 The step of bottom of contact hole 8 carries out the second conduction type heavily-doped implant formation well region contact zone 11.
Step 11, the back side of the Semiconductor substrate 1 is carried out it is thinning and formed the first conduction type heavy doping drain region, Metal layer on back 10 is formed as drain electrode at the back side in the drain region.
The shield grid groove power device that present invention method is formed is N-type device, and the first conduction type is N-type, Second conduction type is p-type, and the Semiconductor substrate 1 is n-type doping.Also can be in other embodiments：Shielding gate groove work( Rate device is P-type device, and the first conduction type is p-type, and the second conduction type is N-type, and the Semiconductor substrate 1 is adulterated for p-type.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should It is considered as protection scope of the present invention.

Claims (15)

1. a kind of shield grid groove power device, it is characterised in that grid structure includes：
The deep trench in Semiconductor substrate is formed at, bottom dielectric layer is formed with the lower surface of the deep trench and side；
The side of the deep trench at the top of the bottom dielectric layer is sequentially formed with gate dielectric layer and polysilicon gate；The bottom Be not filled up completely with for the deep trench by portion's dielectric layer, makes bottom dielectric layer described in the deep trench enclose region for undercut And the polysilicon gate encloses region for top channel；
The width of the superposition width less than the bottom dielectric layer of bottom of the gate dielectric layer and the polysilicon gate, the top Width of the width of portion's groove more than the undercut；
Source polysilicon is filled with the undercut, the top surface of the source polysilicon is less than the undercut Top surface；Second dielectric layer is completely filled in the undercut and the top ditch at the top of the source polysilicon In groove, the second dielectric layer realizes the isolation between the source polysilicon and the polysilicon gate；
Parasitic capacitance between the source polysilicon and the polysilicon gate is reduced by the second dielectric layer；Described second Dielectric layer is deep into the parasitism electricity between the more deep source polysilicon of the depth in the undercut and the polysilicon gate Appearance is smaller, and the parasitic capacitance between the more big source polysilicon of width of the second dielectric layer and the polysilicon gate is more It is small.
2. shield grid groove power device as claimed in claim 1, it is characterised in that：The Semiconductor substrate is first conductive Type is adulterated, and the well region of the second conduction type is formed with the semiconductor substrate surface, by polysilicon gate side covering The well region surface be used for form raceway groove；
The source region of the first conduction type heavy doping is formed with the well region surface；
Interlayer film, contact hole and front metal layer are also formed with the front of the Semiconductor substrate, source electrode and grid are by institute State front metal layer and carry out chemical wet etching and formed, the source electrode is connect by contact hole and the source region and the source polysilicon Touch, the grid is contacted by contact hole and the polysilicon gate；
Drain region be formed from it is thinning after the Semiconductor substrate back side the first conduction type heavily doped region composition, in the leakage The back side in area forms metal layer on back as drain electrode.
3. shield grid groove power device as claimed in claim 2, it is characterised in that：The bottom dielectric layer is oxide layer, The second dielectric layer is oxide layer, and the gate dielectric layer is oxide layer.
4. shield grid groove power device as claimed in claim 3, it is characterised in that：The second dielectric layer is by the interlayer Film is constituted.
5. shield grid groove power device as claimed in claim 2, it is characterised in that：In the contact being in contact with the source region The bottom in hole is formed with the well region contact zone of the second conduction type heavy doping.
6. the manufacture method of shield grid groove power device as claimed in claim 2, it is characterised in that：Shield grid groove power Device is N-type device, and the first conduction type is N-type, and the second conduction type is p-type, and the Semiconductor substrate is n-type doping；Or Person, shield grid groove power device is P-type device, and the first conduction type is p-type, and the second conduction type is N-type, the semiconductor Substrate adulterates for p-type.
7. the shield grid groove power device as described in any claim in claim 1 to 6, it is characterised in that：Described half Conductor substrate is silicon substrate.
8. a kind of manufacture method of shield grid groove power device, it is characterised in that grid structure is formed using following steps：
Step one, offer semi-conductive substrate, deep trench is formed using lithographic etch process in the Semiconductor substrate；
Step 2, form bottom dielectric layer in the lower surface of the deep trench and side；The bottom dielectric layer will not be described Deep trench is filled up completely with；
Step 3, carry out polycrystalline silicon deposit formed the first polysilicon layer will be formed with the bottom dielectric layer the deep trench it is complete Full packing；
Step 4, carry out polysilicon return carve, by return carve after first polysilicon layer constitute source polysilicon；The source electrode is more Crystal silicon is located at the bottom of the deep trench and is isolated by the bottom dielectric layer and the zanjon rooved face；
Step 5, using deposit and return the deep trench of the carving technology at the top of the source polysilicon in form the first mask Layer；Top surface of the top surface of first mask layer less than the deep trench；
Step 6, the bottom dielectric layer is carried out back as mask with first mask layer to carve, the bottom of Hui Kehou is situated between Matter layer be located at the deep trench bottom, and the source polysilicon top surface less than the bottom dielectric layer top table Face；Afterwards, first mask layer is removed；
Step 7, the side of the deep trench at the top of the bottom dielectric layer sequentially form gate dielectric layer and polysilicon gate；
Make bottom dielectric layer described in the deep trench enclose region being by undercut and the polysilicon gate enclose region Top channel；The width of the superposition width less than the bottom dielectric layer of bottom of the gate dielectric layer and the polysilicon gate, Width of the width of the top channel more than the undercut；
Step 8, formation second dielectric layer are complete by the undercut and the top channel at the top of the source polysilicon Full packing, the second dielectric layer realizes the isolation between the source polysilicon and the polysilicon gate；
Parasitic capacitance between the source polysilicon and the polysilicon gate is reduced by the second dielectric layer；Described second Dielectric layer is deep into the parasitism electricity between the more deep source polysilicon of the depth in the undercut and the polysilicon gate Appearance is smaller, and the parasitic capacitance between the more big source polysilicon of width of the second dielectric layer and the polysilicon gate is more It is small.
9. the manufacture method of shield grid groove power device as claimed in claim 8, it is characterised in that：It is many described in step 7 Crystal silicon grid are added crystal silicon time carving technology and are formed using polycrystalline silicon deposit.
10. the manufacture method of shield grid groove power device as claimed in claim 8, it is characterised in that：The semiconductor lining Bottom is adulterated for the first conduction type, after grid structure is formed, is also comprised the following steps：
Step 9, carry out the well region that ion implanting forms the second conduction type in the Semiconductor substrate；Carry out first conductive The source of type heavy doping is infused in the well region surface and forms source region；Thermal annealing propulsion work is carried out to the well region and the source region Skill；The well region surface covered by the polysilicon gate side is used to form raceway groove；
Step 10, interlayer film, contact hole and front metal layer are formed in the Semiconductor substrate front, to the front metal layer Carry out chemical wet etching and form source electrode and grid, the source electrode is connect by contact hole and the source region and the source polysilicon Touch, the grid is contacted by contact hole and the polysilicon gate；
Step 11, the Semiconductor substrate back side is carried out it is thinning and formed the first conduction type heavy doping drain region, in institute The back side for stating drain region forms metal layer on back as drain electrode.
The manufacture method of 11. shield grid groove power devices as claimed in claim 10, it is characterised in that：Described in step 10 After the opening of contact hole is formed, it is metal filled before, the bottom for being additionally included in the contact hole being in contact with the source region carries out second The step of conduction type heavily-doped implant forms well region contact zone.
The manufacture method of 12. shield grid groove power devices as claimed in claim 10, it is characterised in that：The bottom dielectric Layer is oxide layer, and the second dielectric layer is oxide layer；The gate dielectric layer is oxide layer, and the gate dielectric layer uses thermal oxide Technique is formed.
The manufacture method of 13. shield grid groove power devices as claimed in claim 10, it is characterised in that：The second medium Layer is made up of the interlayer film, and now, step 8 is incorporated into the formation process of the interlayer film of step 10, and step 7 is completed Step 9 is directly carried out afterwards, it is by the interlayer film that the source electrode is more in the formation process of the interlayer film of step 10 The undercut and the top channel at the top of crystal silicon are filled up completely with and constitute the second dielectric layer.
The manufacture method of 14. shield grid groove power devices as claimed in claim 10, it is characterised in that：Shielding gate groove work( Rate device is N-type device, and the first conduction type is N-type, and the second conduction type is p-type, and the Semiconductor substrate is n-type doping； Or, shield grid groove power device is P-type device, and the first conduction type is p-type, and the second conduction type is N-type, described partly to lead Body substrate adulterates for p-type.
The manufacture method of the shield grid groove power device in 15. such as claim 8 to 14 as described in any claim, its feature It is：The Semiconductor substrate is silicon substrate.
CN201710206001.5A 2017-03-31 2017-03-31 Shield grid groove power device and its manufacture method Pending CN106876279A (en)

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CN107507765A (en) * 2017-08-31 2017-12-22 上海华虹宏力半导体制造有限公司 Shield grid groove power device and its manufacture method
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Application publication date: 20170620