CN103545368A - Trench gate MOSFET - Google Patents
Trench gate MOSFET Download PDFInfo
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- CN103545368A CN103545368A CN201210317182.6A CN201210317182A CN103545368A CN 103545368 A CN103545368 A CN 103545368A CN 201210317182 A CN201210317182 A CN 201210317182A CN 103545368 A CN103545368 A CN 103545368A
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- 229910044991 metal oxide Inorganic materials 0.000 claims description 58
- 150000004706 metal oxides Chemical class 0.000 claims description 58
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 26
- 238000005229 chemical vapour deposition Methods 0.000 description 22
- 238000004519 manufacturing process Methods 0.000 description 14
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- 239000010703 silicon Substances 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
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- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 3
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- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
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- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
The invention provides a trench gate MOSFET. The epitaxial layer is disposed on the substrate. The body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. The first conductor layer is disposed in the first trench. The first insulating layer is disposed between the first conductive layer and the epitaxial layer. The second conductor layer is disposed on the sidewall of the second trench. The second insulating layer is disposed between the second conductive layer and the body layer and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and fills the second trench. The two doped regions are respectively arranged in the body layer at two sides of the second groove.
Description
Technical field
The invention relates to a kind of semiconductor element, and particularly relevant for a kind of channel grid metal-oxide half field effect transistor.
Background technology
Groove type gold oxygen semiconductcor field effect transistor is widely used on power switch (power switch) element, for example, be power supply, rectifier or low voltage motor controller etc.Generally speaking, groove type gold oxygen semiconductcor field effect transistor is taked the design of vertical stratification more, with lift elements density.It utilizes the back side of wafer as drain electrode, and makes a plurality of transistorized source electrodes and grid in the front of wafer.Because a plurality of transistorized drain electrodes are connected in parallel, so its size of current of bearing can be quite large.
The work loss of groove type gold oxygen semiconductcor field effect transistor can be divided into switch cost (switching loss) and conducting loss (conducting loss) two large classes, wherein because of input capacitance C
issthe switch cost causing can increase because of the raising of frequency of operation.Input capacitance C
isscomprise the capacitor C of grid to source electrode
gsand the capacitor C of grid to drain electrode
gd.
A kind of practice of prior art is in groove, form grid and cover grid (shielded gate).Cover grid and be positioned at grid below, insulating barrier by grid with cover grid and separate, and cover grid and be connected to source electrode.Although this kind of practice can reduce the capacitor C of grid to drain electrode
gd, but can increase but then the capacitor C of grid to source electrode
gs, thereby cannot effectively reduce switch cost.
Summary of the invention
In view of this, the invention provides a kind of channel grid metal-oxide half field effect transistor, can reduce the capacitor C of grid to drain electrode simultaneously
gdand the capacitor C of grid to source electrode
gs, effectively to reduce switch cost, lift elements usefulness.
The invention provides a kind of channel grid metal-oxide half field effect transistor.The epitaxial layer with the first conductivity type is configured in the substrate with the first conductivity type.The body layer with the second conductivity type is configured in epitaxial layer.In epitaxial layer, there is the first groove, in body layer, there is the second groove, and the first arrangements of grooves is in the second beneath trenches.The first conductor layer is configured in the first groove.The first insulating barrier is configured between the first conductor layer and epitaxial layer.The second conductor layer is configured on the sidewall of the second groove.The second insulating barrier be configured between the second conductor layer and body layer and the second conductor layer and the first conductor layer between.Dielectric layer is configured on epitaxial layer and fills up the second groove.Two doped regions with the first conductivity type are configured in respectively in the body layer of both sides of the second groove.
In one embodiment of this invention, the thickness of above-mentioned the second insulating barrier is less than the thickness of the first insulating barrier.
In one embodiment of this invention, above-mentioned the second insulating barrier covers the top of the first conductor layer.
In one embodiment of this invention, above-mentioned the first conductor layer also extends in the second groove.
In one embodiment of this invention, the material of above-mentioned the first conductor layer comprises doped polycrystalline silicon.
In one embodiment of this invention, the material of above-mentioned the second conductor layer comprises doped polycrystalline silicon.
In one embodiment of this invention, above-mentioned channel grid metal-oxide half field effect transistor also comprises the 3rd conductor layer, and it is configured on dielectric layer, and wherein the 3rd conductor layer is electrically connected by two conductor connectors and body layer.
In one embodiment of this invention, the material of above-mentioned the 3rd conductor layer comprises metal.
In one embodiment of this invention, above-mentioned the first conductivity type is N-type, and the second conductivity type is P type; Or first conductivity type be P type, the second conductivity type is N-type.
The present invention separately provides a kind of channel grid metal-oxide half field effect transistor.The epitaxial layer with the first conductivity type is configured in the substrate of the first conductivity type.The body layer with the second conductivity type is configured in epitaxial layer.In epitaxial layer, there is the first groove, in body layer, there is the second groove, and the first arrangements of grooves is in the second beneath trenches.The first conductor layer is configured in the first groove.The first insulating barrier is configured between the first conductor layer and epitaxial layer.The second insulating barrier is configured in the second groove and covers the first conductor layer.The second conductor layer is configured in the second groove and covers the second insulating barrier.The 3rd insulating barrier is configured between the second conductor layer and body layer.Dielectric layer is configured on epitaxial layer and covers the second conductor layer.Two doped regions with the first conductivity type are configured in respectively in the body layer of both sides of the second groove.
In one embodiment of this invention, the thickness of above-mentioned the 3rd insulating barrier is less than the thickness of the first insulating barrier.
In one embodiment of this invention, the width of above-mentioned the second insulating barrier is greater than the width of the first conductor layer.
In one embodiment of this invention, the material of above-mentioned the first conductor layer comprises doped polycrystalline silicon.
In one embodiment of this invention, the material of above-mentioned the second conductor layer comprises doped polycrystalline silicon.
In one embodiment of this invention, above-mentioned channel grid metal-oxide half field effect transistor also comprises the 3rd conductor layer, and it is configured on dielectric layer, and wherein the 3rd conductor layer is electrically connected by two conductor connectors and body layer.
In one embodiment of this invention, the material of above-mentioned the 3rd conductor layer comprises metal.
In one embodiment of this invention, above-mentioned the first conductivity type is N-type, and the second conductivity type is P type; Or first conductivity type be P type, the second conductivity type is N-type.
Based on above-mentioned, in channel grid metal-oxide-semifield-effect electric crystal transistor of the present invention, will cover gate configuration below grid, can reduce the capacitor C of grid to drain electrode
gdand improve the transistorized puncture voltage of electric crystal.In addition, insulating barrier (or dielectric layer) is configured in and in grid, can reduces grid and cover the coupling effect between grid, thereby reduces the capacitor C of grid to source electrode
gs.In other words, structure of the present invention can reduce the capacitor C of grid to drain electrode simultaneously
gdand the capacitor C of grid to source electrode
gs, effectively to reduce switch cost, lift elements usefulness.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Figure 1A to 1G is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the first embodiment of the present invention;
Fig. 2 A to 2F is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the second embodiment of the present invention;
Fig. 3 A to 3H is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the third embodiment of the present invention;
Fig. 4 A to 4F is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the fourth embodiment of the present invention.
Description of reference numerals:
100,200,300,400: channel grid metal-oxide half field effect transistor;
102,202,302,402: substrate;
104,204,304,404: epitaxial layer;
105,305: cover curtain layer;
107,109,111,207,209,211,307,309,311,407,409,411: groove;
108,108a, 112a, 112b, 114,208,208a, 212,310,310a, 314a, 316,408,408a, 412,414: insulating barrier;
110,110a, 116,128,210a, 214,214a, 228,312,312a, 318,328,410a, 410b, 416,428: conductor layer;
112,314: insulation material layer;
120,220,320,420: body layer;
122,222,322,422: doped region;
124,224,324,424: dielectric layer;
126,215,226,326,426: opening;
127,227,327,427: conductor connector;
210,410: conductor material layer;
308: spacer material layer;
308a: clearance wall.
Embodiment
The first embodiment
Figure 1A to 1G is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the first embodiment of the present invention.
First, please refer to Figure 1A, in the substrate 102 with the first conductivity type, sequentially form epitaxial layer 104 and the cover curtain layer 105 with the first conductivity type.Substrate 102 is for example the heavily doped silicon base of N-type.Epitaxial layer 104 is for example the lightly doped epitaxial layer of N-type, and its formation method comprises that carrying out selectivity builds crystals growth (selective epitaxy growth, SEG) processing procedure.The material of cover curtain layer 105 is for example silicon nitride, and its formation method comprises and carries out chemical vapor deposition process.Then, take cover curtain layer 105 as cover curtain, carry out etch process, to form groove 107 in epitaxial layer 104.Afterwards, remove cover curtain layer 105.
Please refer to Figure 1B, on the surface of epitaxial layer 104 and groove 107, form to compliance insulating barrier 108 and conductor layer 110.The material of insulating barrier 108 is for example silica, and its formation method comprises and carries out thermal oxidation method or chemical vapor deposition process.The material of conductor layer 110 is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.Next, on conductor layer 110, form insulation material layer 112, and insulation material layer 112 fills up groove 107.The material of insulation material layer 112 be for example tetraethoxysilane (tetraethosiloxane,
tEOS) silica, and its formation method comprises and carries out chemical vapor deposition process.
Please refer to Fig. 1 C, carry out etch-back processing procedure, remove SI semi-insulation material layer 112, to form the insulating barrier 112a that fills up groove 107.In one embodiment, etch-back processing procedure exposes the end face of conductor layer 110, and its up time pattern is controlled the thickness of insulating barrier 112a.
Please refer to Fig. 1 D, remove segment conductor layer 110, to form the conductor layer 110a that exposes insulating barrier 112a top and insulating barrier 108 end faces and partial sidewall.In specific words, conductor layer 110a is bowl-type or U-shaped, and it is configured as the bottom around insulating barrier 112a, and between insulating barrier 112a and insulating barrier 108.The method that forms conductor layer 110a is for example etch-back method, and its up time pattern is controlled the apical side height of conductor layer 110a.In one embodiment, conductor layer 110a exposes insulating barrier 108, and it highly need coordinate the degree of depth of body layer (figure do not show that related description is detailed later) or groove 107, take approximately 1/2 height that this example is insulating barrier 112a.
Please refer to Fig. 1 E, remove partial insulative layer 112a and partial insulative layer 108, the top that makes the insulating barrier 112b that stays and insulating barrier 108a expose conductor layer 110a.In specific words, conductor layer 110a protrudes from insulating barrier 112b and insulating barrier 108a, and conductor layer 110a is configured as around insulating barrier 112b, and insulating barrier 108a is configured as around conductor layer 110a.The method that forms insulating barrier 112b and insulating barrier 108a is for example etch-back method, and its up time pattern is controlled the apical side height of insulating barrier 112b and insulating barrier 108a.In one embodiment, insulating barrier 112b and insulating barrier 108a expose the height of the approximately 1/8-1/10 of conductor layer 110a.Yet the present invention is not as limit.In another embodiment, the end face of insulating barrier 112b and insulating barrier 108a also can flush haply with the end face of conductor layer 110a.
Please refer to Fig. 1 F, on the surface of epitaxial layer 104 and groove 107, form insulating barrier 114, and insulating barrier 114 covers conductor layer 110a.The material of insulating barrier 114 is for example silica, and its formation method comprises and carries out thermal oxidation method or chemical vapor deposition process.In one embodiment, the thickness of insulating barrier 114 is less than the thickness of insulating barrier 108a.Yet the present invention is not as limit.In another embodiment, the thickness of insulating barrier 114 also can be equal to or greater than the thickness of insulating barrier 108a.Then, in groove 107, fill up conductor layer 116.The method that forms conductor layer 116 is included in and on epitaxial layer 104, forms conductor material layer (not shown), and conductor material layer fills up groove 107.The material of conductor material layer is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.Then, carry out etch-back processing procedure, remove segment conductor material layer.
Please refer to Fig. 1 G, in the epitaxial layer 104 of groove 107 both sides, form respectively two body layers 120 with the second conductivity type.Body layer 120 is for example P type body layer, and its formation method comprises and carries out ion implantation manufacture process.Then, in the body layer 120 of the both sides of groove 107, form respectively two doped regions 122 with the first conductivity type.Doped region 122 is for example N-type heavily doped region, and its formation method comprises and carries out ion implantation manufacture process.
On conductor layer 116 and doped region 122, form dielectric layer 124.The material of dielectric layer 124 is for example silica, boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), fluorine silex glass (FSG) or unadulterated silex glass (USG), and its formation method comprises and carries out chemical vapor deposition process.Then, form two openings 126 that run through dielectric layer 124 and doped region 122.The method that forms opening comprises carries out micro image etching procedure.Afterwards, form conductor layer 128 on dielectric layer 124, wherein conductor layer 128 is inserted opening 126 to be electrically connected with body layer 120.The conductor layer 128 of inserting opening 126 forms conductor connector 127.In other words, conductor layer 128 is electrically connected by conductor connector 127 and body layer 120.The material of conductor layer 128 can be the metal such as aluminium, and its formation method comprises and carries out chemical vapor deposition process.So far, complete the manufacture of the channel grid metal-oxide half field effect transistor 100 of the first embodiment.
The structure of channel grid metal-oxide half field effect transistor 100 of the present invention is described with reference to Fig. 1 G below.Please refer to Fig. 1 G, channel grid metal-oxide half field effect transistor 100 comprises N-type substrate 102, N-type epitaxial layer 104, P type body layer 120.Epitaxial layer 104 is configured in substrate 102.Body layer 120 is configured in epitaxial layer 104.In addition, have groove 109 in epitaxial layer 104, have groove 111 in body layer 120, groove 109 is configured in groove 111 belows, and groove 109 and groove 111 composition grooves 107.
Channel grid metal-oxide half field effect transistor 100 also comprises insulating barrier 108a, conductor layer 110a, insulating barrier 112b, conductor layer 116 and insulating barrier 114.Insulating barrier 108a is configured in the surface of groove 109, and insulating barrier 112b is configured in groove 109, and conductor layer 110a is configured between insulating barrier 108a and insulating barrier 112b.Conductor layer 116 is configured in groove 111.Insulating barrier 114 is configured between conductor layer 116 and body layer 120 and between conductor layer 116 and conductor layer 110a.In one embodiment, conductor layer 110a also extends in groove 111, and insulating barrier 114 covers the top of conductor layer 110a.
Channel grid metal-oxide half field effect transistor 100 also comprises two N-type doped regions 122, a dielectric layer 124, two conductor connectors 127 and conductor layers 128.Doped region 122 is configured in the body layer 120 of both sides of groove 111.Dielectric layer 124 is configured on conductor layer 116 and doped region 122.Conductor layer 128 is configured on dielectric layer 124, and wherein conductor layer 128 is electrically connected by conductor connector 127 and body layer 120.
In the channel grid metal-oxide half field effect transistor 100 of the first embodiment, substrate 102 is as drain electrode, and doped region 122 is as source electrode, and conductor layer 116 is as grid, and conductor layer 110a is as covering grid, and insulating barrier 114 is as lock oxide layer.Be noted that especially due to the configuration of covering grid (being conductor layer 110a), can reduce the capacitor C of grid to drain electrode
gdand improve transistorized puncture voltage (breakdown voltage).In addition, because insulating barrier 112b is configured in, cover in grid (being conductor layer 110a) to reduce grid (being conductor layer 116) and to cover the coupling effect between grid (being conductor layer 110a), thereby can reduce the capacitor C of grid to source electrode
gs.That is to say, the structure of first embodiment of the invention can reduce the capacitor C of grid to drain electrode
gdand the capacitor C of grid to source electrode
gs, effectively to reduce switch cost, lift elements usefulness.
The second embodiment
Fig. 2 A to 2F is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the second embodiment of the present invention.
First, please refer to Fig. 2 A, in the substrate 202 with the first conductivity type, form the epitaxial layer 204 with the first conductivity type.Substrate 202 is for example N-type silicon base.Epitaxial layer 204 is for example N-type epitaxial layer.Then, in epitaxial layer 204, form groove 207.Form epitaxial layer 204 and refer to the first embodiment with the method for groove 207, do not repeat them here.
Then, on the surface of epitaxial layer 204 and groove 207, form to compliance insulating barrier 208.The material of insulating barrier 208 is for example silica, and its formation method comprises and carries out thermal oxidation method or chemical vapor deposition process.Then, on insulating barrier 208, form conductor material layer 210, and conductor material layer 210 fills up groove 207.The material of conductor material layer 210 is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.
Afterwards, please refer to Fig. 2 B, carry out etch-back processing procedure, remove segment conductor material layer 210, with the bottom at groove 207, form conductor layer 210a.In one embodiment, etch-back processing procedure exposes end face and the partial sidewall of insulating barrier 208, and its up time pattern is controlled the apical side height of conductor layer 210a.In one embodiment, the apical side height of conductor layer 210a need coordinate the degree of depth of body layer, for example approximately 1/2 gash depth.
Next, please refer to Fig. 2 C, remove partial insulative layer 208, to form the insulating barrier 208a that exposes conductor layer 210a top.The method that forms insulating barrier 208a comprises carries out etch-back method, until expose approximately 1/8 to 1/10 the height of conductor layer 210a.In one embodiment, up time pattern is controlled the exposed height out of conductor layer 210a.Yet the present invention is not as limit.In another embodiment, the end face of insulating barrier 208a also can flush haply with the end face of conductor layer 210a.
Then, please refer to Fig. 2 D, on the surface of epitaxial layer 204 and groove 207, form insulating barrier 212 to compliance, and insulating barrier 212 covers conductor layer 210a.The material of insulating barrier 212 is for example silica, and its formation method comprises and carries out thermal oxidation method or chemical vapor deposition process.In one embodiment, the thickness of insulating barrier 212 is less than the thickness of insulating barrier 208a.Yet the present invention is not as limit.In another embodiment, the thickness of insulating barrier 212 also can be equal to or greater than the thickness of insulating barrier 208a.Then, on insulating barrier 212, form to compliance conductor layer 214.The material of conductor layer 214 is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.
Then, please refer to Fig. 2 E, remove segment conductor layer 214, to form conductor layer 214a on the sidewall at insulating barrier 212.In specific words, conductor layer 214a is configured on the sidewall of insulating barrier 212 with the form of clearance wall, and has the opening 215 of the part bottom surface that exposes insulating barrier 212.The method that forms conductor layer 214a comprises carries out anisotropic dry ecthing procedure.
Next, please refer to Fig. 2 F, in the epitaxial layer 204 of groove 207 both sides, form respectively two body layers 220 with the second conductivity type.Body layer 220 is for example P type body layer.Afterwards, in the body layer 220 of the both sides of groove 207, form respectively two doped regions 222 with the first conductivity type.Doped region 222 is for example N-type heavily doped region.Afterwards, on conductor layer 214a and doped region 222, form dielectric layer 224, and dielectric layer 224 is inserted in opening 215.Next, form two openings 226 that run through dielectric layer 224 and doped region 222.Then, form conductor layer 228 on dielectric layer 224, wherein conductor layer 228 is inserted opening 226 to be electrically connected with body layer 220.The conductor layer 228 of inserting opening 226 forms conductor connector 227.In other words, conductor layer 228 is electrically connected by conductor connector 227 and body layer 220.Material and the formation method of body layer 220, doped region 222, conductor connector 227 and conductor layer 228 refer to the first embodiment, do not repeat them here.So far, complete the manufacture of the channel grid metal-oxide half field effect transistor 200 of the second embodiment.
The structure of channel grid metal-oxide half field effect transistor 200 of the present invention is described with reference to Fig. 2 F below.Please refer to Fig. 2 F, channel grid metal-oxide half field effect transistor 200 comprises N-type substrate 202, N-type epitaxial layer 204, P type body layer 220.Epitaxial layer 204 is configured in substrate 202.Body layer 220 is configured in epitaxial layer 204.In addition, have groove 209 in epitaxial layer 204, have groove 211 in body layer 220, groove 209 is configured in groove 211 belows, and groove 209 and groove 211 composition grooves 207.
Channel grid metal-oxide half field effect transistor 200 also comprises insulating barrier 208a, conductor layer 210a, insulating barrier 212 and conductor layer 214a.Conductor layer 210a is configured in groove 209.Insulating barrier 208a is configured between conductor layer 210a and epitaxial layer 204.Conductor layer 214a is configured on the sidewall of groove 211.Insulating barrier 212 is configured between conductor layer 214a and body layer 220 and between conductor layer 214a and conductor layer 210a.In one embodiment, conductor layer 210a also extends in groove 211, and insulating barrier 212 covers the top of conductor layer 210a.
Channel grid metal-oxide half field effect transistor 200 also comprises two N-type doped regions 222, a dielectric layer 224, two conductor connectors 227 and conductor layers 228.Doped region 222 is configured in the body layer 220 of both sides of groove 211.Dielectric layer 224 is configured on insulating barrier 212 and fills up groove 211.That is dielectric layer 224 is configured in the opening 215 of conductor layer 214a.Conductor layer 228 is configured on dielectric layer 224, and wherein conductor layer 228 is electrically connected by conductor connector 227 and body layer 220.
In the channel grid metal-oxide half field effect transistor 200 of the second embodiment, substrate 202 is as drain electrode, and doped region 222 is as source electrode, and conductor layer 214a is as grid, and conductor layer 210a is as covering grid, and insulating barrier 212 is as lock oxide layer.Be noted that especially due to the configuration of covering grid (being conductor layer 210a), can reduce the capacitor C of grid to drain electrode
gdand improve transistorized puncture voltage.In addition, because dielectric layer 224 is configured in grid (being conductor layer 214a) to reduce grid (being conductor layer 214a) and to cover the coupling effect between grid (being conductor layer 210a), thereby can reduce the capacitor C of grid to source electrode
gs.That is to say, the structure of second embodiment of the invention can reduce the capacitor C of grid to drain electrode simultaneously
gdand the capacitor C of grid to source electrode
gs, effectively to reduce switch cost, lift elements usefulness.
The 3rd embodiment
Fig. 3 A to 3H is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the third embodiment of the present invention.
First, please refer to Fig. 3 A, in the substrate 302 with the first conductivity type, sequentially form epitaxial layer 304 and the cover curtain layer 305 with the first conductivity type.Substrate 302 is for example N-type silicon base.Epitaxial layer 304 is for example N-type epitaxial layer.The material of cover curtain layer 305 is for example silica, silicon nitride or silicon oxynitride, and its formation method comprises and carries out chemical vapor deposition process.Then, take cover curtain layer 305 as cover curtain, carry out etch process, to form groove 311 in epitaxial layer 304.Then, on the surface of epitaxial layer 304 and groove 311, form spacer material layer 308.The material of spacer material layer 308 is for example silica, silicon nitride or silicon oxynitride, and its formation method comprises and carries out chemical vapor deposition process.In this embodiment, cover curtain layer 305 is different from the material of spacer material layer 308.
Afterwards, please refer to Fig. 3 B, carry out anisotropic dry ecthing procedure, remove part spacer material layer 308, to form clearance wall 308a on the sidewall at groove 311.In this embodiment, because the etching selectivity of 308 pairs of cover curtain layer 305 of spacer material layer is enough high, therefore above-mentioned anisotropic dry ecthing procedure can be parked on the surface of cover curtain layer 305 in fact.In other words, cover curtain layer 305 can be protected epitaxial layer 304 surfaces, makes epitaxial layer 304 surfaces avoid the destruction of subsequent etch processing procedure.Then, take cover curtain layer 305 and clearance wall 308a as cover curtain, remove part epitaxial layer 304, to form groove 309 below groove 311.The method that forms groove 309 is for example to carry out etch process.Afterwards, remove clearance wall 308a.Owing to forming the method for groove 309, being to take clearance wall 308a as cover curtain, is therefore a kind of self-aligning process (self-aligned process), and wherein the width of groove 309 is less than the width of groove 311.In addition, groove 309 is configured in groove 311 belows, and groove 309 and groove 311 composition grooves 307.
Next, please refer to Fig. 3 C, on the surface of epitaxial layer 304 and groove 307, form to compliance insulating barrier 310.The material of insulating barrier 310 is for example silica, and its formation method comprises and carries out thermal oxidation method or chemical vapor deposition process.Then, on insulating barrier 310, form conductor layer 312.In specific words, be formed on the surface of epitaxial layer 304 and groove 311 to conductor layer 312 compliances, and fill up groove 309.The material of conductor layer 312 is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.Then, on epitaxial layer 304, form insulation material layer 314, and insulation material layer 314 fills up groove 311.The material of insulation material layer 314 is for example silica, and its formation method comprises and carries out chemical vapor deposition process.
Then, please refer to Fig. 3 D, carry out etch-back processing procedure, remove SI semi-insulation material layer 314, to form the insulating barrier 314a that fills up groove 311.In one embodiment, etch-back processing procedure exposes the end face of conductor layer 312, and its up time pattern is controlled the thickness of insulating barrier 314a.In one embodiment, the width of insulating barrier 314a equals the width of conductor layer 312 in groove 309 haply, as shown in Figure 3 D.Yet the present invention is not as limit.In another embodiment, the width of insulating barrier 314a also can be greater than the width of conductor layer 312 in groove 309.
Then, please refer to Fig. 3 E, remove segment conductor layer 312, to form conductor layer 312a in the below of insulating barrier 314a.The method that forms conductor layer 312a comprises take insulating barrier 314a as cover curtain, carries out anisotropic dry ecthing procedure.In addition, because said method is to take insulating barrier 314a as cover curtain, be therefore a kind of self-aligning process, wherein conductor layer 312a be positioned at insulating barrier 314a under.In addition,, because the width of insulating barrier 314a is equal to or greater than the width of conductor layer 312 in groove 309, therefore above-mentioned etch process can not remove the part of conductor layer 312 in groove 309.
Then, please refer to Fig. 3 F, remove insulating barrier 314a and partial insulative layer 310, to form the insulating barrier 310a that exposes conductor layer 312a top.The method that forms insulating barrier 310a is for example etch-back method, and its up time pattern is controlled the apical side height of insulating barrier 310a.In one embodiment, insulating barrier 310a exposes the height of the approximately 1/8-1/10 of conductor layer 312a.In another embodiment, insulating barrier 310a is only positioned on the surface of groove 309.
Then, please refer to Fig. 3 G, on the surface of epitaxial layer 304 and groove 307, form insulating barrier 316 to compliance, and insulating barrier 316 covers conductor layer 312a.The material of insulating barrier 316 is for example silica, and its formation method comprises and carries out thermal oxidation method or chemical vapor deposition process.In one embodiment, the thickness of insulating barrier 316 is less than the thickness of insulating barrier 310a.Yet the present invention is not as limit.In another embodiment, the thickness of insulating barrier 316 also can be equal to or greater than the thickness of insulating barrier 310a.Then, in groove 311, fill up conductor layer 318.The method that forms conductor layer 318 is included in and on epitaxial layer 304, forms conductor material layer (not shown), and conductor material layer fills up groove 311.The material of conductor material layer is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.Then, carry out etch-back processing procedure, remove segment conductor material layer.
Next, please refer to Fig. 3 H, in the epitaxial layer 304 of groove 311 both sides, form respectively two body layers 320 with the second conductivity type.Body layer 320 is for example P type body layer.Afterwards, in the body layer 320 of the both sides of groove 311, form respectively two doped regions 322 with the first conductivity type.Doped region 322 is for example N-type heavily doped region.Afterwards, on conductor layer 318 and doped region 322, form dielectric layer 324.Next, form two openings 326 that run through dielectric layer 324 and doped region 322.Then, form conductor layer 328 on dielectric layer 324, wherein conductor layer 328 is inserted opening 326 to be electrically connected with body layer 320.The conductor layer 328 of inserting opening 326 forms conductor connector 327.In other words, conductor layer 328 is electrically connected by conductor connector 327 and body layer 320.Material and the formation method of body layer 320, doped region 322, conductor connector 327 and conductor layer 328 refer to the first embodiment, do not repeat them here.So far, complete the manufacture of the channel grid metal-oxide half field effect transistor 300 of the 3rd embodiment.
The structure of channel grid metal-oxide half field effect transistor 300 of the present invention is described with reference to Fig. 3 H below.Please refer to Fig. 3 H, channel grid metal-oxide half field effect transistor 300 comprises N-type substrate 302, N-type epitaxial layer 304, P type body layer 320.Epitaxial layer 304 is configured in substrate 302.Body layer 320 is configured in epitaxial layer 304.In addition, have groove 309 in epitaxial layer 304, have groove 311 in body layer 320, groove 309 is configured in groove 311 belows, and groove 309 and groove 311 composition grooves 307.
Channel grid metal-oxide half field effect transistor 300 also comprises insulating barrier 310a, conductor layer 312a, insulating barrier 316 and conductor layer 318.Insulating barrier 310a is configured on the surface of groove 309.Conductor layer 312a fills up groove 309.Conductor layer 318 is configured in groove 311.Insulating barrier 316 is configured between conductor layer 318 and body layer 320 and between conductor layer 318 and conductor layer 312a.In one embodiment, conductor layer 312a also extends in groove 311, and insulating barrier 316 covers the top of conductor layer 312a.
Channel grid metal-oxide half field effect transistor 300 also comprises two N-type doped regions 322, a dielectric layer 324, two conductor connectors 327 and conductor layers 328.Doped region 322 is configured in the body layer 320 of both sides of groove 311.Dielectric layer 324 is configured on conductor layer 318 and doped region 322.Conductor layer 328 is configured on dielectric layer 324, and wherein conductor layer 328 is electrically connected by conductor connector 327 and body layer 320.
In the channel grid metal-oxide half field effect transistor 300 of the 3rd embodiment, substrate 302 is as drain electrode, and doped region 322 is as source electrode, and conductor layer 318 is as grid, and conductor layer 312a is as covering grid, and insulating barrier 316 is as lock oxide layer.Be noted that especially due to the configuration of covering grid (being conductor layer 312a), can reduce the capacitor C of grid to drain electrode
gdand improve transistorized puncture voltage.In addition, because the width of groove 309 is less than the width of groove 311, and the thickness of insulating barrier 310a is greater than the thickness of insulating barrier 316, and the width that therefore covers grid (being conductor layer 312a) is less than the width of grid (being conductor layer 318).So, can reduce grid (being conductor layer 318) and cover the coupling effect between grid (being conductor layer 312a), thereby can reduce the capacitor C of grid to source electrode
gs.That is to say, structure of the present invention can reduce the capacitor C of grid to drain electrode simultaneously
gdand the capacitor C of grid to source electrode
gs, effectively to reduce switch cost, lift elements usefulness.
The 4th embodiment
Fig. 4 A to 4F is the generalized section of the manufacture method of the shown a kind of channel grid metal-oxide half field effect transistor of the fourth embodiment of the present invention.
First, please refer to Fig. 4 A, in the substrate 402 with the first conductivity type, form the epitaxial layer 404 with the first conductivity type.Substrate 402 is for example N-type silicon base.Epitaxial layer 404 is for example N-type epitaxial layer.Then, in epitaxial layer 404, form groove 407.Form epitaxial layer 404 and refer to the first embodiment with the method for groove 407, do not repeat them here.
Then, on the surface of epitaxial layer 404 and groove 407, form to compliance insulating barrier 408.The material of insulating barrier 408 is for example silica, and its formation method comprises and carries out thermal oxidation method or chemical vapor deposition process.Then, on epitaxial layer 404, form conductor material layer 410, and conductor material layer 410 fills up groove 407.The material of conductor material layer 410 is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.
Afterwards, please refer to Fig. 4 B, carry out etch-back processing procedure, remove segment conductor material layer 410, to form conductor layer 410a in groove 407.In one embodiment, etch-back processing procedure exposes end face and the partial sidewall of insulating barrier 408, and its up time pattern is controlled the thickness of conductor layer 410a.
Next, please refer to Fig. 4 C, remove partial insulative layer 408, to form the insulating barrier 408a that exposes conductor layer 410a top.The method that forms insulating barrier 408a comprises carries out etch-back method, until expose approximately 1/3 to 2/5 the height of conductor layer 410a.In one embodiment, up time pattern is controlled the exposed height out of conductor layer 410a.In one embodiment, the apical side height of insulating barrier 408a need coordinate the degree of depth of body layer, take the gash depth that this example is approximately 1/2.
Next, please refer to Fig. 4 D, carry out oxidation process, by being insulated layer conductor layer 410a top of 408a covering, be not oxidized to insulating barrier 412, and leave conductor layer 410b, and this oxidation process forms insulating barrier 414 simultaneously on the surface of epitaxial layer 404 and the sidewall of groove 407.The material of insulating barrier 412 and insulating barrier 414 is for example silica.In one embodiment, above-mentioned oxidation process is all oxidized conductor layer 410a top, as shown in Figure 4 D.(not shown) in another embodiment, above-mentioned oxidation process only carries out partial oxidation by conductor layer 410a top.In addition, in one embodiment, the thickness of insulating barrier 414 is less than the thickness of insulating barrier 408a.Yet the present invention is not as limit.In another embodiment, the thickness of insulating barrier 414 also can be equal to or greater than the thickness of insulating barrier 408a.
Then, please refer to Fig. 4 E, in groove 407, form conductor layer 416.The method that forms conductor layer 416 is included in and on epitaxial layer 404, forms conductor material layer (not shown), and conductor material layer covers insulating barrier 412, insulating barrier 414 and fills up groove 407.The material of conductor material layer is for example doped polycrystalline silicon, and its formation method comprises and carries out chemical vapor deposition process.Then, carry out etch-back processing procedure, remove segment conductor material layer.
Then, please refer to Fig. 4 F, in the epitaxial layer 404 of groove 407 both sides, form respectively two body layers 420 with the second conductivity type.Body layer 420 is for example P type body layer.Afterwards, in the body layer 420 of the both sides of groove 407, form respectively two doped regions 422 with the first conductivity type.Doped region 422 is for example N-type heavily doped region.Afterwards, on conductor layer 416 and doped region 422, form dielectric layer 424.Next, form two openings 426 that run through dielectric layer 424 and doped region 422.Then, form conductor layer 428 on dielectric layer 424, wherein conductor layer 428 is inserted opening 426 to be electrically connected with body layer 420.The conductor layer 428 of inserting opening 426 forms conductor connector 427.In other words, conductor layer 428 is electrically connected by conductor connector 427 and body layer 420.Material and the formation method of body layer 420, doped region 422, conductor connector 427 and conductor layer 428 refer to the first embodiment, do not repeat them here.So far, complete the manufacture of the channel grid metal-oxide half field effect transistor 400 of the 4th embodiment.
The structure of channel grid metal-oxide half field effect transistor 400 of the present invention is described with reference to Fig. 4 F below.Please refer to Fig. 4 F, channel grid metal-oxide half field effect transistor 400 comprises N-type substrate 402, N-type epitaxial layer 404, P type body layer 420.Epitaxial layer 204 is configured in substrate 402.Body layer 420 is configured in epitaxial layer 404.In addition, have groove 409 in epitaxial layer 404, have groove 411 in body layer 420, groove 409 is configured in groove 411 belows, and groove 409 and groove 411 composition grooves 407.
Channel grid metal-oxide half field effect transistor 400 also comprises insulating barrier 408a, conductor layer 410b, insulating barrier 412, insulating barrier 414 and conductor layer 416.Conductor layer 410b is configured in groove 409.Insulating barrier 408a is configured between conductor layer 410b and epitaxial layer 404.Insulating barrier 412 is configured in groove 411 and covers conductor layer 410b.That is the width of insulating barrier 412 is more than or equal to the width of conductor layer 410b.In addition, conductor layer 416 is configured in groove 411 and covers insulating barrier 412.Insulating barrier 414 is configured between conductor layer 416 and body layer 420.
Channel grid metal-oxide half field effect transistor 400 also comprises two N-type doped regions 422, a dielectric layer 424, two conductor connectors 427 and conductor layers 428.Doped region 422 is configured in the body layer 420 of both sides of groove 411.Dielectric layer 424 is configured on epitaxial layer 404 and covers conductor layer 416.Conductor layer 428 is configured on dielectric layer 424, and wherein conductor layer 428 is electrically connected by conductor connector 427 and body layer 420.
In the channel grid metal-oxide half field effect transistor 400 of the 4th embodiment, substrate 402 is as drain electrode, and doped region 422 is as source electrode, and conductor layer 416 is as grid, and conductor layer 410b is as covering grid, and insulating barrier 414 is as lock oxide layer.Be noted that especially due to the configuration of covering grid (being conductor layer 410b), can reduce the capacitor C of grid to drain electrode
gdand improve transistorized puncture voltage.In addition, because dielectric layer 412 is configured in grid (being conductor layer 416) to reduce grid (being conductor layer 416) and to cover the coupling effect between grid (being conductor layer 410b), thereby can reduce the capacitor C of grid to source electrode
gs.That is to say, structure of the present invention can reduce the capacitor C of grid to drain electrode simultaneously
gdand the capacitor C of grid to source electrode
gs, effectively to reduce switch cost, lift elements usefulness.
In addition, in first to fourth embodiment, be to take the first conductivity type as N-type, the second conductivity type is that P type is that example illustrates, but the present invention is not as limit.It will be understood by a person skilled in the art that, the first conductivity type can be also P type, and the second conductivity type is N-type.
In sum, in channel grid metal-oxide half field effect transistor of the present invention, will cover gate configuration below grid, and can reduce grid to the capacitor C gd of drain electrode and improve transistorized puncture voltage.In addition, insulating barrier (or dielectric layer) is configured in grid or covers and in grid, can reduce grid and cover the coupling effect between grid, thereby reduces the capacitor C gs of grid to source electrode.Or, by making groove wide at the top and narrow at the bottom, make to reduce at the grid of upper groove and in the coupling effect of covering between grid of lower groove, also can reduce the capacitor C gs of grid to source electrode.In other words, structure of the present invention can reduce capacitor C gd and the grid capacitor C gs to source electrode of grid to drain electrode simultaneously, effectively to reduce switch cost, lift elements usefulness.
Finally it should be noted that: each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit above; Although the present invention is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of various embodiments of the present invention technical scheme.
Claims (17)
1. a channel grid metal-oxide half field effect transistor, is characterized in that, comprising:
There is the substrate of the first conductivity type;
The epitaxial layer with described the first conductivity type, is configured in described substrate;
The body layer with the second conductivity type, is configured in described epitaxial layer, has the first groove in wherein said epitaxial layer, has the second groove in described body layer, and described the first arrangements of grooves is in described the second beneath trenches;
The first conductor layer, is configured in described the first groove;
The first insulating barrier, is configured between described the first conductor layer and described epitaxial layer;
The second conductor layer, is configured on the sidewall of described the second groove;
The second insulating barrier, be configured between described the second conductor layer and described body layer and described the second conductor layer and described the first conductor layer between;
Dielectric layer, is configured on described epitaxial layer and fills up described the second groove; And
Two doped regions with described the first conductivity type, are configured in respectively in the described body layer of both sides of described the second groove.
2. channel grid metal-oxide half field effect transistor according to claim 1, is characterized in that, the thickness of described the second insulating barrier is less than the thickness of described the first insulating barrier.
3. channel grid metal-oxide half field effect transistor according to claim 1, is characterized in that, described the second insulating barrier covers the top of described the first conductor layer.
4. channel grid metal-oxide half field effect transistor according to claim 1, is characterized in that, described the first conductor layer also extends in described the second groove.
5. channel grid metal-oxide half field effect transistor according to claim 1, is characterized in that, the material of described the first conductor layer comprises doped polycrystalline silicon.
6. channel grid metal-oxide half field effect transistor according to claim 1, is characterized in that, the material of described the second conductor layer comprises doped polycrystalline silicon.
7. channel grid metal-oxide half field effect transistor according to claim 1, also comprises one the 3rd conductor layer, is configured on described dielectric layer, it is characterized in that, described the 3rd conductor layer is electrically connected by two conductor connectors and described body layer.
8. channel grid metal-oxide half field effect transistor according to claim 7, is characterized in that, the material of described the 3rd conductor layer comprises metal.
9. channel grid metal-oxide half field effect transistor according to claim 1, is characterized in that, described the first conductivity type is N-type, and described the second conductivity type is P type; Or described the first conductivity type is P type, described the second conductivity type is N-type.
10. a channel grid metal-oxide half field effect transistor, is characterized in that, comprising:
There is the substrate of the first conductivity type;
The epitaxial layer with described the first conductivity type, is configured in described substrate;
The body layer with the second conductivity type, is configured in described epitaxial layer, has the first groove in wherein said epitaxial layer, has the second groove in described body layer, and described the first arrangements of grooves is in described the second beneath trenches;
The first conductor layer, is configured in described the first groove;
The first insulating barrier, is configured between described the first conductor layer and described epitaxial layer;
The second insulating barrier, is configured in described the second groove and covers described the first conductor layer;
The second conductor layer, is configured in described the second groove and covers described the second insulating barrier;
The 3rd insulating barrier, is configured between described the second conductor layer and described body layer;
Dielectric layer, is configured on described epitaxial layer and covers described the second conductor layer; And
Two doped regions with described the first conductivity type, are configured in respectively in the described body layer of both sides of described the second groove.
11. channel grid metal-oxide half field effect transistors according to claim 10, is characterized in that, the thickness of described the 3rd insulating barrier is less than the thickness of described the first insulating barrier.
12. channel grid metal-oxide half field effect transistors according to claim 10, is characterized in that, the width of described the second insulating barrier is greater than the width of described the first conductor layer.
13. channel grid metal-oxide half field effect transistors according to claim 10, is characterized in that, the material of described the first conductor layer comprises doped polycrystalline silicon.
14. channel grid metal-oxide half field effect transistors according to claim 10, is characterized in that, the material of described the second conductor layer comprises doped polycrystalline silicon.
15. channel grid metal-oxide half field effect transistors according to claim 10, also comprise one the 3rd conductor layer, are configured on described dielectric layer, it is characterized in that, described the 3rd conductor layer is electrically connected by two conductor connectors and described body layer.
16. channel grid metal-oxide half field effect transistors according to claim 15, is characterized in that, the material of described the 3rd conductor layer comprises metal.
17. channel grid metal-oxide half field effect transistors according to claim 10, is characterized in that, described the first conductivity type is N-type, and described the second conductivity type is P type; Or described the first conductivity type is P type, described the second conductivity type is N-type.
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| TW101125354A TWI470790B (en) | 2012-07-13 | 2012-07-13 | Trench gate mosfet |
| TW101125354 | 2012-07-13 |
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| CN105552118A (en) * | 2016-03-03 | 2016-05-04 | 安徽省祁门县黄山电器有限责任公司 | Trench gate structure for power device and fabrication method of trench gate structure |
| CN106876279A (en) * | 2017-03-31 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power device and its manufacture method |
| CN108010961A (en) * | 2017-11-30 | 2018-05-08 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
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| CN111599866A (en) * | 2020-05-29 | 2020-08-28 | 电子科技大学 | Low-grid charge power MOSFET device with U-shaped separation grid and manufacturing method thereof |
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| CN114975126A (en) * | 2022-07-29 | 2022-08-30 | 威晟半导体科技(广州)有限公司 | Manufacturing method of shielded gate trench type MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
| CN115036359A (en) * | 2022-08-12 | 2022-09-09 | 无锡新洁能股份有限公司 | Shielding gate groove type MOSFET device and manufacturing method thereof |
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| KR101701240B1 (en) * | 2013-09-20 | 2017-02-01 | 산켄덴키 가부시키가이샤 | Semiconductor device |
| US10818800B2 (en) | 2017-12-22 | 2020-10-27 | Nanya Technology Corporation | Semiconductor structure and method for preparing the same |
| US10615263B2 (en) * | 2018-06-11 | 2020-04-07 | Vanguard International Semiconductor Corporation | Semiconductor devices and methods for forming the same |
| CN111223930A (en) * | 2018-11-26 | 2020-06-02 | 深圳尚阳通科技有限公司 | Shielded gate trench MOSFET |
| CN109888003A (en) * | 2019-03-12 | 2019-06-14 | 电子科技大学 | A kind of power MOS (Metal Oxide Semiconductor) device of separate gate enhancing |
| TWI704606B (en) | 2019-04-24 | 2020-09-11 | 帥群微電子股份有限公司 | Trench power semiconductor device and manufacturing method thereof |
| JP7381335B2 (en) * | 2019-12-26 | 2023-11-15 | 株式会社東芝 | semiconductor equipment |
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| CN106876279A (en) * | 2017-03-31 | 2017-06-20 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power device and its manufacture method |
| CN108010961A (en) * | 2017-11-30 | 2018-05-08 | 上海华虹宏力半导体制造有限公司 | Shield grid groove MOSFET and its manufacture method |
| CN111403341A (en) * | 2020-03-28 | 2020-07-10 | 电子科技大学 | Metal wiring method for reducing gate resistance of narrow control gate structure |
| CN111524976A (en) * | 2020-04-28 | 2020-08-11 | 电子科技大学 | Power MOS device with low grid charge and manufacturing method thereof |
| CN111524976B (en) * | 2020-04-28 | 2021-08-17 | 电子科技大学 | Power MOS device with low grid charge and manufacturing method thereof |
| CN111599866A (en) * | 2020-05-29 | 2020-08-28 | 电子科技大学 | Low-grid charge power MOSFET device with U-shaped separation grid and manufacturing method thereof |
| CN113078210A (en) * | 2021-03-25 | 2021-07-06 | 电子科技大学 | Semiconductor device and manufacturing method thereof |
| CN114975126A (en) * | 2022-07-29 | 2022-08-30 | 威晟半导体科技(广州)有限公司 | Manufacturing method of shielded gate trench type MOSFET (Metal-oxide-semiconductor field Effect transistor) capable of reducing gate charges |
| CN115036359A (en) * | 2022-08-12 | 2022-09-09 | 无锡新洁能股份有限公司 | Shielding gate groove type MOSFET device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150008515A1 (en) | 2015-01-08 |
| US20150008514A1 (en) | 2015-01-08 |
| US20140015041A1 (en) | 2014-01-16 |
| US9035283B2 (en) | 2015-05-19 |
| CN103545368B (en) | 2016-10-26 |
| US9406795B2 (en) | 2016-08-02 |
| TWI470790B (en) | 2015-01-21 |
| TW201403813A (en) | 2014-01-16 |
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