JP5440662B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device, and in particular, a low on-resistance power MOSFET used for an IC that controls a large current with a high withstand voltage, such as a switching power supply IC, an automotive power system driving IC, or a flat panel display driving IC. The present invention relates to a field effect transistor having an insulated gate structure made of a metal-oxide film-semiconductor.

  In recent years, with the rapid spread of portable information devices and the advancement of communication technology, the importance of power ICs with built-in power MOSFETs (field-effect transistors with an insulated gate structure made of metal-oxide-semiconductor) has increased. Yes. A power IC that integrates a lateral power MOSFET and a control circuit is expected to be smaller, lower power consumption, higher reliability, and lower cost than a conventional power MOSFET combined with a control drive circuit. Is done.

  Incidentally, a MOSFET having a trench structure is known as a technique for reducing the device pitch and increasing the degree of integration. Also in the lateral power MOSFET described above, in order to achieve further higher integration and lower on-resistance, trench technology is actively used. FIG. 66 is a cross-sectional view showing a configuration of a lateral power MOSFET (hereinafter referred to as TLPM) to which a conventional trench structure is applied.

  As shown in FIG. 66, an n-type well region 102 is provided as a first conductivity type semiconductor region in the surface region of the p-type semiconductor substrate 101. In the n-type well region 102, two trenches 105 are formed from the substrate surface. In the n-type well region 102, an n-type extended drain region 103 serving as a drift region is formed so as to surround the bottom of each trench 105.

  A high impurity concentration n-type drain region 106 is provided in the substrate surface layer sandwiched between two trenches 105 in the n-type well region 102. In the substrate surface layer outside the two trenches 105 inside the n-type well region 102, p-type offset regions 104 serving as channel regions are provided.

  A high impurity concentration n-type source region 107 is provided in contact with the trench 105 in the substrate surface layer of the p-type offset region 104. A high impurity concentration p-type source region 108 is provided outside the n-type source region 107.

  On the outer side wall of each trench 105, a gate oxide film 113 and a gate electrode 111 serving as a gate insulating film are provided. Further, a field oxide film 114 and a field electrode 112 serving as a field plate insulating film are provided on the sidewalls inside each trench 105. The first interlayer insulating film 115 is filled between the gate electrode 111 and the field electrode 112 in each trench 105.

  Except for a part of each of the n-type source region 107, the p-type source region 108, and the n-type drain region 106, the substrate surface is covered with a second interlayer insulating film 116. The source electrode 110 is electrically connected to the n-type source region 107 and the p-type source region 108 on the surface of the substrate through source plug electrodes 120 and 122 that penetrate the second interlayer insulating film 116. The drain electrode 109 is electrically connected to the n-type drain region 106 on the surface of the substrate through drain plug electrodes 119 and 121 that penetrate the second interlayer insulating film 116.

  FIG. 67 is a cross-sectional view showing a configuration of a TLPM to which a conventional trench structure is applied. The difference from FIG. 66 is that the field oxide film 114 and the field electrode 112 do not exist. Other configurations are the same as those in FIG. 66, and thus description thereof is omitted.

  FIG. 68 is a cross-sectional view showing a configuration of a TLPM to which a conventional trench structure is applied. A difference from FIG. 66 is that an n-type second drain region 117 is formed under the n-type drain region 106. The n-type second drain region 117 has a higher impurity concentration than the n-type extended drain region 103. Other configurations are the same as those in FIG. 66, and thus description thereof is omitted.

  FIG. 69 is a cross-sectional view showing a configuration of a TLPM to which a conventional trench structure is applied. The difference from FIG. 68 is that the field oxide film 114 and the field electrode 112 do not exist. Other configurations are the same as those in FIG.

  Next, a method for manufacturing a TLPM to which the conventional trench structure shown in FIGS. 66 to 69 is applied will be described. Here, the first conductivity type is n-type and the second conductivity type is p-type. 70 to 73 are cross-sectional views showing a structure in the middle of manufacturing the TLPM to which the conventional trench structure shown in FIG. 66 is applied.

  First, as shown in FIG. 70, an n-type well region 102 is formed in a p-type semiconductor substrate 101, and a p-type offset region 104 is formed inside the n-type well region 102. Next, an oxide film 123 is deposited. Then, two trenches 105 are formed using the oxide film 123 as a mask. Then, buffer oxide film 130 is formed, and phosphorus (P31), for example, is ion-implanted as an n-type impurity into the bottom surface of trench 105. Here, the p-type offset region 104 is not formed on the substrate surface between the two trenches 105.

  Next, as shown in FIG. 71, thermal diffusion is performed to form an n-type extended drain region 103 on the bottom surface of the trench 105, and the oxide film 123 and the buffer oxide film 130 are removed. Then, a gate oxide film 113 and a field oxide film 114 are formed on the sidewall of the trench 105. Next, the gate electrode 111 and the field electrode 112 are formed along the gate oxide film 113 and the field oxide film 114, respectively. Subsequently, arsenic (As75), for example, is ion-implanted as an n-type impurity into the substrate surface between the two trenches 105 and the p-type offset region 104 outside the trench 105 using the mask 124.

  72, after removing the mask 124, for example, boron (B11) is ion-implanted as a p-type impurity into the substrate surface outside the trench 105 using the mask 125. As shown in FIG. Next, as shown in FIG. 73, after removing the mask 125, thermal diffusion is performed to form an n-type drain region 106, an n-type source region 107, and a p-type source region 108.

  Subsequently, a first interlayer insulating film 115 and a second interlayer insulating film 116 are sequentially deposited, a contact hole is opened in each interlayer insulating film (115, 116), and an n-type drain region 106, n on the substrate surface is formed. The type source region 107 and the p type source region 108 are exposed. 66. When the drain plug electrodes 119 and 121 and the source plug electrodes 120 and 122 are embedded in the contact holes and the drain electrode 109 and the source electrode 110 are wired, the TLPM shown in FIG. 66 can be obtained.

  Next, a manufacturing method of TLPM to which the conventional trench structure shown in FIG. 67 is applied will be described. The manufacturing method of TLPM shown in FIG. 67 first follows the process of FIG. 70, and then follows the process of FIGS. Then, the process of FIGS. 72 and 73 is followed. Here, description of overlapping processes is omitted, and only the processes of FIGS. 74 and 75 are described.

  After the process shown in FIG. 70, thermal diffusion is performed to form an n-type extended drain region 103 on the bottom surface of the trench 105 as shown in FIG. Next, after removing the oxide film 123 and the buffer oxide film 130, a gate oxide film 113 and a field oxide film 114 are formed on the sidewall of the trench 105. Subsequently, the gate electrode 111 and the field electrode 112 are formed along the gate oxide film 113 and the field oxide film 114, respectively.

  Then, a mask 127 having a pattern covering the gate electrode 111 and having an opening on the field electrode 112 is formed on the substrate surface. Next, as shown in FIG. 75, the field electrode 112 is removed, and, for example, arsenic (As75) is ion-implanted into the region between the two trenches 105 and outside the trenches 105 using the mask 128. Thereafter, the process shown in FIGS. 72 and 73 is followed.

  Next, a manufacturing method of TLPM to which the conventional trench structure shown in FIG. 68 is applied will be described. The manufacturing method of TLPM shown in FIG. 68 first follows the process of FIG. 76, and then follows the process of FIGS. Here, description of overlapping processes is omitted, and only the process of FIG. 76 is described.

  In FIG. 76, an n-type well region 102, a p-type offset region 104, and an n-type second drain region 117 are first formed on the substrate surface of a p-type semiconductor substrate 101. Subsequently, two trenches 105 are formed using the oxide film 129 as a mask. At this time, the trench 105 is formed so that the n-type second drain region 117 is located between the trenches 105. Then, after forming the buffer oxide film 130, for example, phosphorus (P 31) is ion-implanted into the bottom surface of each trench 105. Thereafter, the process shown in FIGS.

  Next, a method for manufacturing a TLPM to which the conventional trench structure shown in FIG. 69 is applied will be described. The TLPM manufacturing method shown in FIG. 69 first follows the process of FIG. 76, and then follows the processes of FIGS. 74 and 75. Further, the process of FIGS. 72 and 73 is followed. Since these steps are the same as those described above, description thereof is omitted.

  In the TLPM to which the conventional trench structure described above is applied, there is no metal plug on the bottom of the trench, so that the depletion layer does not reach the plug defect. For this reason, the leakage and the breakdown voltage do not increase due to reach through, and high reliability can be obtained.

  By the way, it has a source region and a drain region on the surface, a gate electrode in the trench between them, a gate oxide film between the gate electrode and the source region, and a thick oxide between the gate electrode and the drain region. High voltage power transistors having a film have been proposed (see, for example, Patent Document 1 and Patent Document 2 below).

Japanese Patent No. 3348911 US Pat. No. 5,434,435

  However, in the conventional TLPM shown in FIGS. 66 to 69 described above, the drain current is drawn by the substrate between the trenches 105 sandwiched between the two trenches 105. Therefore, in the TLPM shown in FIG. 66, as shown in FIG. 77, the diffusion resistance (R1) generated in the substrate between the trenches 105 determines the on-characteristic. In order to lower the diffusion resistance (R1), an n-type second drain region 117 may be provided under the n-type drain region 106 as shown in FIG. In the case of FIG. 68, as shown in FIG. 78, the diffusion resistance (R2) generated in the substrate between the trenches 105 is small (R2 <R1), but the diffusion resistance (R2) is not sufficiently small. There is a problem that the on-resistance is affected by the diffusion resistance R2.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method that can reduce the contribution of drain diffusion resistance in order to eliminate the above-described problems caused by the prior art.

In order to solve the above-described problems and achieve the object, a semiconductor device manufacturing method according to the present invention includes a trench formed in a surface layer of a semiconductor substrate so that the surface layer of the semiconductor substrate has a first mesa region and a second mesa. A semiconductor device that is divided into regions and in which the first mesa regions and the second mesa regions are alternately arranged, the source current is drawn in the first mesa region, and the drain current is drawn in the second mesa region A first step of forming a well region in a surface layer of the semiconductor substrate; a second step of forming a channel region of a second conductivity type in the well region; and a surface of the semiconductor substrate Forming an etching mask having a trench pattern on the surface, forming the trench in the surface layer of the well region using the etching mask, and forming the surface layer of the semiconductor substrate on the surface of the semiconductor substrate. A third step of dividing the first mesa region into the second mesa region, a fourth step of forming a first drain region of the first conductivity type at the bottom of the trench, and after removing the etching mask, trench, a fifth step of forming a gate insulating film on the side wall along the first mesa region, a sixth step of forming a gate electrode inside the trench along the gate insulating film, wherein A seventh step of filling the trench with a first interlayer insulating film; an eighth step of etching the second mesa region; and the first interlayer insulating film; a surface layer of the first mesa region; A ninth step of forming a first conductivity type source region and a first conductivity type second drain region on the surface layer of the second mesa region; and a substrate surface on which the first interlayer insulating film is formed. 10th process of depositing 2 interlayer insulation films A source contact hole and a drain contact hole are opened in the first interlayer insulating film and the second interlayer insulating film, and the source region and the second drain region are formed through the source contact hole and the drain contact hole. And an eleventh step of forming a source electrode and a drain electrode that are electrically connected to each other.

  In the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, the eighth step includes anisotropically etching the second mesa region and the first interlayer insulating film, and A twelfth step of shadow oxidizing the exposed surface of the mesa region is characterized.

  In the semiconductor device manufacturing method according to the present invention as set forth in the invention described above, the eighth step includes anisotropically etching the first interlayer insulating film and isotropic dry etching of the second mesa region. And a thirteenth step of shadow oxidizing the exposed surface of the second mesa region.

  In the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the ninth step includes masking the second drain region and the first interlayer insulating film etched by the eighth step. As mentioned above, it is formed by ion implantation of impurities.

  The method for manufacturing a semiconductor device according to the present invention includes the fourteenth step of forming a third drain region in the surface layer of the second mesa region in the above-described invention, and is formed by the fourteenth step. The third drain region has the same impurity concentration as the first drain region or a higher impurity concentration than the first drain region, and the third drain region includes the first drain region and the first drain region. It is formed between the two drain regions.

  In the semiconductor device manufacturing method according to the present invention, the third drain region is formed after removing the etching mask in the above-described invention.

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, ion implantation is performed to form the third drain region before the trench is formed.

  In the semiconductor device manufacturing method according to the present invention, the third drain region is formed before the trench is formed in the above-described invention.

  In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the third drain region is formed before the second drain region is formed by etching the second mesa region. And

In order to solve the above-described problems and achieve the object, a semiconductor device manufacturing method according to the present invention includes a trench formed in a surface layer of a semiconductor substrate so that the surface layer of the semiconductor substrate has a first mesa region and a second mesa. A semiconductor device that is divided into regions and in which the first mesa regions and the second mesa regions are alternately arranged, the source current is drawn in the first mesa region, and the drain current is drawn in the second mesa region A first step of forming a well region in a surface layer of the semiconductor substrate, a second step of forming a plurality of second conductivity type channel regions in the well region, and the semiconductor substrate A first etching mask having a trench pattern on the surface is formed, and the two channel regions are straddled on the surface layer of the well region by using the first etching mask. And a second step of forming a first trench, forming a second etching mask having a trench pattern in a central portion of the bottom surface inside the first trench, and using the second etching mask, a second etching mask is formed. A fourth step of dividing the surface layer of the semiconductor substrate into the first mesa region and the second mesa region, and a first conductivity type first drain region at the bottom of the second trench. a fifth step of forming, with the first etching mask, after removing the second etching mask to form the second trench, the gate insulating film on the side wall along the first mesa region 6 and steps, a seventh step of forming a gate electrode inside the second trench along the gate insulating film, the surface of the surface layer and the second mesa region of the first mesa region Each layer has first conductivity An eighth step of forming a source region and a second drain region of the first conductivity type, a ninth step of filling the second trench with an interlayer insulating film, and a source contact hole and a drain contact in the interlayer insulating film And a tenth step of forming a source electrode and a drain electrode that open a hole and are electrically connected to the source region and the second drain region through the source contact hole and the drain contact hole, respectively. It is characterized by.

  The method of manufacturing a semiconductor device according to the present invention includes the eleventh step of forming a third drain region in the surface layer of the second mesa region in the above-described invention, and is formed by the eleventh step. The third drain region has an impurity concentration higher than that of the first drain region, and the third drain region is formed between the first drain region and the second drain region. It is characterized by.

  The method of manufacturing a semiconductor device according to the present invention includes the eleventh step of forming a third drain region in the surface layer of the second mesa region in the above-described invention, and is formed by the eleventh step. The third drain region has the same impurity concentration as that of the first drain region, and the third drain region is formed between the first drain region and the second drain region. It is characterized by being.

  In the method for manufacturing a semiconductor device according to the present invention, the width of the second mesa region is Std, the width of the first trench is Lt1, and the width of the second trench is Lt2. In this case, Lt1 = 2 × Lt2 + Std is satisfied.

  According to the present invention, the depth of the region from which the drain current is drawn can be made deeper than the depth from the substrate surface of the region from which the source current is drawn. Therefore, the on-resistance can be reduced as compared with the prior art.

  Further, according to the present invention, when the field electrode is not present, it is possible to avoid the concentration of the electric field at the corner portion of the trench. Therefore, a high breakdown voltage can be achieved. In addition, the manufacturing process can be simplified. Furthermore, the cost can be reduced.

  According to the semiconductor device manufacturing method of the present invention, the depth of the region from which the drain current is drawn can be made deeper than the depth from the substrate surface of the region from which the source current is drawn. Therefore, the contribution of drain diffusion resistance is reduced, high reliability equivalent to that of the conventional TLPM can be ensured, and the trade-off between on-resistance and breakdown voltage can be improved.

It is sectional drawing which shows the structure of TLPM concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure of TLPM concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure of TLPM concerning Embodiment 3 of this invention. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure of TLPM concerning Embodiment 4 of this invention. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure of TLPM concerning Embodiment 5 of this invention. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. It is sectional drawing shown about TLPM manufactured by applying Embodiment 4 to Embodiment 5. FIG. It is sectional drawing which shows the structure of TLPM concerning Embodiment 6 of this invention. 10 is a cross-sectional view showing a TLPM manufactured by applying Embodiment 6 to Embodiment 2. FIG. 10 is a cross-sectional view showing a TLPM manufactured by applying Embodiment 6 to Embodiment 3. FIG. 10 is a cross-sectional view showing a TLPM manufactured by applying Embodiment 6 to Embodiment 4. FIG. It is sectional drawing which shows the structure of TLPM concerning Embodiment 7 of this invention. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. FIG. 44 is a cross-sectional view illustrating a configuration in the middle of manufacturing the TLPM illustrated in FIG. 43. It is sectional drawing which shows the structure of TLPM concerning Embodiment 8 of this invention. FIG. 57 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM shown in FIG. 56. FIG. 57 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM shown in FIG. 56. FIG. 57 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM shown in FIG. 56. It is sectional drawing which shows the structure of TLPM manufactured when Embodiment 7 is applied to Embodiment 3. FIG. It is sectional drawing which shows the structure of TLPM manufactured when Embodiment 7 is applied to Embodiment 4. FIG. FIG. 61 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM shown in FIG. 60. FIG. 61 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM shown in FIG. 60. FIG. 61 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM shown in FIG. 60. FIG. 61 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM shown in FIG. 60. It is sectional drawing which shows the structure of horizontal type power MOSFET (henceforth TLPM) to which the conventional trench structure is applied. It is sectional drawing which shows the structure of TLPM to which the conventional trench structure is applied. It is sectional drawing which shows the structure of TLPM to which the conventional trench structure is applied. It is sectional drawing which shows the structure of TLPM to which the conventional trench structure is applied. FIG. 67 is a cross-sectional view showing a configuration in the middle of manufacturing a TLPM to which the conventional trench structure shown in FIG. 66 is applied. FIG. 67 is a cross-sectional view showing a configuration in the middle of manufacturing a TLPM to which the conventional trench structure shown in FIG. 66 is applied. FIG. 67 is a cross-sectional view showing a configuration in the middle of manufacturing a TLPM to which the conventional trench structure shown in FIG. 66 is applied. FIG. 67 is a cross-sectional view showing a configuration in the middle of manufacturing a TLPM to which the conventional trench structure shown in FIG. 66 is applied. FIG. 68 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM to which the conventional trench structure shown in FIG. 67 is applied. FIG. 68 is a cross-sectional view showing a configuration in the middle of manufacturing the TLPM to which the conventional trench structure shown in FIG. 67 is applied. FIG. 69 is a cross-sectional view showing a configuration in the middle of manufacturing the conventional TLPM shown in FIG. 68. It is explanatory drawing shown about the diffused resistance (R1) which arises in the board | substrate between trenches. It is explanatory drawing shown about the diffused resistance (R2) which arises in the board | substrate between trenches.

  Exemplary embodiments of a method for manufacturing a semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
First, the configuration of a lateral power MOSFET (hereinafter referred to as TLPM) according to the first embodiment of the present invention will be described. 1 is a cross-sectional view showing a configuration of a TLPM according to a first embodiment of the present invention. As shown in FIG. 1, a well region 2 is provided on the surface of a semiconductor substrate 1 as a first conductivity type semiconductor region. Further, for example, two trenches 5 are formed in the well region 2. The trench 5 is shallower than the well region 2.

  By these trenches 5, the surface layer of the semiconductor substrate 1 is divided into a first mesa region 41 and a second mesa region 42. The first mesa region 41 and the second mesa region 42 are alternately arranged. For example, in the example of FIG. The area to be processed is the second mesa area 42. The second mesa region 42 is deeper from the substrate surface than the first mesa region 41.

  An n-type source region 7 and a p-type source region 8 are provided on the surface layer of the first mesa region 41. The n-type source region 7 is provided in contact with one side wall of the trench 5. An extended drain region 3 is provided on the bottom surface of each trench 5. The extended drain region 3 surrounds the entire bottom surface and part of the side surface of the trench 5 and is shallower than the well region 2. In the first mesa region 41, a p-type offset region 4 is provided between the extended drain region 3 and the n-type source region 7 and the p-type source region 8. In the second mesa region 42, an n-type drain region 6 is provided between the extended drain region 3 and the substrate surface.

  A thin gate oxide film 13 and a field oxide film 14 are provided inside each trench 5. Gate oxide film 13 is provided along the sidewall of trench 5 in contact with p-type offset region 4. The field oxide film 14 is provided along the side wall of the trench 5 in contact with the n-type drain region 6. In each trench 5, a gate electrode 11 and a field electrode 12 are provided inside the gate oxide film 13 and the field oxide film 14, respectively.

  The first interlayer insulating film 15 is provided in the trench 5 and on the first mesa region 41. The second interlayer insulating film 16 is provided on the first interlayer insulating film 15 so as to cover the substrate surface on which the trench 5 is formed. The drain plug electrode 19 is covered with a drain plug electrode (barrier metal) 21 and penetrates through the second interlayer insulating film 16 to electrically connect the drain electrode 9 and the n-type drain region 6.

  Therefore, the semiconductor device of the first embodiment is configured to draw the drain current from the substrate surface between the two trenches 5. The source plug electrode 20 is covered with a source plug electrode (barrier metal) 22, and the source electrode 10, the n-type source region 7 and the p-type source region 8 are electrically connected through the second interlayer insulating film 16. Connected to.

  Next, a manufacturing process of the TLPM shown in FIG. 1 will be described. 2-12 is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. First, the well region 2 is formed in the surface layer of the semiconductor substrate 1. Next, a p-type offset region 4 serving as a channel is formed in the surface layer of the well region 2. Subsequently, an oxide film 23 is formed on the surface of the semiconductor substrate 1.

  Next, using the oxide film 23 as a mask, trench etching is performed to form, for example, two trenches 5 in the surface layer of the well region 2. After the trench 5 is formed, buffer oxidation is performed and a buffer oxide film 30 is formed. Thereafter, for example, phosphorus (P31) is ion-implanted as an n-type impurity into the bottom surface of the trench 5.

  Next, as shown in FIG. 3, thermal diffusion is performed to form the extended drain region 3 on the bottom surface of the trench 5. Subsequently, all of the oxide film 23 and the buffer oxide film 30 on the surface of the substrate are removed, the gate oxide film 13 and the field oxide film 14 are formed on the sidewalls of the trench 5, and the gate oxide film 13 and the field oxide film are further formed inside. A gate electrode 11 and a field electrode 12 made of polysilicon are formed along 14.

  At that time, the gate oxide film 13 and the field oxide film 14 may be formed simultaneously or separately. Further, the gate electrode 11 and the field electrode 12 may be formed simultaneously or separately. Then, for example, arsenic (As75) is ion-implanted as an n-type impurity into the p-type offset region 4 outside the trench 5 using the mask 50.

  After removing the mask 50, for example, boron (B11) is ion-implanted as a p-type impurity in the p-type offset region 4 using a mask 51 as shown in FIG. Note that the ion implantation of arsenic (As75) may be performed after the order of FIGS. 3 and 4 is changed and boron (B11) ion implantation is performed.

  Thereafter, the mask 51 is removed, and as shown in FIG. 5, a first interlayer insulating film 15 is deposited and planarized by, for example, CMP (Chemical Mechanical Polishing). Then, a desired mask 52 is formed on the first interlayer insulating film 15, and the first interlayer insulating film 15 is opened as shown in FIG. Then, after exposing the substrate surface of the substrate between the gate electrode 11, the field electrode 12, and the trench 5, the mask 52 is removed.

  Subsequently, as shown in FIG. 7, the substrate surface of the substrate between the field electrode 12 and the trench 5 is anisotropically etched, for example. Moreover, although the etching shown in FIG. 7 described above is anisotropic etching, isotropic dry etching (for example, CDE: chemical dry etching) may be performed. By performing isotropic etching, the protrusions 40 near the interface 31 can be loosened. Therefore, an effect that generation of particles can be suppressed is expected.

  Further, in the above-described etching, as shown in FIG. 7, the etching is performed so that the height of the substrate between the field electrode 12 and the trench 5 is uniform, but the height does not need to be uniform. Etching of the substrate between the field electrode 12 and the trench 5 may be performed simultaneously or separately.

  By this etching, protrusions 40 are generated near the interface 31 between the field electrode 12 and the field oxide film 14 and near the interface 31 between the substrate 5 and the field oxide film 14 between the trenches 5. Therefore, as shown in FIG. 8, shadow oxidation is performed, and the protrusions 40 near the interface 31 are eliminated. By this shadow oxidation, a shadow oxide film 32 is formed on the field electrode 12 and on the substrate surface between the trenches 5.

  Next, for example, arsenic (As75) is ion-implanted as an n-type impurity into the substrate between the trenches 5 using the first interlayer insulating film 15 as a mask. At this time, since the shadow oxide film 32 on the field electrode 12 is thin, n-type impurities are also ion-implanted onto the field electrode 12, but the influence on the electrical characteristics of the field electrode 12 can be ignored. In addition, since the influence of the electrical characteristics can be ignored in this way, the process of using the resist oxide film is omitted, and the process becomes simple.

  Thereafter, as shown in FIG. 9, thermal diffusion is performed to form an n-type drain region 6, an n-type source region 7, and a p-type source region 8, and a second interlayer insulating film 16 is formed on the surface of the semiconductor substrate 1. accumulate. Next, as shown in FIGS. 10 and 11, the drain contact 35 (FIG. 10) and the source contact 36 (FIG. 11) are formed using the two masks 54 and 55, and the n-type drain region 6 on the substrate surface is formed. The n-type source region 7 and the p-type source region 8 are exposed.

  Finally, as shown in FIG. 12, the drain plug electrodes 19 and 21 and the source plug electrodes 20 and 22 are embedded in the contact holes (35 and 36), and the wiring of the drain electrode 9 and the source electrode 10 is performed by the above process. The TLPM shown in FIG. 1 is completed.

  As described above, according to the first embodiment, since the height of the second mesa region 42 is relatively lower than the height of the first mesa region 41, the on-resistance compared to the conventional TLPM. Can be lowered. Furthermore, a breakdown voltage comparable to that of a conventional TLPM can be expected. Therefore, the trade-off between the withstand voltage and the on-resistance can be greatly improved as compared with the conventional TLPM.

(Embodiment 2)
Next, the configuration of the TLPM according to the second embodiment of the present invention will be described. FIG. 13 is a sectional view showing the structure of the TLPM according to the second embodiment of the present invention. The second embodiment is a modification of the first embodiment. The difference from the first embodiment is only that the field electrode 12 is removed in FIG. Others are the same as the TLPM shown in the first embodiment, and thus the description thereof is omitted.

  Next, a manufacturing process of the TLPM shown in FIG. 13 will be described. 14-20 is sectional drawing which shows the structure in the middle of manufacture of TLPM shown in FIG. The TLPM shown in FIG. 13 first follows a process similar to that shown in FIG. Thereafter, according to the processes of FIGS. 14 to 20 and further to the processes of FIGS. 9 to 12 shown in the first embodiment. Here, the description of the overlapping parts is omitted, and the processes of FIGS. 14 to 20 will be described.

  After the process shown in FIG. 2, as shown in FIG. 14, thermal diffusion is performed to form the extended drain region 3 on the bottom surface of the trench 5. Then, all of the oxide film 23 and the buffer oxide film 30 on the substrate surface are removed, and a gate oxide film 13 and a field oxide film are formed on the inner wall of the trench 5. Furthermore, a gate electrode 11 and a field electrode made of polysilicon are formed along the gate oxide film 13 and the field oxide film. At that time, the gate oxide film 13 and the field oxide film may be formed simultaneously or separately. Further, the gate electrode 11 and the field electrode may be formed simultaneously or separately.

  Next, the field electrode is completely removed by anisotropic etching, for example, using a mask 56 such as an oxide film. Subsequently, as shown in FIG. 15, for example, arsenic (As75) is ion-implanted as an n-type impurity into the p-type offset region 4 outside the trench 5 using a mask 57.

  Subsequently, after removing the mask 57, for example, boron (B11) is ion-implanted as a p-type impurity inside the p-type offset region 4 using the mask 58 as shown in FIG. Note that the ion implantation of arsenic (As75) may be performed after ion implantation of boron (B11) is performed by changing the order of FIGS. Instead of sequentially performing the processes of FIGS. 2, 15, and 16, the field electrode 12 may be removed using a mask after the processes of FIGS.

  Next, as shown in FIG. 17, a first interlayer insulating film 15 is deposited on the surface of the substrate and planarized by, for example, CMP. Then, a desired mask 59 is formed on the first interlayer insulating film 15, and as shown in FIG. 18, the interlayer insulating film 15 is anisotropically etched to expose the substrate surface of the substrate between the trenches 5, for example. Let Subsequently, as shown in FIG. 19, the substrate surface of the substrate between the trenches 5 is anisotropically etched, for example. By this etching, a protrusion 40 is generated near the interface 31.

  Therefore, as shown in FIG. 20, shadow oxidation is performed to form the shadow oxide film 32 and eliminate the protrusions 40. Thereafter, for example, arsenic (As75) is ion-implanted as an n-type impurity into the substrate between the trenches 5 using the first interlayer insulating film 15 as a mask. Subsequent processes follow the processes of FIGS. 9 to 12 of the first embodiment. In addition, although the etching shown in FIG. 19 is anisotropic etching, isotropic dry etching (for example, CDE: chemical dry etching) may be performed. By performing isotropic etching, the protrusions 40 near the interface 31 can be loosened. Therefore, an effect that generation of particles can be suppressed is expected.

  In the TLPM of the second embodiment (FIG. 13), not only the TLPM of the first embodiment (FIG. 1) can be expected by eliminating the field electrode 12, but also the TLPM of the first embodiment (FIG. 13). Compared with 1), the manufacturing process can be greatly simplified. These reasons are shown below.

  As shown in FIG. 7, it is necessary to etch the substrate between the field electrode 12 and the trench 5 using the thin field oxide film 14 as a mask. Further, since the protrusions 40 are sharp, it becomes a cause of generation of particles and the yield is lowered. Furthermore, when the substrate between the field electrode 12 and the trench 5 is etched separately, a mask is necessary, and the accuracy of mask displacement when the mask is installed must be concerned.

  On the other hand, in the second embodiment, as shown in FIG. 18, the first interlayer insulating film 15 only needs to be opened wider than the substrate between the trenches 5, and it is necessary to consider the accuracy of mask displacement. There is no. Furthermore, in the etching process of FIG. 19, only the substrate can be selectively etched by using high selectivity etching (semiconductor substrate 1 / insulating film >> 1). Further, since the protrusions 40 shown in FIG. 7 do not occur, the generation of particles can be greatly suppressed, and the yield is improved.

  For the above reasons, the process can be simplified in the second embodiment as compared with the first embodiment. Further, the yield can be improved and the cost can be greatly reduced. Further, the on-resistance can be lowered similarly to the first embodiment, and the high reliability of the device can be obtained. Further, higher breakdown voltage can be expected than in the first embodiment.

(Embodiment 3)
Next, the configuration of the TLPM according to the third embodiment of the present invention will be described. FIG. 21 is a sectional view showing the structure of the TLPM according to the third embodiment of the present invention. The third embodiment is a modification of the first embodiment. The difference from the first embodiment is that an n-type second drain region 17 is formed under the n-type drain region 6 in FIG. The n-type second drain region 17 has the same impurity concentration as the extended drain region 3 or a higher impurity concentration than the extended drain region 3. Others are the same as the TLPM shown in the first embodiment, and thus the description thereof is omitted.

  Next, a manufacturing process of the TLPM shown in FIG. 21 will be described. 22 and 23 are cross-sectional views showing a configuration during the manufacture of the TLPM shown in FIG. The TLPM shown in FIG. 21 first follows the same process as in FIG. 2 shown in the first embodiment. Thereafter, according to the processes of FIGS. 22 and 23, the processes of FIGS. 4 to 12 shown in the first embodiment are also followed. Here, the description of overlapping parts is omitted, and the processes of FIGS. 22 and 23 will be described.

  After the process shown in FIG. 2, the oxide film 23 and the buffer oxide film 30 on the substrate surface are all removed. Then, a gate oxide film 13 and a field oxide film 14 are formed on the inner wall of the trench 5 as shown in FIG. Further on the inner side, a gate electrode 11 and a field electrode 12 made of polysilicon are formed along the gate oxide film 13 and the field oxide film 14, respectively. At that time, the gate oxide film 13 and the field oxide film 14 may be formed simultaneously or separately. Further, the gate electrode 11 and the field electrode 12 may be formed simultaneously or separately.

  Next, for example, phosphorus (P31) is ion-implanted as an n-type impurity into the substrate between the trenches 5 using a mask 60 such as an oxide film. Then, as shown in FIG. 23, thermal diffusion is performed to form the extended drain region 3 on the bottom surface of the trench 5. Subsequently, an n-type second drain region 17 is formed on the substrate surface of the substrate between the trenches 5. Then, after removing the mask 60, for example, arsenic (As 75) is ion-implanted as an n-type impurity into the p-type offset region 4 outside the trench 5 using the mask 61. Subsequent processes follow the processes of FIGS. 4 to 12 of the first embodiment.

  The n-type second drain region 17 described above may have the same impurity concentration as that of the extended drain region 3 or a higher impurity concentration than that of the extended drain region 3. The n-type second drain region 17 preferably has a higher impurity concentration than the extended drain region 3 in order to lower the diffusion resistance and achieve a lower on-resistance than the TLPM of the first embodiment.

  Next, another manufacturing process of the TLPM shown in FIG. 21 will be described. 24 and 25 are cross-sectional views showing a configuration during the manufacture of the TLPM shown in FIG. 21 may first follow the process of FIGS. 24 and 25, then the process of FIG. 23, and may further follow the process of FIGS. 4 to 12 shown in the first embodiment. Here, the description of overlapping parts is omitted, and the processes of FIGS. 24 and 25 will be described.

  First, as shown in FIG. 24, the well region 2 and the p-type offset region 4 are formed in the surface layer of the semiconductor substrate 1, and the n-type second drain region 17 is formed using the mask 62. For example, phosphorus (P31) is ion-implanted as a type impurity. Next, the mask 62 is removed, and as shown in FIG. 25, the trench 5 is formed using the oxide film 23 as a mask, buffer oxidation is performed, and the buffer oxide film 30 is formed. Then, for example, phosphorus (P31) is ion-implanted as an n-type impurity in the bottom surface of the trench.

  Thereafter, the process of FIGS. 4 to 12 shown in FIG. 23 and the first embodiment may be followed. Thus, by forming the trench 5 after performing the ion implantation for forming the n-type second drain region 17, it is not necessary to consider the accuracy of mask displacement as shown in FIG. The manufacturing process can be further simplified.

  As described above, according to the third embodiment, the same breakdown voltage and high reliability as those of the first embodiment can be obtained, and a low resistance region (n-type second drain region 17) is added. As a result, the on-resistance is lower than in the first embodiment, and the trade-off between the breakdown voltage and the on-resistance is improved.

(Embodiment 4)
Next, the configuration of the TLPM according to the fourth embodiment of the present invention will be described. FIG. 26 is a sectional view showing the structure of the TLPM according to the fourth embodiment of the present invention. The fourth embodiment is an example in which the third embodiment is applied to the second embodiment. The difference from the second embodiment is that an n-type second drain region 17 is formed under the n-type drain region 6. The second drain region 17 has a higher impurity concentration than the extended drain region 3. Others are the same as in FIG.

  Next, a manufacturing process of the TLPM shown in FIG. 26 will be described. 27 and 28 are cross-sectional views showing a configuration during the manufacture of the TLPM shown in FIG. The TLPM shown in FIG. 26 first follows a process similar to that shown in FIG. Then, the process of FIG. 22 of Embodiment 3 is followed. Subsequently, the process of FIGS. 27 and 28 is followed, and the process of FIGS. 4 to 12 shown in the first embodiment is followed. Here, the description of the overlapping parts is omitted, and the processes of FIGS. 27 and 28 will be described.

  After the process shown in FIGS. 2 and 22, thermal diffusion is performed to form the extended drain region 3 on the bottom surface of the trench 5 as shown in FIG. 27. An n-type second drain region 17 is formed on the substrate surface of the substrate between the trenches 5. Subsequently, the gate electrode 11 is covered. Then, using the mask 63 having an opening on the field electrode 12, the field electrode 12 is removed by, for example, anisotropic etching, and the mask 63 is completely removed. Subsequently, as shown in FIG. 28, for example, arsenic (As75) is ion-implanted as an n-type impurity into the n-type offset region 4 outside the trench 5 using a mask 64.

  The n-type second drain region 17 described above may have the same impurity concentration as the extended drain region 3 or may have a higher impurity concentration than the extended drain region 3. However, in order to reduce the diffusion resistance on the substrate between the trenches 5 and to achieve a lower on-resistance than the TLPM of the first embodiment, the n-type second drain region 17 is larger than the extended drain region 3. A high impurity concentration is preferable. Subsequent processes follow the processes of FIGS. 4 to 12 of the first embodiment.

  As described above, according to the fourth embodiment, the same low on-resistance as in the third embodiment can be achieved. Further, since there is no field electrode 12, electrolytic concentration at the corner of the trench 5 on the drain side can be avoided. Therefore, a higher breakdown voltage can be expected as compared with the third embodiment.

(Embodiment 5)
Next, the configuration of the TLPM according to the fifth embodiment of the present invention will be described. FIG. 29 is a sectional view showing the structure of the TLPM according to the fifth embodiment of the present invention. In the third and fourth embodiments, the n-type second drain region 17 is formed before the substrate between the trenches 5 is etched. In the fifth embodiment, after the substrate between the trenches 5 is etched, An n-type second drain region 17 is formed. The difference from the third embodiment is that there is no second interlayer insulating film 16. Others are the same as those in FIG.

  Next, a manufacturing process of the TLPM shown in FIG. 29 will be described. 30 to 37 are cross-sectional views showing a configuration during the manufacture of the TLPM shown in FIG. The TLPM shown in FIG. 29 first follows the same process as in FIG. 2 shown in the first embodiment. Subsequently, the process of FIGS. 30 to 37 is followed, and further, the process of FIGS. 10 to 12 shown in the first embodiment is followed. Here, description of overlapping parts is omitted, and the processes of FIGS. 30 to 37 will be described.

  After the process shown in FIG. 2, the oxide film 23 and the buffer oxide film 30 are removed without performing thermal diffusion on the bottom surface of the trench 5 as shown in FIG. Next, a gate oxide film 13 and a field oxide film 14 are formed on the inner wall of the trench 5. Further on the inner side, a gate electrode 11 and a field electrode 12 made of polysilicon are formed along the gate oxide film 13 and the field oxide film 14, respectively. At that time, the gate oxide film 13 and the field oxide film 14 may be formed simultaneously or separately. Further, the gate electrode 11 and the field electrode 12 may be formed simultaneously or separately.

  Thereafter, only the field electrode 12 is anisotropically etched, for example, using the mask 65 that covers the gate electrode 11 and opens on the field electrode 12. By this etching, a protrusion 40 is generated near the interface 31 between the field electrode 12 and the field oxide film 14. Next, as shown in FIG. 31, shadow oxidation is performed, a shadow oxide film 32 is formed, and the protrusions 40 are eliminated.

  Subsequently, as shown in FIG. 32, the oxide film on the substrate between the trenches 5 is removed, and a mask 66 is formed. Then, as shown in FIG. 33, the substrate surface of the substrate between the trenches 5 is anisotropically etched, for example. This etching produces a protrusion 40.

  Next, as shown in FIG. 34, shadow oxidation is performed to form a shadow oxide film 32, and the protrusions 40 on the substrate between the trenches 5 are eliminated. Subsequently, phosphorus (P31), for example, is ion-implanted as an n-type impurity on the substrate between the trenches 5 using the mask 66 as it is. Subsequently, as shown in FIG. 35, thermal diffusion is performed to simultaneously form the extended drain region 3 on the bottom surface of the trench 5 and the n-type second drain region 17 on the substrate between the trenches 5.

  Then, using another mask 67, for example, arsenic (As75) is ion-implanted as an n-type impurity into the p-type offset region 4 outside the trench 5 at the same time. Subsequently, as shown in FIG. 36, for example, boron (B 11) is ion-implanted as a p-type impurity inside the p-type offset region 4 using a mask 68 different from the mask 67.

  Thereafter, as shown in FIG. 37, thermal diffusion is performed to form an n-type drain region 6, an n-type source region 7, and a p-type source region 8, and a first interlayer insulating film 15 is formed on the surface of the semiconductor substrate 1. Deposit to fill the inside of the trench 5. Thereafter, for example, anisotropic etching is performed to reduce the thickness of the first interlayer insulating film 15 on the substrate between the trenches 5.

  In the example described above, as shown in FIG. 35, thermal diffusion is performed, and the extended drain region 3 and the n-type second drain region 17 are formed simultaneously. This is because both the extended drain region 3 and the n-type second drain region 17 are thermally diffused at a high temperature of 1000 ° C. to 1100 ° C., for example. For this reason, if the thermal diffusion is performed separately, the impurity profile changes, and the desired electrical characteristics may not be obtained.

  The first interlayer insulating film 15 in the trench 5 is buried after the extended drain region 3 and the n-type second drain region 17 are formed. For example, after the first interlayer insulating film 15 is buried, the extended drain region 3 and the n-type second drain region 17 are formed. For this reason, thermal diffusion is performed at a high temperature, and stress and strain are generated, resulting in deterioration of initial characteristics and reliability.

  Next, a case where the fourth embodiment is applied to the fifth embodiment will be described. FIG. 38 is a cross-sectional view showing a TLPM manufactured by applying the fourth embodiment to the fifth embodiment. The difference from FIG. 29 is that there is no field electrode 12. Others are the same as those in FIG.

  Next, a manufacturing process of the TLPM shown in FIG. 38 will be described. The TLPM manufacturing method shown in FIG. 38 first follows the process of FIG. Next, all the field electrodes 12 are removed in the process shown in FIG. Next, the process shown in FIG. 31 is omitted and the process shown in FIG. 32 is followed. Then, according to the process of FIGS. 33-37, the process of FIGS. 10-12 is followed. Since these processes have been described in Embodiment 1 and Embodiment 5 (FIG. 29), they are omitted.

  The TLPM in FIG. 38 has both the effects expected from the TLPM in the fourth embodiment (FIG. 26) and the fifth embodiment (FIG. 29). That is, a high breakdown voltage equivalent to that in the fourth embodiment (FIG. 26) can be expected, and further, a reduction in on-resistance equivalent to that in the fifth embodiment (FIG. 29) can be expected.

(Embodiment 6)
Next, the configuration of the TLPM according to the sixth embodiment of the present invention will be described. FIG. 39 is a sectional view showing the structure of the TLPM according to the sixth embodiment of the present invention. In the first to fifth embodiments, the source region (n-type source region 7, p-type source region 8) is outside the opening end of the trench 5, and the drain region (n-type drain region 6) is formed on the substrate between the trenches 5. In the sixth embodiment, the positional relationship between the source region (n-type source region 7 and p-type source region 8) and the drain region is reversed.

  In FIG. 39, the well region 2 is provided in the surface layer of the semiconductor substrate 1. Inside the well region 2, a trench 5 is formed from the surface of the semiconductor substrate 1. The difference from the first embodiment (FIG. 1) is that the positional relationship between the source region (n-type source region 7 and p-type source region 8) and the drain region is reversed. This is that the height of the region 6 is partially reduced. Further, the positional relationship between the gate oxide film 13 and the field oxide film 14 in the trench 5 is reversed. Furthermore, the positional relationship between the gate electrode 11 and the field electrode 12 is reversed.

  The TLPM manufacturing method shown in FIG. 39 is the same as that in the manufacturing process shown in the first embodiment (FIGS. 2 to 12). The ion implantation, oxidation (buffer oxidation, shadow oxidation), etching, and mask pattern are formed outside the trench. The TLPM of FIG. 39 can be obtained by reversing the rotation of the substrate between the trenches 5.

  A case where the sixth embodiment is applied to the second to fourth embodiments will be described. FIG. 40 is a cross-sectional view showing a TLPM manufactured by applying the sixth embodiment to the second embodiment. FIG. 41 is a cross-sectional view showing a TLPM manufactured by applying the sixth embodiment to the third embodiment. FIG. 42 is a cross-sectional view showing a TLPM manufactured by applying the sixth embodiment to the fourth embodiment. The difference between FIGS. 40 to 42 and FIGS. 13, 21, and 26 is that the positional relationship between the source region (n-type source region 7 and p-type source region 8) and the drain region is reversed. Is a point. These effects can obtain the same effects as the effects shown in the second to fourth embodiments.

(Embodiment 7)
Next, the configuration of the TLPM according to the seventh embodiment of the present invention will be described. In the first to sixth embodiments, the example in which the second mesa region 42 is etched to form a step between the second mesa region 42 and the first mesa region 41 after forming the trench 5 has been described. Then, the trench 5a wider than the trench 5 is formed using the oxide film 23, and the second mesa region 42 and the first mesa region 41 are formed using the step formed by the trench 5a.

  FIG. 43 is a sectional view showing the structure of the TLPM according to the seventh embodiment of the present invention. The difference from the first embodiment (FIG. 1) is that the second interlayer insulating film 16 is not deposited, the position of the drain electrode 9 is relatively lower than the source electrode 10, and the n-type Since the shadow oxide film 32 is not formed on the drain region 6 or the field electrode 12, the rest of the configuration is the same as that shown in FIG.

  Next, a manufacturing process of the TLPM shown in FIG. 43 will be described. 44 to 51 are cross-sectional views showing a structure during the manufacture of the TLPM shown in FIG. First, as shown in FIG. 44, the well region 2 is formed in the surface layer of the semiconductor substrate 1. Subsequently, an oxide film 23 is formed on the substrate surface, and the trench 5a is formed using this as a mask. Here, the width Lt1 of the trench 5a is formed using the width Lt2 of the trench 5 and the width Std of the second mesa region 42 so as to have the following formula (1).

  Lt1 = 2 × Lt2 + Std (1)

  The trenches 5a are formed so as to satisfy the above formula (1). After the trenches 5 are formed, the second mesa regions 42 and the first mesa regions 41 are alternately arranged using the steps of the trenches 5a. This is to prevent the occurrence of constriction on the side wall of the trench 5a. This is to improve the reliability of the device.

  Next, as shown in FIG. 45, shadow oxidation is performed inside the trench 5a to form a shadow oxide film 32. Subsequently, a nitride film 24 is deposited on the surfaces of the oxide film 23 and the shadow oxide film 32, and a mask 69 for forming the trench 5 is formed. Thereafter, as shown in FIG. 46, using the etched nitride film 24 as a mask, the surface of the shadow oxide film 32 inside the trench 5a is etched to expose the bottom surface of the trench 5a. Next, as shown in FIG. 47, the exposed substrate surface of the trench 5 a is etched to form the trench 5.

  Next, as shown in FIG. 48, the exposed substrate surface of the trenches 5 and 5a is buffer-oxidized using the nitride film 24 and the oxide film 23 as a mask. (P31) is ion-implanted. Subsequently, as shown in FIG. 49, thermal diffusion is performed to form the extended drain region 3 on the bottom surface of the trench 5. Then, the oxide film 23 and the nitride film 24 on the substrate surface are removed, and the gate oxide film 13, the field oxide film 14, the gate electrode 11, and the field electrode 12 are formed. Next, arsenic (As75), for example, is implanted as an n-type impurity into the p-type offset region 4 outside the trench 5 using the mask 71.

  Subsequently, after removing the mask 71, for example, boron (B11) is ion-implanted as a p-type impurity into the p-type offset region 4 using a mask 72 as shown in FIG. Subsequently, as shown in FIG. 51, an n-type source region 7, a p-type source region 8, and an n-type drain region 6 are formed, and a first interlayer insulating film 15 is deposited on the substrate surface. Then, a contact hole 45 is opened. Next, when a plug electrode is embedded in each contact hole 45 and metal wiring is provided on the plug electrode, a TLPM shown in FIG. 43 is obtained.

  Next, another manufacturing process of the TLPM shown in FIG. 43 will be described. 52 to 55 are cross-sectional views showing a configuration during the manufacture of the TLPM shown in FIG. In this manufacturing method, first, as shown in FIG. 44, the well region 2 and the trench 5 a are formed in the surface layer of the semiconductor substrate 1. Next, as shown in FIG. 52, shadow oxidation is performed inside the trench 5 a to form a shadow oxide film 32. Subsequently, a nitride film 24 is deposited on the surfaces of the oxide film 23 and the shadow oxide film 32, and patterning is performed to form the trench 5. Specifically, a mask 73 is formed.

  Patterning is performed only on the central portion of the trench 5a. Thereafter, as shown in FIG. 53, using the etched nitride film 24 as a mask, the surface of the shadow oxide film 32 and the nitride film 24 inside the trench 5a are etched to expose the bottom surface of the trench 5a. Next, as shown in FIG. 54, the exposed substrate surface of the trench 5 a is etched to form the trench 5. Then, as shown in FIG. 55, the substrate surface where the trenches 5 and 5a are exposed is buffer-oxidized using the nitride film 24 and the oxide film 23 as a mask, and then further, for example, phosphorus ( P31) is ion-implanted. The subsequent process follows the process shown in FIGS.

  As described above, according to the seventh embodiment, the same effect as the TLPM of the first embodiment (FIG. 1) can be expected. Further, the manufacturing process can be greatly simplified as compared with the first embodiment. In addition, since no protrusion is generated in the manufacturing process, a decrease in yield due to generation of particles can be suppressed, and the manufacturing process can be simplified, so that manufacturing cost can be reduced.

  The process described above eliminates the need to consider the accuracy of mask displacement with respect to the trench 5a, thereby simplifying the process. Further, since no protrusion is generated during the manufacturing process, it is possible to avoid a decrease in yield due to generation of particles. Furthermore, since the process is simplified, the manufacturing cost can be reduced.

(Embodiment 8)
Next, the configuration of the TLPM according to the eighth embodiment of the present invention will be described. In the eighth embodiment, the seventh embodiment is applied to the second embodiment. FIG. 56 is a sectional view showing the structure of the TLPM according to the eighth embodiment of the present invention. In FIG. 56, the difference from the seventh embodiment (FIG. 43) is that there are no field electrode 12 and field oxide film. Others are the same as those of the TLPM shown in the seventh embodiment (FIG. 43), and thus description thereof is omitted.

  Next, a manufacturing process of the TLPM shown in FIG. 56 will be described. 57 to 59 are cross-sectional views showing a structure in the middle of manufacturing the TLPM shown in FIG. The TLPM shown in FIG. 56 first follows a process similar to that shown in FIGS. 44 to 48 described in the seventh embodiment. Thereafter, the process of FIGS. 57 to 59 is followed, and the process of FIGS. 50 and 51 shown in the seventh embodiment is further followed. Here, the description of overlapping parts is omitted, and the processes of FIGS. 57 to 59 will be described.

  After the process shown in FIG. 48, as shown in FIG. 57, thermal diffusion is not performed, and nitride film 24 and oxide film 23 on the substrate surface are removed. Next, a gate oxide film 13 and a field oxide film 14 are formed on the inner wall of the trench 5. Further on the inner side, a gate electrode 11 and a field electrode 12 made of polysilicon are formed along the gate oxide film 13 and the field oxide film 14, respectively. Subsequently, in order to leave the gate electrode 11, a mask 74 is formed so as to cover the surface of the field oxide film 13 and the gate electrode 11.

  Next, as shown in FIG. 58, the field electrode 12 is removed by anisotropic etching, for example. Next, as shown in FIG. 59, thermal diffusion is performed to form the extended drain region 3 on the bottom surface of the trench 5. Subsequently, arsenic (As75), for example, is ion-implanted as an n-type impurity into the substrate between the trenches 5 and the p-type offset region 4 outside the trenches 5 using the mask 75. The subsequent process follows the process shown in FIGS.

  As described above, according to the eighth embodiment, device characteristics similar to those of the second embodiment (FIG. 13) can be obtained. Further, the process can be simplified as in the seventh embodiment. Therefore, the generation of particles is suppressed and the yield is improved.

  Furthermore, the seventh embodiment can be applied to the third and fourth embodiments. FIG. 60 is a cross-sectional view showing a configuration of a TLPM manufactured when the seventh embodiment is applied to the third embodiment. FIG. 61 is a cross-sectional view showing a configuration of a TLPM manufactured when the seventh embodiment is applied to the fourth embodiment.

  60 and 61 differ from FIGS. 43 and 56 in that an n-type second drain region 17 is formed under the n-type drain region 6. Next, a method for manufacturing the TLPM shown in FIG. 60 will be described. First, in accordance with the process of FIG. 44, buffer oxidation is then performed to form a buffer oxide film (not shown). Then, n-type impurities are ion-implanted only into a region that will later become the n-type second drain region 17 (not shown). Next, the process of FIGS. 45 to 51 is followed. Then, a plug electrode may be embedded in the contact hole 45 and metal wiring may be applied thereon.

  Next, a method for manufacturing the TLPM shown in FIG. 61 will be described. First, in accordance with the process of FIG. 44, buffer oxidation is then performed to form a buffer oxide film (not shown). Then, n-type impurities are ion-implanted only into a region that will later become the n-type second drain region 17 (not shown). Next, the processes of FIGS. 45 to 48 are followed, and then the processes of FIGS. 57 to 59 are followed. Subsequently, the process of FIGS. 50 and 51 is followed. Then, a plug electrode may be embedded in the contact hole 45 and metal wiring may be applied thereon.

(Embodiment 9)
Next, the configuration of the TLPM according to the ninth embodiment of the present invention will be described. In the ninth embodiment, the seventh embodiment is applied to the fifth embodiment. In this case, the TLPM shown in FIG. 60 is manufactured. About the structure of TLPM shown in FIG. 60, since the content overlaps, description is abbreviate | omitted.

  Next, a manufacturing process of the TLPM shown in FIG. 60 according to the ninth embodiment will be described. 62 to 64 are cross-sectional views showing a configuration during the manufacture of the TLPM shown in FIG. 60 first follows a process similar to that shown in FIGS. 44 to 47 described in the seventh embodiment. Thereafter, the processes of FIGS. 62 to 64 are followed, and the processes of FIGS. 50 and 51 shown in the seventh embodiment are followed. Here, the description of the overlapping parts is omitted, and the processes of FIGS. 62 to 64 will be described.

  After the process shown in FIG. 47, as shown in FIG. 62, the exposed substrate surface of trenches 5 and 5a is buffer-oxidized using oxide film 23 and nitride film 24 as a mask. For example, phosphorus (P31) is ion-implanted as an impurity. Next, as shown in FIG. 63, the nitride film 24 is removed, and, for example, phosphorus (P31) is ion-implanted as an n-type impurity on the substrate between the trenches 5 using a single mask 76.

  Next, as shown in FIG. 64, the mask 76 is removed and thermal diffusion is performed to form the extended drain region 3 and the n-type second drain region 17 on the bottom surface of the trench 5. Subsequently, a gate oxide film 13 and a field oxide film 14 are formed on the inner wall of the trench 5. Further on the inner side, a gate electrode 11 and a field electrode 12 made of polysilicon are formed along the gate oxide film 13 and the field oxide film 14, respectively.

  Then, for example, arsenic (As75) is ion-implanted as an n-type impurity into the substrate between the trenches 5 using the mask 77. Thereafter, the process shown in FIGS. 50 and 51 is followed. The n-type second drain region 17 described above may have the same impurity concentration as the extended drain region 3 or may have a higher impurity concentration than the extended drain region 3. However, in order to reduce the diffusion resistance on the substrate between the trenches 5 and to achieve a lower on-resistance than the TLPM of the first embodiment, the n-type second drain region 17 is larger than the extended drain region 3. A high impurity concentration is preferable.

  Next, another method for manufacturing the TLPM in FIG. 60 will be described. This manufacturing method can be applied when the n-type second drain region 17 and the extended drain region 3 have the same impurity concentration. This manufacturing method follows the process shown in FIG. 65 in place of the process shown in FIGS.

  Specifically, after the process of FIG. 47, the substrate surface where the trenches 5 and 5a are exposed is buffer-oxidized using only the oxide film 23 as a mask, and then the n-type second drain region 17 and the extended drain are further formed. For example, phosphorus (P31) is ion-implanted as an n-type impurity at the same time on the surface of the substrate where the region 3 is formed. Thereafter, the process of FIG. 64 is followed. In this manufacturing method, the mask can be reduced by one as compared with the processes shown in FIGS. 62 and 63, so that the process can be simplified.

  Moreover, when Embodiment 7 is applied to FIG. 38 of Embodiment 5, TLPM shown in FIG. 61 can be obtained. The configuration and manufacturing method of the TLPM in FIG. 61 are the same as the contents of the eighth embodiment, and thus description thereof is omitted. The device characteristics of FIG. 61 are the same as those of FIG. 60. However, since no protrusions are generated in the manufacturing process, the generation of particles can be suppressed, and the yield can be improved.

  As described above, in the ninth embodiment, device characteristics similar to those in the fifth embodiment (FIG. 29) can be obtained. Further, since no protrusion is generated during the manufacturing process, the generation of particles can be suppressed and the yield is improved.

  As described above, the present invention can be variously modified in the above-described embodiment. For example, in the first to ninth embodiments, the well region 2 may be either n-type or p-type. The semiconductor substrate 1 may be either n-type or p-type. The semiconductor device (TLPM) may have a configuration in which all of p-type and n-type are reversed.

  As described above, according to the manufacturing method of the semiconductor device according to each embodiment, the height of the region where the drain current is drawn can be made lower than the height of the region where the source current is drawn. For this reason, the contribution of the drain diffusion resistance is reduced, high reliability equivalent to that of the conventional TLPM can be ensured, and the trade-off between on-resistance and breakdown voltage can be improved.

  As described above, the method for manufacturing a semiconductor device according to the present invention is useful for a low on-resistance power MOSFET suitable for an integrated circuit that controls a large current with a high breakdown voltage, and in particular, an IC for a switching power supply and an automobile power system drive. This is suitable for power MOSFETs integrated in ICs for flat panel displays and ICs for driving flat panel displays.

1 semiconductor substrate 2 well region 3 extended drain region 4 p-type offset region 5 trench 6 n-type drain region 7 n-type source region 8 p-type source region 9 drain electrode 10 source electrode 11 gate electrode 12 field electrode 13 gate oxide film 14 field Oxide film 15 First interlayer insulating film 16 Second interlayer insulating film 19 Drain plug electrode 20 Source plug electrode 21 Drain plug electrode 22 Source plug electrode

Claims (13)

The surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, A method of manufacturing a semiconductor device in which a source current is drawn in a first mesa region and a drain current is drawn in the second mesa region,
A first step of forming a well region in a surface layer of the semiconductor substrate;
A second step of forming a channel region of a second conductivity type in the well region;
An etching mask having a trench pattern is formed on the surface of the semiconductor substrate, the trench is formed in a surface layer of the well region using the etching mask, and the surface layer of the semiconductor substrate is formed with the first mesa region and the first mesa region. A third step of dividing into two mesa regions;
A fourth step of forming a first drain region of a first conductivity type at the bottom of the trench;
A fifth step of forming a gate insulating film on the sidewall of the trench along the first mesa region after removing the etching mask;
A sixth step of forming a Gate electrode inside the trench along the gate insulating film,
A seventh step of filling the trench with a first interlayer insulating film;
An eighth step of etching the second mesa region and the first interlayer insulating film;
A ninth step of forming a first conductivity type source region and a first conductivity type second drain region in the surface layer of the first mesa region and the surface layer of the second mesa region, respectively;
A tenth step of depositing a second interlayer insulating film on the substrate surface on which the first interlayer insulating film is formed;
A source contact hole and a drain contact hole are opened in the first interlayer insulating film and the second interlayer insulating film, and the source region and the second drain region are respectively formed through the source contact hole and the drain contact hole. An eleventh step of forming a source electrode and a drain electrode to be electrically connected;
A method for manufacturing a semiconductor device, comprising: In the eighth step, the second mesa region and the first interlayer insulating film are anisotropically etched,
The method of manufacturing a semiconductor device according to claim 1, further comprising a twelfth step of performing shadow oxidation on the exposed surface of the second mesa region. In the eighth step, the first interlayer insulating film is anisotropically etched, the second mesa region is isotropically dry etched,
The method of manufacturing a semiconductor device according to claim 1, further comprising a thirteenth step of performing shadow oxidation on the exposed surface of the second mesa region.   The ninth step is characterized in that the second drain region is formed by ion implantation of impurities using the first interlayer insulating film etched in the eighth step as a mask. Item 4. The method for manufacturing a semiconductor device according to any one of Items 1 to 3. A fourteenth step of forming a third drain region in the surface layer of the second mesa region;
The third drain region formed by the fourteenth step has the same impurity concentration as the first drain region or a higher impurity concentration than the first drain region, and the third drain region The method for manufacturing a semiconductor device according to claim 1, wherein the method is formed between the first drain region and the second drain region.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the third drain region is formed after removing the etching mask.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the ion implantation for forming the third drain region is performed before the trench is formed.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the third drain region is formed before the trench is formed.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the third drain region is formed before the second mesa region is etched to form the second drain region. The surface layer of the semiconductor substrate is divided into a first mesa region and a second mesa region by a trench formed in the surface layer of the semiconductor substrate, and the first mesa region and the second mesa region are alternately arranged, A method of manufacturing a semiconductor device in which a source current is drawn in a first mesa region and a drain current is drawn in the second mesa region,
A first step of forming a well region in a surface layer of the semiconductor substrate;
A second step of forming a plurality of second conductivity type channel regions in the well region;
A first etching mask having a trench pattern is formed on the surface of the semiconductor substrate, and a first trench is formed on the surface layer of the well region so as to straddle the two channel regions using the first etching mask. A third step of forming;
A second etching mask having a trench pattern is formed at a central portion of the bottom surface inside the first trench, a second trench is formed using the second etching mask, and a surface layer of the semiconductor substrate is formed on the surface layer of the semiconductor substrate. A fourth step of dividing the first mesa region and the second mesa region;
A fifth step of forming a first drain region of the first conductivity type at the bottom of the second trench;
Said first etching mask, after removing the second etching mask, a sixth step of forming a gate insulating film on said second trenches, the side wall along the first mesa region,
A seventh step of forming a Gate electrode along the gate insulating film on the inside of the second trench,
An eighth step of forming a first conductivity type source region and a first conductivity type second drain region in the surface layer of the first mesa region and the surface layer of the second mesa region, respectively;
A ninth step of filling the second trench with an interlayer insulating film;
A source contact hole and a drain contact hole are opened in the interlayer insulating film, and a source electrode and a drain electrode electrically connected to the source region and the second drain region through the source contact hole and the drain contact hole, respectively. A tenth step of forming;
A method for manufacturing a semiconductor device, comprising: An eleventh step of forming a third drain region in the surface layer of the second mesa region;
The third drain region formed in the eleventh step has an impurity concentration higher than that of the first drain region, and the third drain region includes the first drain region and the second drain region. The method for manufacturing a semiconductor device according to claim 10, wherein the method is formed between the drain region and the drain region. An eleventh step of forming a third drain region in the surface layer of the second mesa region;
The third drain region formed in the eleventh step has the same impurity concentration as the impurity concentration of the first drain region, and the third drain region includes the first drain region and the second drain region. The method of manufacturing a semiconductor device according to claim 10, wherein the method is formed between the semiconductor device and the region.   The width of the second mesa region is Std, the width of the first trench is Lt1, and the width of the second trench is Lt2, and Lt1 = 2 × Lt2 + Std is satisfied. The manufacturing method of the semiconductor device as described in any one of -12.

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